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1. 发明授权

US4944836A Chem-mech polishing method for producing coplanar metal/insulator films on a substrate 失效
标题翻译：用于在基板上制造共面金属/绝缘体膜的化学抛光方法
公开(公告)号：US4944836A
公开(公告)日：1990-07-31
申请号：US791860
申请日：1985-10-28
申请人： Klaus D. Beyer , William L. Guthrie , Stanley R. Makarewicz , Eric Mendel , William J. Patrick , Kathleen A. Perry , William A. Pliskin , Jacob Riseman , Paul M. Schaible , Charles L. Standley
发明人： Klaus D. Beyer , William L. Guthrie , Stanley R. Makarewicz , Eric Mendel , William J. Patrick , Kathleen A. Perry , William A. Pliskin , Jacob Riseman , Paul M. Schaible , Charles L. Standley
IPC分类号： H01L21/3205 , H01L21/304 , H01L21/3105 , H01L21/3213 , H01L21/768
CPC分类号： H01L21/304 , H01L21/31053 , H01L21/32134 , H01L21/7684
摘要： A method is disclosed for producing coplanar metal/insulator films on a substrate according to a chem-mech polishing technique. In one example, a substrate having a patterned insulating layer of dielectric material thereon, is coated with a layer of metal. The substrate is then placed in a parallel polisher and the metal is removed elsewhere except in the holes where it is left intact. This is made possible through the use of an improved selective slurry which removes the metal much faster than the dielectric material. The insulating layer may then be used as an automatic etch stop barrier.In a second example a substrate having a patterned metallic layer is coated with an insulating layer and then subjected to chem-mech polishing. The structure is coplanarized by the chem-mech removal of the insulating material from the high points of the structure at a faster rate than from the lower points. Optional etch stop layers also may be used.
摘要翻译：公开了一种根据化学机械抛光技术在基底上产生共面金属/绝缘体膜的方法。在一个示例中，具有其上的介电材料的图案化绝缘层的衬底被涂覆有金属层。然后将基板放置在平行的抛光机中，并将金属除去在其中保持完整的孔中除去。这通过使用改进的选择性浆料成为可能，其比电介质材料更快地除去金属。然后可以将绝缘层用作自动蚀刻停止屏障。在第二实施例中，具有图案化金属层的基板涂覆有绝缘层，然后进行化学研磨。该结构通过从结构的高点以比从较低点更快的速率化学去除绝缘材料而被共面化。也可以使用可选的蚀刻停止层。

2. 发明授权

US4506435A Method for forming recessed isolated regions 失效
标题翻译：形成凹陷隔离区域的方法
公开(公告)号：US4506435A
公开(公告)日：1985-03-26
申请号：US287468
申请日：1981-07-27
申请人： William A. Pliskin , Jacob Riseman , Joseph F. Shepard
发明人： William A. Pliskin , Jacob Riseman , Joseph F. Shepard
IPC分类号： H01L21/70 , H01L21/31 , H01L21/3105 , H01L21/316 , H01L21/331 , H01L21/76 , H01L21/762 , H01L29/73 , H01L21/95
CPC分类号： H01L21/02145 , H01L21/02266 , H01L21/02271 , H01L21/02282 , H01L21/02304 , H01L21/3105 , H01L21/31604 , H01L21/31608 , H01L21/76232 , H01L21/76237
摘要： A method is described for forming the recessed dielectric isolation in a silicon substrate involves first forming trenches which may be less than about 1 micron in depth in areas of one principal surface of the silicon substrate where isolation is desired. Where, for example, an NPN bipolar transistor structure is planned to be formed it is usually necessary to have a P+ region underneath the recessed dielectric isolation to allow full isolation between the various bipolar transistor devices. A PNP transistor uses an N+ region underneath the isolation. Where a field effect transistor is planned a channel stop can be substituted for the P+ region. Under the circumstance of bipolar devices, the P+ region is formed in the substrate prior to the deposition of an epitaxial layer thereover. The trench formation is caused to be formed through the epitaxial layer and into the P+ regions therein. The surface of the trenches are then oxidized in an oxidizing ambient to form a silicon dioxide layer thereon. A glass is deposited over this principal surface. The glass used has a thermal coefficient of expansion that approximates that of silicon and has a softening temperature of less than about 1200.degree. C. The structure is then heated to a temperature that allows the flow of the deposited glass on the surface so as to fill the trenches. The glass on the principal surface above the trench can be removed by a reactive ion etching method. Alternatively and preferably, the glass is removed from areas other than the immediate area of the trench by lithography and etching techniques followed by a second heating of the structure to cause the glass flow to result in surface planarization.
摘要翻译：描述了一种用于在硅衬底中形成凹陷电介质隔离的方法，包括首先形成在硅衬底的一个主表面的需要隔离的区域中深度小于约1微米的沟槽。其中，例如，计划形成NPN双极晶体管结构，通常需要在凹入的介电隔离之下具有位于各种双极晶体管器件之间的完全隔离的P +区。 PNP晶体管使用隔离下方的N +区。在场效应晶体管被计划的情况下，通道停止可以代替P +区域。在双极器件的情况下，在其外部层沉积之前，在衬底中形成P +区。导致沟槽形成通过外延层形成并进入其中的P +区域。然后在氧化环境中氧化沟槽的表面以在其上形成二氧化硅层。玻璃沉积在该主表面上。所使用的玻璃的热膨胀系数近似于硅，并且具有小于约1200℃的软化温度。然后将该结构加热到允许沉积的玻璃在表面上流动以便填充的温度壕沟可以通过反应离子蚀刻方法去除沟槽上方主表面上的玻璃。或者优选地，通过光刻和蚀刻技术从玻璃的紧邻区域除去玻璃，然后对该结构进行第二次加热以使玻璃流产生表面平坦化。

3. 发明授权

US4492717A Method for forming a planarized integrated circuit 失效
标题翻译：形成平面化集成电路的方法
公开(公告)号：US4492717A
公开(公告)日：1985-01-08
申请号：US287467
申请日：1981-07-27
申请人： William A. Pliskin , Jacob Riseman
发明人： William A. Pliskin , Jacob Riseman
IPC分类号： H01L21/31 , H01L21/3105 , H01L21/316 , H01L21/768 , H01L23/29 , H01L23/31
CPC分类号： H01L21/02126 , H01L21/02266 , H01L21/02282 , H01L21/02304 , H01L21/31051 , H01L21/31604 , H01L21/31608 , H01L21/76819 , H01L23/291 , H01L23/3171 , H01L2924/0002 , H01L2924/09701 , H01L2924/19041
摘要： A method is given for forming a planarized integrated circuit structure just prior to the formation of metallurgy interconnection lines on the integrated circuit. The method begins with the integrated circuit intermediate product having devices formed therein but before interconnection metallurgy has been formed on the principal surface of the product. A glass layer is deposited in a non-conformal way onto the principal surface of the integrated circuit. The glass is chosen to have a thermal coefficient of expansion that approximates that silicon and has a softening temperature of less than about 1200.degree. C. The thermal coefficient of expansion approximates that of silicon to reduce stress problems in the integrated circuit structure. The relatively low softening temperature is required for the next step of heating the structure to cause the flow of glass on the surface of the integrated circuit product to fill in the irregularities therein and to thereby planarize the integrated circuit surface. Openings are then formed through the glass down to the device elements of the integrated circuit. The interconnection metallurgy is formed over the surface of the glass and through the openings of the glass to interconnect the device elements of the integrated circuit. The glass may be deposited by various methods which include the sedimentation methods of spraying, centrifuging and spin-on plus sputtering or evaporation methods.
摘要翻译：给出了在集成电路之前形成冶金互连线之前形成平面化集成电路结构的方法。该方法从其中形成有器件的集成电路中间产品开始，但是在产品的主表面上形成互连冶金之前。玻璃层以非共形方式沉积到集成电路的主表面上。玻璃被选择为具有近似于该硅并具有小于约1200℃的软化温度的热膨胀系数。热膨胀系数近似于硅，以减少集成电路结构中的应力问题。需要相对较低的软化温度来进行下一步加热结构以使集成电路产品的表面上的玻璃流充满其中的凹凸，从而使集成电路表面平坦化。然后通过玻璃将开口形成为集成电路的器件元件。互连冶金形成在玻璃的表面上并且穿过玻璃的开口以互连集成电路的器件元件。玻璃可以通过各种方法沉积，包括喷雾，离心和旋涂加溅射或蒸发方法的沉降方法。

4. 发明授权

US4544576A Deep dielectric isolation by fused glass 失效
标题翻译：熔融玻璃进行深度介电隔离
公开(公告)号：US4544576A
公开(公告)日：1985-10-01
申请号：US287466
申请日：1981-07-27
申请人： Wei-Kan Chu , William A. Pliskin , Jacob Riseman
发明人： Wei-Kan Chu , William A. Pliskin , Jacob Riseman
IPC分类号： H01L21/76 , H01L21/31 , H01L21/3105 , H01L21/316 , H01L21/762
CPC分类号： H01L21/02126 , H01L21/02282 , H01L21/02304 , H01L21/31051 , H01L21/31604 , H01L21/31608 , H01L21/76224 , Y10S438/951
摘要： Deep dielectric isolation zones in a substrate are achieved by forming trenches using reactive ion etching. A glass having a coefficient of thermal expansion closely matching that of the substrate is deposited onto the trench to entirely or partially fill the trench. Deposition can be by sedimentation, centrifugation or spin-on techniques. The structure is then fired until the glass particles fuse into a continuous glass layer and final smoothing if necessary can be accomplished.
摘要翻译：通过使用反应离子蚀刻形成沟槽来实现衬底中的深介电隔离区。将具有与衬底紧密匹配的热膨胀系数的玻璃沉积到沟槽上以完全或部分地填充沟槽。沉积可以通过沉降，离心或旋转技术进行。然后烧结该结构，直到玻璃颗粒熔化成连续的玻璃层，并且可以在必要时进行最终平滑化。

5. 发明授权

US4354309A Method of manufacturing a metal-insulator-semiconductor device utilizing a graded deposition of polycrystalline silicon 失效
标题翻译：利用多晶硅分级沉积制造金属绝缘体半导体器件的方法
公开(公告)号：US4354309A
公开(公告)日：1982-10-19
申请号：US187036
申请日：1980-09-12
申请人： James R. Gardiner , William A. Pliskin , Martin Revitz , Joseph F. Shepard
发明人： James R. Gardiner , William A. Pliskin , Martin Revitz , Joseph F. Shepard
IPC分类号： H01L21/033 , H01L21/3205 , H01L21/3215 , H01L21/336 , H01L29/778 , H01L21/20 , H01L21/225
CPC分类号： H01L29/66575 , H01L21/033 , H01L21/32055 , H01L21/32155 , H01L29/7783 , Y10S438/914
摘要： A method of making a metal-oxide-semiconductor device is disclosed. A thin silicon dioxide insulating layer is formed on the surface of a planar silicon wafer. A first layer of intrinsic polycrystalline silicon is deposited over the dioxide layer, and a second layer of doped polycrystalline silicon is deposited over the intrinsic layer, thereby forming the gate. Subsequent hot processing steps result in diffusion of a portion of the dopant from the doped polycrystalline layer into and throughout the intrinsic layer so as to dope the latter. A metal contact layer is then deposited onto the gate and in superimposed vertical alignment with respect to the thin silicon dioxide insulating layer. The intrinsic nature of the first polycrystalline layer reduces grain growth and void formation in the polycrystalline silicon and thereby prevents the silicon dioxide from being attacked by hydrofluoric acid seeping through voids in the polycrystalline layer during subsequent processing. The yield for the manufacture of devices having thin oxide gates is substantially improved.
摘要翻译：公开了制造金属氧化物半导体器件的方法。在平面硅晶片的表面上形成薄的二氧化硅绝缘层。本征多晶硅的第一层沉积在二氧化层上，并且第二层掺杂多晶硅沉积在本征层上，由此形成栅极。随后的热处理步骤导致掺杂剂的一部分从掺杂多晶层扩散到本征层中并遍及本征层，以便掺杂后者。然后将金属接触层沉积到栅极上并且相对于薄的二氧化硅绝缘层叠加垂直取向。第一多晶层的固有特性减少多晶硅中的晶粒生长和空隙形成，从而防止二氧化硅在随后的处理期间被氢氟酸渗透通过多晶层中的空隙。用于制造具有薄氧化物栅极的器件的产量大大提高。

6. 发明授权

US4249968A Method of manufacturing a metal-insulator-semiconductor utilizing a multiple stage deposition of polycrystalline layers 失效
标题翻译：利用多层沉积多晶层制造金属 - 绝缘体半导体的方法
公开(公告)号：US4249968A
公开(公告)日：1981-02-10
申请号：US974577
申请日：1978-12-29
申请人： James R. Gardiner , William A. Pliskin , Martin Revitz , Joseph F. Shepard
发明人： James R. Gardiner , William A. Pliskin , Martin Revitz , Joseph F. Shepard
IPC分类号： H01L29/78 , H01L21/033 , H01L21/28 , H01L21/336 , H01L29/417 , H01L29/778 , H01L21/20 , H01L21/225
CPC分类号： H01L29/66575 , H01L21/033 , H01L29/7783 , Y10S148/018 , Y10S148/02 , Y10S148/025 , Y10S148/122
摘要： A method of making a metal-oxide-semiconductor device is disclosed. A thin silicon dioxide insulating layer is formed on the surface of a planar silicon wafer. A first layer of intrinsic polycrystalline silicon is deposited over the dioxide layer, and a second layer of doped polycrystalline silicon is deposited over the intrinsic layer, thereby forming the gate. Subsequent hot processing steps result in diffusion of a portion of the dopant from the doped polycrystalline layer into and throughout the intrinsic layer so as to dope the latter. A metal contact layer is then deposited onto the gate and in superimposed vertical alignment with respect to the thin silicon dioxide insulating layer. The instrinsic nature of the first polycrystalline layer reduces grain growth and void formation in the polycrystalline silicon and thereby prevents the silicon dioxide from being attacked by hydrofluoric acid seeping through voids in the polycrystalline layer during subsequent processing. The yield for the manufacture of devices having thin oxide gates is substantially improved.
摘要翻译：公开了制造金属氧化物半导体器件的方法。在平面硅晶片的表面上形成薄的二氧化硅绝缘层。本征多晶硅的第一层沉积在二氧化层上，并且第二层掺杂多晶硅沉积在本征层上，由此形成栅极。随后的热处理步骤导致掺杂剂的一部分从掺杂多晶层扩散到本征层中并遍及本征层，以便掺杂后者。然后将金属接触层沉积到栅极上并且相对于薄的二氧化硅绝缘层叠加垂直取向。第一多晶层的本征性质降低了多晶硅中的晶粒生长和空隙形成，从而防止二氧化硅在随后的处理期间被氢氟酸渗透通过多晶层中的空隙。用于制造具有薄氧化物栅极的器件的产量大大提高。

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