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    • 5. 发明授权
    • Gene participating in low temperature germinability in rice and utilization of the same
    • 基因参与水稻的低温发芽率和利用率
    • US08212112B2
    • 2012-07-03
    • US12676473
    • 2008-09-05
    • Kenji FujinoHiroshi Sekiguchi
    • Kenji FujinoHiroshi Sekiguchi
    • A01H5/00A01H5/10C12N15/29C12N15/63
    • C07K14/415C12N15/8273
    • The present invention provides a gene participating in the low temperature germinability in rice and utilization of the same, and the invention relates to a gene for a low temperature germinability which is an isolated qLTG-3-1 gene from the rice line Italica Livorno, has low temperature germinability and has the base sequence of SEQ ID NO: 1; an amino acid sequence encoded by the gene; a transgenic plant transformed with the gene for the low temperature germinability to improve the low temperature germinability; a method of analyzing low temperature germinability, including analyzing the low temperature germinability of a cultivar by comparing the base sequence of the gene for the low temperature germinability with the genotype of the cultivar; a method of improving the low temperature germinability of rice, including transforming the gene for the low temperature germinability into a rice cultivar to improve the low temperature germinability of the cultivar under low temperature conditions; and a method of analyzing the low temperature germinability of a rice cultivar by utilizing the expression of the gene for the low temperature germinability.
    • 本发明提供参与水稻低温发芽性的基因及其利用,本发明涉及一种低温发芽性基因,该基因是水稻品系Italica Livorno中分离的qLTG-3-1基因,具有 具有低温发芽性,并具有SEQ ID NO:1的碱基序列; 由该基因编码的氨基酸序列; 转基因植物转基因为低温发芽性,提高低温发芽率; 分析低温发芽率的方法,包括通过比较低温发芽能力基因的碱基序列与品种的基因型来分析品种的低温发芽率; 提高水稻低温发芽率的方法,包括将低温发芽基因转化为水稻品种,以提高低温条件下品种的低温发芽率; 以及通过利用该基因表达低温发芽性来分析水稻品种的低温发芽率的方法。
    • 6. 发明授权
    • Display device having angled connector
    • 具有成角度连接器的显示装置
    • US6078137A
    • 2000-06-20
    • US955750
    • 1997-10-22
    • Kazuhiko TojoTatsuya YoshinoHiroto KomatsuKenji Fujino
    • Kazuhiko TojoTatsuya YoshinoHiroto KomatsuKenji Fujino
    • G09F9/30H01J29/92H05K3/32H01J63/04H01J5/50
    • H01J31/126H01J29/92H01J2329/92H05K3/325
    • A display panel which can reduce the number of external terminals for a fluorescent display tube and has its simplified assembled structure difficult to cause conduction failure. The base substrate of the container for a fluorescent display tube protrudes partially outward. Conductors electrically connected to the electrodes inside the container are derived out from the container to electrically connect to the external electrodes on the substrate. Connection terminals are formed on the substrate. The conductive rubber connector includes a non-conductive portion 39 with a nearly L-shaped cross section in which plural conductive fine wires bent in a nearly U-shaped form are buried at predetermined intervals. The fluorescent display tube is mounted on the upper surface of the printed board. The conductive rubber connector is placed at a predetermined position. The fluorescent display tube and the conductive rubber connector are fixed by means of a fixture. The external terminals of the fluorescent display tube is electrically connected to the connection terminals of the printed board via the conductive rubber connector.
    • 可以减少荧光显示管的外部端子数量并且其组装结构简单难以导致导通故障的显示面板。 用于荧光显示管的容器的基底部分向外突出。 与容器内的电极电连接的导体从容器中导出,以电连接到基板上的外部电极。 连接端子形成在基板上。 导电橡胶连接器包括具有大致L形横截面的非导电部分39,其中以预定间隔掩埋以几乎U形的形式弯曲的多个导电细线。 荧光显示管安装在印刷电路板的上表面上。 导电橡胶连接器放置在预定位置。 荧光显示管和导电橡胶连接器通过固定装置固定。 荧光显示管的外部端子通过导电橡胶连接器电连接到印刷电路板的连接端子。
    • 7. 发明授权
    • Data acquisition systems with programmable bit-serial digital signal
processors
    • 具有可编程位串行数字信号处理器的数据采集系统
    • US5349676A
    • 1994-09-20
    • US653935
    • 1991-02-11
    • Steven L. GarverickKenji Fujino
    • Steven L. GarverickKenji Fujino
    • G01R19/00G01R21/00G01R21/133G05B19/042G06F7/544G06F15/78G06F17/10G06F7/68G06F7/70G06F9/302
    • G06F15/7842G05B19/0423G06F7/5443G06F7/5446G01R21/006G05B2219/25254
    • A monolithic integrated circuit as may be used in combination with a plurality of sensors for generating respective sensor output signals, which monolithic integrated circuit includes means for converting each sensor output signal to bit-serial digital format, together with some initial processing circuitry comprising a bit-serial multiply-add processor. This processor includes a bit-serial digital multiplier for multiplying a first digital processor input signal in bit-serial form by a second digital processor input signal to generate a digital product signal, a digital adder for adding a third digital processor input signal to the digital product signal to generate a digital sum signal, and means for supplying a digital processor output signal with bits correspond-ing to those of said digital sum signal. A memory system provides memory for storing program instructions, memory for storing successive values of the second digital processor input signal, memory for storing successive values of the third digital processor input signal, and memory for storing successive values of the digital processor output signal as written into the memory system. The first digital processor input signal can be selected from among the sensor output signals as converted to bit-serial digital format. The second digital processor input signals applied to the bit-serial multiply-add processor are at least at selected times read from the memory system, as are the third digital processor input signals applied to the bit-serial multiply-add processor. A controller retrieves stored program instructions in a prescribed order from the memory for storing program instructions and generates control signals for controlling at least the reading and writing of the memory system, as well as the selecting of the first digital processor input signal.
    • 可以与用于产生各个传感器输出信号的多个传感器组合使用的单片集成电路,该单片集成电路包括用于将每个传感器输出信号转换为位串行数字格式的装置,以及一些初始处理电路,包括一位 - 系列乘法加法处理器。 该处理器包括位串行数字乘法器,用于将位串行形式的第一数字处理器输入信号乘以第二数字处理器输入信号以产生数字乘积信号;数字加法器,用于将第三数字处理器输入信号加到数字 产生信号以产生数字和信号,以及用于向数字处理器输出信号提供与所述数字和信号相对应的位的装置。 存储器系统提供用于存储程序指令的存储器,用于存储第二数字处理器输入信号的连续值的存储器,用于存储第三数字处理器输入信号的连续值的存储器和用于存储数字处理器输出信号的连续值的存储器, 进入内存系统。 可以从传感器输出信号中选择第一个数字处理器输入信号,转换为位串行数字格式。 应用于位串行乘法加法处理器的第二数字处理器输入信号至少在从存储器系统读取的选定时间,以及施加到位串行乘法加法处理器的第三数字处理器输入信号。 控制器从用于存储程序指令的存储器中以规定的顺序检索存储的程序指令,并且生成用于至少控制存储器系统的读取和写入以及第一数字处理器输入信号的选择的控制信号。
    • 8. 发明授权
    • Method and apparatus for examination by nuclear magnetic resonance
    • 用核磁共振检查的方法和装置
    • US4536712A
    • 1985-08-20
    • US528599
    • 1983-09-01
    • Hideto IwaokaKenji FujinoTadashi SugiyamaHiroyuki Matsuura
    • Hideto IwaokaKenji FujinoTadashi SugiyamaHiroyuki Matsuura
    • A61B10/00A61B5/055G01R33/48G01R33/54G01R33/08
    • G01R33/482
    • An examination method and apparatus utilizes a nuclear magnetic resonance technique in which the body of a subject to be examined is placed in a uniform static magnetic field and subjected to an electromagnetic wave having a frequency which induces nuclear magnetic resonance, a magnetic field is also applied to the subject body to specify an area of the body from which nuclear magnetic resonance (NMR) signals are radiated, and such nuclear magnetic resonance signals from the specified body area are received. A first 90.degree. pulse as the electromagnetic wave is applied to the body to excite the same, and then a 180.degree. pulse is applied to the body to produce an echo signal. A second 90.degree. pulse is to the body when the echo signal is maximum to thereby allow a magnetization to return to a state of thermal equilibrium. The foregoing sequence of the steps is repeated at prescribed intervals.
    • 一种检查方法和装置利用核磁共振技术,其中待检查对象的身体被置于均匀的静磁场中并且经受具有诱发核磁共振的频率的电磁波,也施加磁场 指定主体以指定辐射核磁共振(NMR)信号的身体的区域,并且接收来自指定身体区域的这种核磁共振信号。 将第一个90度脉冲作为电磁波施加到身体上以激发它,然后将180度脉冲施加到身体以产生回波信号。 当回波信号最大时,第二个90度脉冲是指身体,从而允许磁化返回到热平衡状态。 以规定的间隔重复上述步骤顺序。