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1. 发明授权

US5203076A Vacuum infiltration of underfill material for flip-chip devices 失效
标题翻译：用于倒装芯片的底部填充材料的真空渗透
公开(公告)号：US5203076A
公开(公告)日：1993-04-20
申请号：US812332
申请日：1991-12-23
申请人： Kingshuk Banerji , Francisco D. Alves , Robert F. Darveaux
发明人： Kingshuk Banerji , Francisco D. Alves , Robert F. Darveaux
IPC分类号： H01L21/56
CPC分类号： H01L21/563 , H01L24/28 , H01L2224/16225 , H01L2224/73203 , H01L2224/73204 , H01L2224/83102 , H01L2224/92125 , H01L2924/01033 , H01L2924/01082 , H01L2924/14 , Y10S428/901 , Y10T29/49144
摘要： A method of attaching an integrated circuit (10) to a substrate (20) starts with electrically interconnecting (14) the integrated circuit on the substrate. Next, a bead of underfill material (22) is provided on the substrate (20) about the periphery (24) of the integrated circuit (10). At least a partial vacuum (34) is then applied to the integrated circuit (10) and the substrate (20) to substantially evacuate the area (18) between the integrated circuit (10) and the substrate (20). Finally, fluid pressure (42) is applied to the integrated circuit (10) and the substrate (20) to force at least a portion of the underfill material (22) into the area (18) between the integrated circuit (10) and the substrate (20).
摘要翻译：将集成电路（10）附接到衬底（20）的方法从将衬底上的集成电路电连接（14）开始。接下来，围绕集成电路（10）的周边（24）在基板（20）上设置有底部填充材料（22）的小珠。至少部分真空（34）然后被施加到集成电路（10）和基板（20），以基本上抽出集成电路（10）和基板（20）之间的区域（18）。最后，将流体压力（42）施加到集成电路（10）和基板（20）以迫使底部填充材料（22）的至少一部分进入集成电路（10）和集成电路（10）之间的区域（18）衬底（20）。

2. 发明授权

US5262674A Chip carrier for an integrated circuit assembly 失效
标题翻译：用于集成电路组件的芯片载体
公开(公告)号：US5262674A
公开(公告)日：1993-11-16
申请号：US866951
申请日：1992-04-09
申请人： Kingshuk Banerji , Kenneth R. Thompson , Francisco D. Alves
发明人： Kingshuk Banerji , Kenneth R. Thompson , Francisco D. Alves
IPC分类号： H01L21/58 , H01L21/60 , H01L23/538 , H01L23/02 , H01L39/02
CPC分类号： H01L24/83 , H01L23/538 , H01L24/32 , H01L2224/05554 , H01L2224/2919 , H01L2224/32057 , H01L2224/48091 , H01L2224/49175 , H01L2224/73265 , H01L2224/8319 , H01L2224/83385 , H01L2224/8385 , H01L24/48 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/0781 , H01L2924/14 , H01L2924/15787
摘要： Epoxy bonding between an IC chip and a chip carrier is strengthened by creating substantially rougher oxidized surfaces within substantially smooth gold surfaces of a die paddle portion of the chip carrier.
摘要翻译： IC芯片和芯片载体之间的环氧粘合通过在芯片载体的芯片桨形部分的基本平滑的金表面内形成基本上较粗糙的氧化表面而被加强。

3. 发明授权

US5152451A Controlled solder oxidation process 失效
标题翻译：控制焊料氧化工艺
公开(公告)号：US5152451A
公开(公告)日：1992-10-06
申请号：US678410
申请日：1991-04-01
申请人： Robert F. Darveaux , Kingshuk Banerji , Francisco da Costa Alves
发明人： Robert F. Darveaux , Kingshuk Banerji , Francisco da Costa Alves
IPC分类号： B23K1/20 , H05K3/34
CPC分类号： B23K1/20 , H05K3/3415 , H05K3/3442 , H05K3/3457 , B23K2201/42 , H05K2201/10636 , H05K2203/0315 , H05K2203/0485 , H05K2203/1105 , H05K2203/1476 , H05K2203/1572 , H05K3/3473 , H05K3/3489 , Y02P70/611 , Y02P70/613
摘要： A method of soldering leadless components to a printed circuit board without using solder paste is disclosed. A thick layer of solder (42) is plated onto a printed circuit board (40), and an oxide layer (43) is formed by heating. Solder flux (45) is applied to those solder pads that are intended to be reflowed, and components (54) are placed. The printed circuit board is heated, and a solder joint (68) is effected between the components (54) and the circuit board (40), while the unfluxed solder pads (66) do not reflow and remain flat. Solder flux is then applied to the remaining solder pads (66) on the same or the opposite side of the circuit board. Additional components (77) are placed, and the circuit board (40) is reflowed a second time.
摘要翻译：公开了一种将无铅组件焊接到印刷电路板而不使用焊膏的方法。将厚的焊料层（42）电镀在印刷电路板（40）上，通过加热形成氧化物层（43）。焊接焊剂（45）被施加到要被回流的那些焊盘，并且部件（54）被放置。印刷电路板被加热，并且在组件（54）和电路板（40）之间实现焊接接头（68），而未焊接的焊盘（66）不回流并保持平坦。然后将焊剂焊剂施加到电路板的相同或相对侧上的剩余焊盘（66）。放置附加部件（77），并且电路板（40）第二次回流。

4. 发明授权

US5623127A Single alloy solder clad substrate 失效
标题翻译：单合金焊包覆基板
公开(公告)号：US5623127A
公开(公告)日：1997-04-22
申请号：US348427
申请日：1994-12-02
申请人： Edwin L. Bradley, III , Kingshuk Banerji , William B. Mullen, III
发明人： Edwin L. Bradley, III , Kingshuk Banerji , William B. Mullen, III
IPC分类号： B23K35/14 , B23K35/26 , H05K3/24 , H05K3/34 , H05K1/02
CPC分类号： B23K35/262 , H05K3/3484 , H05K2203/043 , H05K3/3463
摘要： A solder clad printed circuit board (100) consists of an electrically insulating substrate that has copper circuit traces (105), portions of which are solderable. A substantially planar layer (120) of a soldering composition is fused to the solderable traces, to form a solder pad that is not domed. The layer is composed of a mass of off-eutectic solder particles (115) that are fused together to form an agglomeration (120) having a porous structure. The solder particles are fused together by heating the off-eutectic solder to a temperature that is between the solidus temperature and the liquidus temperature of the solder. The solder is then cooled below the solidus temperature to solidify it.
摘要翻译：焊料包覆印刷电路板（100）由具有铜电路迹线（105）的电绝缘基板组成，其一部分是可焊接的。焊接组合物的基本平坦的层（120）被熔合到可焊接迹线，以形成不是圆顶的焊盘。该层由大量的非共熔焊料颗粒（115）组成，它们被熔合在一起以形成具有多孔结构的附聚物（120）。通过将非共晶焊料加热到固相线温度和焊料的液相线温度之间的温度将焊料颗粒熔合在一起。然后将焊料冷却至固相线温度以使其固化。

5. 发明授权

US5429293A Soldering process 失效
标题翻译：焊接工艺
公开(公告)号：US5429293A
公开(公告)日：1995-07-04
申请号：US358295
申请日：1994-12-19
申请人： Edwin L. Bradley, III , Kingshuk Banerji , Vahid Kazem-Goudarzi
发明人： Edwin L. Bradley, III , Kingshuk Banerji , Vahid Kazem-Goudarzi
IPC分类号： B23K35/02 , B23K35/26 , H05K3/12 , H05K3/34
CPC分类号： H05K3/3463 , B23K35/025 , B23K35/26 , H05K3/3484 , B23K2201/04 , B23K2201/12 , H05K2201/035 , H05K2201/10992 , H05K2203/043 , H05K3/1216
摘要： A soldering process uses two or more different solder alloys. A first solder alloy (115) that undergoes a solid-to-liquid transition at a first temperature is coated (20) onto the solderable surfaces (105) of a printed circuit board (100). A solder paste (120) that undergoes this solid-to-liquid transition at a temperature greater than the first temperature is deposited on the coated solderable potions, and is heated to a temperature that is above the first temperature but below the second temperature. During this time, the first solder alloy liquifies, while the solder paste does not. The first solder alloy wets to the individual particles in the solder paste, and alloys to the solderable surfaces and the solder particles in the solder paste. The soldering composition is subsequently cooled (40) to solidify the first solder material, forming a solid and substantially planar coating on the solderable potions of the printed circuit board.
摘要翻译：焊接工艺使用两种或更多种不同的焊料合金。在第一温度下经历固 - 液过渡的第一焊料合金（115）涂覆（20）到印刷电路板（100）的可焊接表面（105）上。在大于第一温度的温度下经历该固 - 液过渡的焊膏（120）沉积在涂覆的可焊接部分上，并被加热到高于第一温度但低于第二温度的温度。在此期间，第一焊料合金液化，而锡膏不发生。第一焊料合金润湿焊锡膏中的各个颗粒，并将其焊接到可焊接表面和焊膏中的焊料颗粒。焊接组合物随后被冷却（40）以固化第一焊料材料，在印刷电路板的可焊接部分上形成固体和基本上平面的涂层。

6. 发明授权

US5293067A Integrated circuit chip carrier 失效
标题翻译：集成电路芯片载体
公开(公告)号：US5293067A
公开(公告)日：1994-03-08
申请号：US898231
申请日：1992-06-12
申请人： Kenneth R. Thompson , Kingshuk Banerji , William B. Mullen, III
发明人： Kenneth R. Thompson , Kingshuk Banerji , William B. Mullen, III
IPC分类号： H01L23/12 , H01L21/56 , H01L23/32 , H01L23/498 , H01L23/02
CPC分类号： H01L23/49827 , H01L21/563 , H01L2224/16225 , H01L2224/16237 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2924/01004 , H01L2924/15311
摘要： An integrated circuit chip carrier assembly, comprising a semiconductor device (10) having interconnection pads (14) disposed on an active surface (12) of the device. The device (10) is attached by means of electrically conducting bumps (26) to a circuitry pattern (18) on a first side of a circuit carrying substrate (16). The substrate is typically an aramid reinforced organic resin, such as epoxy. The circuitry (18, 20) is electrically connected by conductive through-holes (22) to an array of solder pads on a second side of the substrate. Some or all of the through-holes (22) are covered by the device. The overall length and width of the circuit carrying substrate (16) are each a maximum of about 0.15 inches greater than the equivalent dimensions of the device (10), creating a carrier that is only slightly larger than the semiconductor device itself.
摘要翻译：一种集成电路芯片载体组件，包括具有布置在所述装置的有效表面（12）上的互连焊盘（14）的半导体器件（10）。装置（10）通过导电凸块（26）连接到电路承载衬底（16）的第一侧上的电路图案（18）。基底通常是芳族聚酰胺增强的有机树脂，例如环氧树脂。电路（18,20）通过导电通孔（22）电连接到衬底的第二侧上的焊盘阵列。一些或全部通孔（22）被装置覆盖。电路承载基板（16）的总长度和宽度各自最大大约为装置（10）的等效尺寸约0.15英寸，从而形成仅略大于半导体装置本身的载体。

7. 发明授权

US5415944A Solder clad substrate 失效
标题翻译：焊接基板
公开(公告)号：US5415944A
公开(公告)日：1995-05-16
申请号：US236615
申请日：1994-05-02
申请人： Vahid Kazem-Goudarzi , Edwin L. Bradley, III , Kingshuk Banerji , Henry F. Liebman
发明人： Vahid Kazem-Goudarzi , Edwin L. Bradley, III , Kingshuk Banerji , Henry F. Liebman
IPC分类号： B22F1/00 , B23K35/02 , B23K35/26 , C22C1/04 , H05K3/12 , H05K3/34 , B22F7/00 , H01L23/02
CPC分类号： H05K3/3484 , B22F1/0003 , B23K35/0244 , B23K35/262 , C22C1/04 , H05K2201/0215 , H05K2201/0272 , H05K2203/043 , H05K2203/0568 , H05K3/1216 , H05K3/3452 , H05K3/3463 , Y10T428/12014 , Y10T428/12028 , Y10T428/12063 , Y10T428/12097 , Y10T428/12104 , Y10T428/1216
摘要： A solder-clad printed circuit board (100) has solder particles of one alloy (120) arranged within a matrix of a second solder alloy (115). This arrangement forms a flat structure that is alloyed to the solder pads (105) on the substrate. The solder particles (120) have a predetermined melting temperature and are made from one or more of the following elements: tin, lead, bismuth, indium, copper, antimony, cadmium, arsenic, aluminum, gallium, gold, silver. The second solder alloy (115) is compositionally distinct from the solder particles, and has a melting temperature that is lower than the melting temperature of the solder particles. The solder particles may comprise about 88% by weight, and the second solder alloy may comprise about 12% by weight of the solder cladding.
摘要翻译：焊料包覆印刷电路板（100）具有布置在第二焊料合金（115）的基体内的一种合金（120）的焊料颗粒。这种布置形成了与衬底上的焊盘（105）合金化的平坦结构。焊料颗粒（120）具有预定的熔融温度，并且由以下元素中的一种或多种制成：锡，铅，铋，铟，铜，锑，镉，砷，铝，镓，金，银。第二焊料合金（115）在组成上不同于焊料颗粒，并且具有低于焊料颗粒的熔化温度的熔化温度。焊料颗粒可以包含约88重量％，并且第二焊料合金可以包含约12重量％的焊料包层。

8. 发明授权

US5311059A Backplane grounding for flip-chip integrated circuit 失效
标题翻译：背板接地用于倒装芯片集成电路
公开(公告)号：US5311059A
公开(公告)日：1994-05-10
申请号：US825367
申请日：1992-01-24
申请人： Kingshuk Banerji , Fadia Nounou , William B. Mullen, III
发明人： Kingshuk Banerji , Fadia Nounou , William B. Mullen, III
IPC分类号： H01L23/28 , H01L21/56 , H01L23/12 , H01L23/14 , H01L23/24 , H01L23/58
CPC分类号： H01L23/585 , H01L21/56 , H01L21/563 , H01L23/145 , H01L23/24 , H01L2224/05568 , H01L2224/05573 , H01L2224/056 , H01L2224/16225 , H01L2224/16227 , H01L2224/73203 , H01L2924/01014 , H01L2924/01057 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/15151 , H01L2924/15311
摘要： A semiconductor device package comprises a substrate (20) having a metallization pattern (22) on at least one surface, and a semiconductor device (10) having an active surface (12) and a grounded surface (14) on opposed sides. The semiconductor device is electrically attached to the substrate metallization pattern with the active surface (12) facing the substrate. A polymeric underfill material (30) substantially fills the space between the semiconductor device and the substrate. An electrically conductive material (35) covers the exposed grounded surface (14) of the semiconductor device and at least a portion of the metallization pattern (22), providing electrical connection between the grounded surface of the semiconductor and the metallization pattern (22) on the substrate.
摘要翻译：半导体器件封装包括在至少一个表面上具有金属化图案（22）的衬底（20）和在相对侧上具有有源表面（12）和接地表面（14）的半导体器件（10）。半导体器件电连接到衬底金属化图案，其中有源表面（12）面向衬底。聚合物底部填充材料（30）基本上填充半导体器件和衬底之间的空间。导电材料（35）覆盖半导体器件的暴露的接地表面（14）和金属化图案（22）的至少一部分，在半导体的接地表面和金属化图案（22）之间提供电连接，底物。

9. 发明授权

US5573602A Solder paste 失效
标题翻译：焊膏
公开(公告)号：US5573602A
公开(公告)日：1996-11-12
申请号：US358489
申请日：1994-12-19
申请人： Kingshuk Banerji , Edwin L. Bradley, III
发明人： Kingshuk Banerji , Edwin L. Bradley, III
IPC分类号： B23K35/02 , B23K35/14 , B23K35/26 , H05K3/34 , B23K35/34
CPC分类号： B23K35/262 , B23K35/0244 , B23K35/025 , H05K3/3484 , H05K2201/0218 , H05K3/3463 , Y10T428/12181
摘要： A solder paste is made from solder powder having two different alloys. The individual particles in the solder powder consist of a low melting solder coating (115) that surrounds a nucleus (120) of a higher melting solder. The low melting solder is compositionally distinct from the higher melting solder. The particles are suspended in a matrix of a solder paste vehicle, which may also contain a fluxing agent. In one embodiment of the invention, the low melting solder is an alloy of 43% tin, 43% lead and 14% bismuth, and the higher melting solder is an alloy of 52% tin, and 48% bismuth.
摘要翻译：焊膏由具有两种不同合金的焊料粉末制成。焊料粉末中的单个颗粒由围绕较高熔点焊料的核（120）的低熔点焊料涂层（115）组成。低熔点焊料在组成上不同于较高熔点的焊料。颗粒悬浮在焊膏载体的基质中，焊膏载体也可以含有助熔剂。在本发明的一个实施例中，低熔点焊料是43％锡，43％铅和14％铋的合金，而较高熔点的焊料是52％锡和48％铋的合金。

10. 发明授权

US5535101A Leadless integrated circuit package 失效
标题翻译：无铅集成电路封装
公开(公告)号：US5535101A
公开(公告)日：1996-07-09
申请号：US970901
申请日：1992-11-03
申请人： Barry M. Miles , Frank J. Juskey , Kingshuk Banerji
发明人： Barry M. Miles , Frank J. Juskey , Kingshuk Banerji
IPC分类号： H01L21/56 , H01L23/13 , H01L23/31 , H05K7/10
CPC分类号： H01L23/13 , H01L21/563 , H01L23/3121 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2924/01079 , H01L2924/01087 , H01L2924/15311
摘要： A semiconductor device package comprises an integrated circuit chip (10), a substrate (16), an encapsulant (30), and an organic coupling agent or underfill material (12) disposed between the integrated circuit chip and the first side of the substrate. The chip has a plurality of interconnection pads (14) disposed on an active surface of the chip at some minimum spacing "X." Each of the interconnect pads also has electrically conducting bumps (26) on them. The substrate has a circuit pattern (20) on a first side and an array of solder pads (23) spaced a certain distance apart on an opposite side of the substrate. The distance between these pads is greater than the minimum distance (X) between the interconnect pads on the IC. The circuit pattern is electrically connected to the array of solder pads by plated through holes (22). The length and width of the circuit carrying substrate is substantially greater than the length and width of the integrated circuit chip. The chip is mounted face down to the substrate with the electrically connecting bumps, such that at least some of the plated through holes in the substrate are covered by the chip. The polymeric encapsulant (30) covers the entire chip and substantially all of the first side of the substrate, providing a sealed package.
摘要翻译：半导体器件封装包括集成电路芯片（10），衬底（16），密封剂（30）以及设置在集成电路芯片和衬底的第一侧之间的有机耦合剂或底部填充材料（12）。芯片具有多个布置在芯片的有效表面上的互连焊盘（14），该互连焊盘以一定的最小间距“X” 每个互连焊盘在其上也具有导电凸块（26）。衬底在第一侧具有电路图案（20）和在衬底的相对侧上间隔一定距离的焊盘（23）阵列。这些焊盘之间的距离大于IC上的互连焊盘之间的最小距离（X）。电路图案通过电镀通孔（22）电连接到焊盘阵列。电路承载衬底的长度和宽度远大于集成电路芯片的长度和宽度。芯片通过电连接凸块面向下安装到基板上，使得基板中的至少一些电镀通孔被芯片覆盖。聚合物密封剂（30）覆盖基片的整个芯片和基本上所有的第一侧，提供密封的封装。

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