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    • 6. 发明授权
    • Semiconductor device, method of manufacturing the same and application
thereof
    • 半导体装置及其制造方法及其应用
    • US4293868A
    • 1981-10-06
    • US9968
    • 1979-02-06
    • Takashi IizukaMasayuki Horie
    • Takashi IizukaMasayuki Horie
    • H01L29/73H01L21/331H01L27/07H01L27/082H01L27/02
    • H01L27/0755H01L27/0825Y10S438/983
    • This invention relates to a power transistor which includes a driving transistor and an output transistor in the Darlington connection. This invention has for its object to prevent the power transistor from being destroyed by a surge in such a way that a surge destruction-preventing Zener diode is connected between the base and the collector or the emitter of the power transistor. Especially, it is intended to dispose the Zener diode within a semiconductor substrate together with the power transistor. According to this invention, a p-n junction for the Zener diode is formed between a semiconductor region continuous to a collector region of the transistor and a semiconductor region continuous to a base region thereof. The p-n junction is surrounded by the base region of the transistor, whereby it is formed within a bulk and is prevented from reaching the surface of the semiconductor substrate.
    • 本发明涉及一种在达林顿连接中包括驱动晶体管和输出晶体管的功率晶体管。 本发明的目的是防止功率晶体管被浪涌破坏,使得防止浪涌破坏的齐纳二极管连接在功率晶体管的基极和集电极或发射极之间。 特别地,旨在将齐纳二极管与功率晶体管一起配置在半导体衬底内。 根据本发明,用于齐纳二极管的p-n结形成在与晶体管的集电极区域连续的半导体区域和与其基极区域连续的半导体区域之间。 p-n结被晶体管的基极区域包围,从而形成在体内并被防止到达半导体衬底的表面。
    • 7. 发明授权
    • 64B/66B Encoding data generation method and circuit
    • 64B / 66B编码数据生成方法和电路
    • US07463169B2
    • 2008-12-09
    • US11877831
    • 2007-10-24
    • Masayuki HorieYukio Suda
    • Masayuki HorieYukio Suda
    • H03M7/00
    • H03M7/04
    • In a more effective data generation method and circuit used for 64B/66B encoding, when packet data, and head and tail information of the data packet are received, write user data in which a head and tail identifying bytes are respectively added to a head and a tail of the packet data based on the head and tail information is associated with control data indicating positions of both of the identifying bytes to be written in a memory sequentially from a predetermined address of the memory. From the predetermined address, user data by 8 bytes and the control data corresponding to the user data are sequentially read to be provided to a 64B/66B encoding circuit. During a period in which the reading can not be made, idle bytes for 8n bytes (n≧1) and control data indicating the idle bytes, or maintenance user data of 8n bytes (n≧2) in which the head and tail identifying bytes are respectively added to a head and a tail of the maintenance information and control data indicating positions of both of the identifying bytes are provided to the 64B/66B encoding circuit.
    • 在用于64B / 66B编码的更有效的数据生成方法和电路中,当分组数据和数据分组的头尾信息被接收时,写入将头尾识别字节分别添加到头部的用户数据, 基于头尾信息的分组数据的尾部与从存储器的预定地址顺序地指示要写入存储器的两个识别字节的位置的控制数据相关联。 从预定地址,按8字节的用户数据和对应于用户数据的控制数据被顺序读取以提供给64B / 66B编码电路。 在不能进行读取的期间,8n字节(n> = 1)的空闲字节和指示空闲字节的控制数据,或8n字节(n> = 2)的维护用户数据,其中头和尾 识别字节分别被添加到维护信息的头部和尾部,并且指示两个标识字节的位置的控制数据被提供给64B / 66B编码电路。
    • 8. 发明申请
    • 64B/66B Encoding Data Generation Method and Circuit
    • 64B / 66B编码数据生成方法与电路
    • US20080100481A1
    • 2008-05-01
    • US11877831
    • 2007-10-24
    • Masayuki HorieYukio Suda
    • Masayuki HorieYukio Suda
    • H03M5/00
    • H03M7/04
    • In a more effective data generation method and circuit used for 64B/66B encoding, when packet data, and head and tail information of the data packet are received, write user data in which a head and tail identifying bytes are respectively added to a head and a tail of the packet data based on the head and tail information is associated with control data indicating positions of both of the identifying bytes to be written in a memory sequentially from a predetermined address of the memory. From the predetermined address, user data by 8 bytes and the control data corresponding to the user data are sequentially read to be provided to a 64B/66B encoding circuit. During a period in which the reading can not be made, idle bytes for 8n bytes (n≧1) and control data indicating the idle bytes, or maintenance user data of 8n bytes (n≧2) in which the head and tail identifying bytes are respectively added to a head and a tail of the maintenance information and control data indicating positions of both of the identifying bytes are provided to the 64B/66B encoding circuit.
    • 在用于64B / 66B编码的更有效的数据生成方法和电路中,当分组数据和数据分组的头尾信息被接收时,写入将头尾识别字节分别添加到头部的用户数据, 基于头尾信息的分组数据的尾部与从存储器的预定地址顺序地指示要写入存储器的两个识别字节的位置的控制数据相关联。 从预定地址,按8字节的用户数据和对应于用户数据的控制数据被顺序读取以提供给64B / 66B编码电路。 在不能进行读取的期间,8n字节(n> = 1)的空闲字节和指示空闲字节的控制数据,或8n字节(n> = 2)的维护用户数据,其中头和尾 识别字节分别被添加到维护信息的头部和尾部,并且指示两个标识字节的位置的控制数据被提供给64B / 66B编码电路。
    • 9. 发明授权
    • Frame buffer monitoring method and device
    • 帧缓冲区监控方法和设备
    • US07978704B2
    • 2011-07-12
    • US11443243
    • 2006-05-31
    • Shiuji SakakuraYasuhiro OobaYukio SudaMasayuki Horie
    • Shiuji SakakuraYasuhiro OobaYukio SudaMasayuki Horie
    • H04L12/28
    • H04L49/555H04L49/30
    • In a frame buffer monitoring method and device, information concerning a received frame is extracted, and a monitoring frame added to a start of the frame is written in a FIFO buffer. When the monitoring frame is read from the FIFO buffer, expectation information is generated from the information concerning the frame added to the start of the monitoring frame read, the expectation information is compared with the information concerning the frame included in the frame within the monitoring frame read, and whether or not the expectation information is consistent with the information concerning the frame is determined. As a result of the comparison, when it is determined that the expectation information is not consistent with the information concerning the frame, e.g. bits of an FCS within the frame which is determined to be inconsistent are inverted to be transmitted to a subsequent stage as a discarded frame or the frame is discarded. Also, a write destination address and a read source address for the FIFO buffer are initialized.
    • 在帧缓冲器监视方法和装置中,提取关于接收到的帧的信息,并且将添加到帧的开始的监视帧写入FIFO缓冲器。 当从FIFO缓冲器读取监视帧时,根据从读取的监视帧开始的相关信息产生预期信息,将期望信息与监视帧内的帧中包含的帧的信息进行比较 读取,以及期望信息是否与关于帧的信息一致。 作为比较的结果,当确定期望信息与关于帧的信息不一致时,例如, 被确定为不一致的帧内的FCS的比特被反转以作为丢弃的帧被发送到后一级,或者丢弃该帧。 此外,初始化FIFO缓冲器的写目的地地址和读源地址。
    • 10. 发明申请
    • Frame buffer monitoring method and device
    • 帧缓冲区监控方法和设备
    • US20070189314A1
    • 2007-08-16
    • US11443243
    • 2006-05-31
    • Shiuji SakakuraYasuhiro OobaYukio SudaMasayuki Horie
    • Shiuji SakakuraYasuhiro OobaYukio SudaMasayuki Horie
    • H04L12/56
    • H04L49/555H04L49/30
    • In a frame buffer monitoring method and device, information concerning a received frame is extracted, and a monitoring frame added to a start of the frame is written in a FIFO buffer. When the monitoring frame is read from the FIFO buffer, expectation information is generated from the information concerning the frame added to the start of the monitoring frame read, the expectation information is compared with the information concerning the frame included in the frame within the monitoring frame read, and whether or not the expectation information is consistent with the information concerning the frame is determined. As a result of the comparison, when it is determined that the expectation information is not consistent with the information concerning the frame, e.g. bits of an FCS within the frame which is determined to be inconsistent are inverted to be transmitted to a subsequent stage as a discarded frame or the frame is discarded. Also, a write destination address and a read source address for the FIFO buffer are initialized.
    • 在帧缓冲器监视方法和装置中,提取关于接收到的帧的信息,并且将添加到帧的开始的监视帧写入FIFO缓冲器。 当从FIFO缓冲器读取监视帧时,根据从读取的监视帧开始的相关信息产生预期信息,将期望信息与监视帧内的帧中包含的帧的信息进行比较 读取,以及期望信息是否与关于帧的信息一致。 作为比较的结果,当确定期望信息与关于帧的信息不一致时,例如, 被确定为不一致的帧内的FCS的比特被反转以作为丢弃的帧被发送到后一级,或者丢弃该帧。 此外,初始化FIFO缓冲器的写目的地地址和读源地址。