专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07598615B2 Analytic structure for failure analysis of semiconductor device having a multi-stacked interconnection structure 有权
标题翻译：具有多堆叠互连结构的半导体器件的故障分析的分析结构
公开(公告)号：US07598615B2
公开(公告)日：2009-10-06
申请号：US11346678
申请日：2006-02-03
申请人： Ki-Am Lee , Jong-Hyun Lee
发明人： Ki-Am Lee , Jong-Hyun Lee
IPC分类号： H01L23/485 , H01L23/528
CPC分类号： H01L27/1104 , H01L27/11
摘要： In an analytic structure for failure analysis of a semiconductor device, a plurality of analytic regions are arranged in regions of a semiconductor substrate. A plurality of semiconductor transistors having an array structure are arranged in each of the analytic regions. A plurality of interconnection structures connect the semiconductor transistors, each comprising multiple layered metal patterns and multiple layered plugs interposed between the multiple layered metal patterns. A first number of layers of the multiple layered metal patterns and multiple layered plugs is different in one of the analytic regions than a second number of layers of the multiple layered metal patterns and multiple layered plugs in another one of the analytic regions.
摘要翻译：在用于半导体器件的故障分析的分析结构中，多个分析区域布置在半导体衬底的区域中。在每个分析区域中布置有具有阵列结构的多个半导体晶体管。多个互连结构连接半导体晶体管，每个半导体晶体管包括多层金属图案和插入在多层金属图案之间的多个分层插塞。在多个分层金属图案和多个分层塞子的第一层中，一个分析区域中的多层金属图案的第二数量层和另一个分析区域中的多个分层塞子是不同的。

2. 发明申请

US20060118784A1 Structure and method for failure analysis in a semiconductor device 有权
标题翻译：半导体器件故障分析的结构和方法
公开(公告)号：US20060118784A1
公开(公告)日：2006-06-08
申请号：US11291242
申请日：2005-11-30
申请人： Ki-Am Lee , Sang-Deok Kwon , Jong-Hyun Lee
发明人： Ki-Am Lee , Sang-Deok Kwon , Jong-Hyun Lee
IPC分类号： H01L23/58
CPC分类号： G01R31/2884
摘要： In a method and structure for semiconductor failure analysis, the structure comprises: a plurality of analytic fields disposed on a predetermined area of a semiconductor device; semiconductor transistors arranged in each of the analytic fields, the semiconductor transistors arranged in an array; wordlines arranged on each of the plurality of the analytic fields, connecting the semiconductor transistors with each other in a first direction; and bitline structures on each of the plurality of the analytic fields, connecting the semiconductor transistors with each other in a second direction, wherein the bitline structures are configured in different patterns in each of the plurality of analytic fields.
摘要翻译：在半导体故障分析的方法和结构中，该结构包括：设置在半导体器件的预定区域上的多个分析场; 布置在每个分析场中的半导体晶体管，排列成阵列的半导体晶体管; 布置在多个分析场中的每一个上的字线，在第一方向上将半导体晶体管彼此连接; 以及在所述多个分析场中的每一个上的位线结构，在第二方向上将所述半导体晶体管彼此连接，其中所述位线结构在所述多个分析场中的每一个中被配置为不同的图案。

3. 发明申请

US20060175668A1 Analytic structure for failure analysis of semiconductor device 有权
标题翻译：半导体器件故障分析分析结构
公开(公告)号：US20060175668A1
公开(公告)日：2006-08-10
申请号：US11346678
申请日：2006-02-03
申请人： Ki-Am Lee , Jong-Hyun Lee
发明人： Ki-Am Lee , Jong-Hyun Lee
IPC分类号： H01L29/76
CPC分类号： H01L27/1104 , H01L27/11
摘要： In an analytic structure for failure analysis of a semiconductor device, a plurality of analytic regions are arranged in regions of a semiconductor substrate. A plurality of semiconductor transistors having an array structure are arranged in each of the analytic regions. A plurality of interconnection structures connect the semiconductor transistors, each comprising multiple layered metal patterns and multiple layered plugs interposed between the multiple layered metal patterns. A first number of layers of the multiple layered metal patterns and multiple layered plugs is different in one of the analytic regions than a second number of layers of the multiple layered metal patterns and multiple layered plugs in another one of the analytic regions.
摘要翻译：在用于半导体器件的故障分析的分析结构中，多个分析区域布置在半导体衬底的区域中。在每个分析区域中布置有具有阵列结构的多个半导体晶体管。多个互连结构连接半导体晶体管，每个半导体晶体管包括多层金属图案和插入在多层金属图案之间的多个分层插塞。在多个分层金属图案和多个分层塞子的第一层中，一个分析区域中的多层金属图案的第二数量层和另一个分析区域中的多个分层塞子是不同的。

4. 发明授权

US07468530B2 Structure and method for failure analysis in a semiconductor device 有权
标题翻译：半导体器件故障分析的结构和方法
公开(公告)号：US07468530B2
公开(公告)日：2008-12-23
申请号：US11291242
申请日：2005-11-30
申请人： Ki-Am Lee , Sang-Deok Kwon , Jong-Hyun Lee
发明人： Ki-Am Lee , Sang-Deok Kwon , Jong-Hyun Lee
IPC分类号： H01L29/74
CPC分类号： G01R31/2884
摘要： In a method and structure for semiconductor failure analysis, the structure comprises: a plurality of analytic fields disposed on a predetermined area of a semiconductor device; semiconductor transistors arranged in each of the analytic fields, the semiconductor transistors arranged in an array; wordlines arranged on each of the plurality of the analytic fields, connecting the semiconductor transistors with each other in a first direction; and bitline structures on each of the plurality of the analytic fields, connecting the semiconductor transistors with each other in a second direction, wherein the bitline structures are configured in different patterns in each of the plurality of analytic fields.
摘要翻译：在半导体故障分析的方法和结构中，该结构包括：设置在半导体器件的预定区域上的多个分析场; 布置在每个分析场中的半导体晶体管，排列成阵列的半导体晶体管; 布置在多个分析场中的每一个上的字线，在第一方向上将半导体晶体管彼此连接; 以及在所述多个分析场中的每一个上的位线结构，在第二方向上将所述半导体晶体管彼此连接，其中所述位线结构在所述多个分析场中的每一个中被配置为不同的图案。

5. 发明申请

US20080094053A1 Test circuits having ring oscillators and test methods thereof 审中-公开
标题翻译：具有环形振荡器的测试电路及其测试方法
公开(公告)号：US20080094053A1
公开(公告)日：2008-04-24
申请号：US11889418
申请日：2007-08-13
申请人： Yong-Woon Han , Ki-Am Lee
发明人： Yong-Woon Han , Ki-Am Lee
IPC分类号： G01R23/02
CPC分类号： G01R31/31727
摘要： In a test circuit, an oscillation signal is generated based on a design rule pattern of a chip formed on a wafer. The oscillation signal is counted using a counter, and an N-bit signal is generated from the counting of the oscillation signal. The N-bit signal is serialized and output. In a test method, an oscillation signal is generated based on a design rule pattern of a chip formed on a wafer. The oscillation signal is counted, and an N-bit signal is generated based on the counting of the oscillation signal. The N-bit signal is serialized and output.
摘要翻译：在测试电路中，基于晶片上形成的芯片的设计规则图案产生振荡信号。使用计数器对振荡信号进行计数，并且从振荡信号的计数产生N位信号。 N位信号被序列化并输出。在测试方法中，基于在晶片上形成的芯片的设计规则图案产生振荡信号。对振荡信号进行计数，并根据振荡信号的计数产生N位信号。 N位信号被序列化并输出。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式