专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07703055B2 Method and system for enhancing yield of semiconductor integrated circuit devices using systematic fault rate of hole 有权
标题翻译：使用系统故障率提高半导体集成电路器件产量的方法和系统
公开(公告)号：US07703055B2
公开(公告)日：2010-04-20
申请号：US11698029
申请日：2007-01-26
申请人： Choel-hwyi Bae , Sang-deok Kwon , Min-geon Cho , Gwang-hyeon Baek
发明人： Choel-hwyi Bae , Sang-deok Kwon , Min-geon Cho , Gwang-hyeon Baek
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： A method of enhancing yield of semiconductor integrated circuit includes determining multiple experimental values, each experimental value corresponding to a distance from a side of a hole to an opposing side of a shape surrounding the hole, forming test patterns representing each of the experimental values on a wafer and calculating experimental value-based systematic fault rates from the test patterns; converting the experimental value-based systematic fault rates of the hole into the experimental value-based systematic fault rates, calculating a length of a side of the hole for which a distance between the side of the hole and the opposing side of the shape corresponds to each of experimental values, and calculating a systematic fault rate of the hole using the experimental value-based systematic fault rates per unit hole length and the length of the sides of the hole calculated for the respective experimental values in the desired layout.
摘要翻译：提高半导体集成电路的产量的方法包括确定多个实验值，每个实验值对应于从孔的一侧到围绕孔的形状的相对侧的距离，形成表示每个实验值的测试图案并从测试模式中计算基于实验值的系统故障率; 将孔的实验值系统故障率转换为基于实验值的系统故障率，计算孔的侧面与形状的相对侧之间的距离对应于孔的一侧的长度每个实验值，并且使用每个单位孔长度的实验值系统故障率和针对所需布局中的各个实验值计算的孔的边的长度来计算孔的系统故障率。

2. 发明申请

US20070118824A1 METHODS, SYSTEMS, AND COMPUTER PROGRAM PRODUCTS FOR IMPROVING YIELD IN INTEGRATED CIRCUIT DEVICE FABRICATION AND RELATED DEVICES 审中-公开
标题翻译：用于改善集成电路设备制造和相关设备中的功率的方法，系统和计算机程序产品
公开(公告)号：US20070118824A1
公开(公告)日：2007-05-24
申请号：US11560006
申请日：2006-11-15
申请人： Choel-hwyi Bae , Sang-deok Kwon , Gwang-hyeon Baek
发明人： Choel-hwyi Bae , Sang-deok Kwon , Gwang-hyeon Baek
IPC分类号： G06F17/50 , G06F19/00
CPC分类号： G06F17/504 , G06F17/5068
摘要： A method of improving yield in integrated circuit device fabrication includes calculating a fault rate for a design rule based on a plurality failure rates for a corresponding plurality of Design Of Experiment (DOE) rule values and based on numbers of features in a layout of interest corresponding to ones of the plurality of DOE rule values. The layout of interest is corrected based on the fault rate for the design rule. Related systems and devices are also discussed.
摘要翻译：一种在集成电路器件制造中提高产量的方法包括基于相应的多个设计实验（DOE）规则值的多个故障率并基于感兴趣的布局中的特征的数量来计算设计规则的故障率到多个DOE规则值中的一个。感兴趣的布局根据设计规则的故障率进行更正。还讨论了相关系统和设备。

3. 发明授权

US07468530B2 Structure and method for failure analysis in a semiconductor device 有权
标题翻译：半导体器件故障分析的结构和方法
公开(公告)号：US07468530B2
公开(公告)日：2008-12-23
申请号：US11291242
申请日：2005-11-30
申请人： Ki-Am Lee , Sang-Deok Kwon , Jong-Hyun Lee
发明人： Ki-Am Lee , Sang-Deok Kwon , Jong-Hyun Lee
IPC分类号： H01L29/74
CPC分类号： G01R31/2884
摘要： In a method and structure for semiconductor failure analysis, the structure comprises: a plurality of analytic fields disposed on a predetermined area of a semiconductor device; semiconductor transistors arranged in each of the analytic fields, the semiconductor transistors arranged in an array; wordlines arranged on each of the plurality of the analytic fields, connecting the semiconductor transistors with each other in a first direction; and bitline structures on each of the plurality of the analytic fields, connecting the semiconductor transistors with each other in a second direction, wherein the bitline structures are configured in different patterns in each of the plurality of analytic fields.
摘要翻译：在半导体故障分析的方法和结构中，该结构包括：设置在半导体器件的预定区域上的多个分析场; 布置在每个分析场中的半导体晶体管，排列成阵列的半导体晶体管; 布置在多个分析场中的每一个上的字线，在第一方向上将半导体晶体管彼此连接; 以及在所述多个分析场中的每一个上的位线结构，在第二方向上将所述半导体晶体管彼此连接，其中所述位线结构在所述多个分析场中的每一个中被配置为不同的图案。

4. 发明申请

US20070180412A1 Method and system for enhancing yield of semiconductor integrated circuit devices using systematic fault rate of hole 有权
标题翻译：使用系统故障率提高半导体集成电路器件产量的方法和系统
公开(公告)号：US20070180412A1
公开(公告)日：2007-08-02
申请号：US11698029
申请日：2007-01-26
申请人： Choel-hwyi Bae , Sang-deok Kwon , Min-geon Cho , Gwang-hyeon Baek
发明人： Choel-hwyi Bae , Sang-deok Kwon , Min-geon Cho , Gwang-hyeon Baek
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F2217/12 , Y02P90/265
摘要： A method of enhancing yield of semiconductor integrated circuit includes determining multiple experimental values, each experimental value corresponding to a distance from a side of a hole to an opposing side of a shape surrounding the hole, forming test patterns representing each of the experimental values on a wafer and calculating experimental value-based systematic fault rates from the test patterns; converting the experimental value-based systematic fault rates of the hole into the experimental value-based systematic fault rates, calculating a length of a side of the hole for which a distance between the side of the hole and the opposing side of the shape corresponds to each of experimental values, and calculating a systematic fault rate of the hole using the experimental value-based systematic fault rates per unit hole length and the length of the sides of the hole calculated for the respective experimental values in the desired layout.
摘要翻译：提高半导体集成电路的产量的方法包括确定多个实验值，每个实验值对应于从孔的一侧到围绕孔的形状的相对侧的距离，形成表示每个实验值的测试图案并从测试模式中计算基于实验值的系统故障率; 将孔的实验值系统故障率转换为基于实验值的系统故障率，计算孔的侧面与形状的相对侧之间的距离对应于孔的一侧的长度每个实验值，并且使用每个单位孔长度的实验值系统故障率和针对所需布局中的各个实验值计算的孔的边的长度来计算孔的系统故障率。

5. 发明授权

US07733099B2 Monitoring pattern for detecting a defect in a semiconductor device and method for detecting a defect 有权
标题翻译：用于检测半导体器件中的缺陷的监视模式和用于检测缺陷的方法
公开(公告)号：US07733099B2
公开(公告)日：2010-06-08
申请号：US11798838
申请日：2007-05-17
申请人： Choel-Hwyi Bae , Yong-Woon Han , Mi-Joung Lee , Sang-Deok Kwon
发明人： Choel-Hwyi Bae , Yong-Woon Han , Mi-Joung Lee , Sang-Deok Kwon
IPC分类号： G01R31/305 , G01R31/26
CPC分类号： G01R31/2884 , G01R31/307
摘要： A monitoring pattern for detecting a defect in a semiconductor device allows a voltage contrast inspection which may be verified by an electrical test where no special test pattern is required for the electrical test. The monitoring pattern includes a test pattern with line shapes arranged in parallel and spaced apart at predetermined linewidths and intervals, and an interconnection layer connected to the test pattern, where the test pattern is adapted to be charged with a specific potential to be displayed as a voltage contrast image when scanned with an electron beam.
摘要翻译：用于检测半导体器件中的缺陷的监视模式允许电压对比度检查，其可以通过电测试来验证，其中不需要用于电测试的特殊测试图案。监视图案包括具有平行布置且以预定线宽和间隔间隔开的线形状的测试图案，以及连接到测试图案的互连层，其中测试图案适于以特定电位进行充电以被显示为用电子束扫描时的电压对比度图像。

6. 发明申请

US20060118784A1 Structure and method for failure analysis in a semiconductor device 有权
标题翻译：半导体器件故障分析的结构和方法
公开(公告)号：US20060118784A1
公开(公告)日：2006-06-08
申请号：US11291242
申请日：2005-11-30
申请人： Ki-Am Lee , Sang-Deok Kwon , Jong-Hyun Lee
发明人： Ki-Am Lee , Sang-Deok Kwon , Jong-Hyun Lee
IPC分类号： H01L23/58
CPC分类号： G01R31/2884
摘要： In a method and structure for semiconductor failure analysis, the structure comprises: a plurality of analytic fields disposed on a predetermined area of a semiconductor device; semiconductor transistors arranged in each of the analytic fields, the semiconductor transistors arranged in an array; wordlines arranged on each of the plurality of the analytic fields, connecting the semiconductor transistors with each other in a first direction; and bitline structures on each of the plurality of the analytic fields, connecting the semiconductor transistors with each other in a second direction, wherein the bitline structures are configured in different patterns in each of the plurality of analytic fields.
摘要翻译：在半导体故障分析的方法和结构中，该结构包括：设置在半导体器件的预定区域上的多个分析场; 布置在每个分析场中的半导体晶体管，排列成阵列的半导体晶体管; 布置在多个分析场中的每一个上的字线，在第一方向上将半导体晶体管彼此连接; 以及在所述多个分析场中的每一个上的位线结构，在第二方向上将所述半导体晶体管彼此连接，其中所述位线结构在所述多个分析场中的每一个中被配置为不同的图案。

7. 发明申请

US20070296447A1 Monitoring pattern for detecting a defect in a semiconductor device and method for detecting a defect 有权
标题翻译：用于检测半导体器件中的缺陷的监视模式和用于检测缺陷的方法
公开(公告)号：US20070296447A1
公开(公告)日：2007-12-27
申请号：US11798838
申请日：2007-05-17
申请人： Choel-Hwyi Bae , Yong-Woon Han , Mi-Joung Lee , Sang-Deok Kwon
发明人： Choel-Hwyi Bae , Yong-Woon Han , Mi-Joung Lee , Sang-Deok Kwon
IPC分类号： G01R31/26
CPC分类号： G01R31/2884 , G01R31/307
摘要： A monitoring pattern for detecting a defect in a semiconductor device allows a voltage contrast inspection which may be verified by an electrical test where no special test pattern is required for the electrical test. The monitoring pattern includes a test pattern with line shapes arranged in parallel and spaced apart at predetermined linewidths and intervals, and an interconnection layer connected to the test pattern, where the test pattern is adapted to be charged with a specific potential to be displayed as a voltage contrast image when scanned with an electron beam.
摘要翻译：用于检测半导体器件中的缺陷的监视模式允许电压对比度检查，其可以通过电测试来验证，其中不需要用于电测试的特殊测试图案。监视图案包括具有平行布置且以预定线宽和间隔间隔开的线形状的测试图案，以及连接到测试图案的互连层，其中测试图案适于以特定电位进行充电以被显示为用电子束扫描时的电压对比度图像。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式