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1. 发明授权

US09373516B2 Method and apparatus for forming gate stack on Si, SiGe or Ge channels 有权
标题翻译：在Si，SiGe或Ge通道上形成栅叠层的方法和装置
公开(公告)号：US09373516B2
公开(公告)日：2016-06-21
申请号：US14016027
申请日：2013-08-30
申请人： Khaled Z. Ahmed , Steven Hung , Kaushal K. Singh , Sundar Ramamurthy
发明人： Khaled Z. Ahmed , Steven Hung , Kaushal K. Singh , Sundar Ramamurthy
IPC分类号： H01L21/322 , H01L21/30 , H01L21/67 , H01L21/28 , H01L21/02 , H01L21/306 , H01L29/66
CPC分类号： H01L21/3003 , H01L21/02164 , H01L21/02301 , H01L21/02315 , H01L21/28194 , H01L21/2822 , H01L21/28255 , H01L21/306 , H01L21/6715 , H01L21/67207 , H01L29/66545
摘要： Provided are methods and apparatus for functionalizing a substrate surface used as the channel in a gate stack. Silicon, germanium and silicon germanium substrates surfaces are functionalized with one or more of sulfur and selenium by plasma processing.
摘要翻译：提供了用于将用作栅极堆叠中的沟道的衬底表面功能化的方法和装置。硅，锗和锗锗衬底表面通过等离子体处理中的一种或多种硫和硒进行功能化。

2. 发明申请

US20140065798A1 METHOD AND APPARATUS FOR FORMING GATE STACK ON Si, SiGe or Ge CHANNELS 有权
标题翻译：用于在Si，SiGe或Ge通道上形成栅极堆叠的方法和装置
公开(公告)号：US20140065798A1
公开(公告)日：2014-03-06
申请号：US14016027
申请日：2013-08-30
申请人： Khaled Z. Ahmed , Steven Hung , Kaushal K. Singh , Sundar Ramamurthy
发明人： Khaled Z. Ahmed , Steven Hung , Kaushal K. Singh , Sundar Ramamurthy
IPC分类号： H01L21/30 , H01L21/67
CPC分类号： H01L21/3003 , H01L21/02164 , H01L21/02301 , H01L21/02315 , H01L21/28194 , H01L21/2822 , H01L21/28255 , H01L21/306 , H01L21/6715 , H01L21/67207 , H01L29/66545
摘要： Provided are methods and apparatus for functionalizing a substrate surface used as the channel in a gate stack. Silicon, germanium and silicon germanium substrates surfaces are functionalized with one or more of sulfur and selenium by plasma processing.
摘要翻译：提供了用于将用作栅极堆叠中的沟道的衬底表面功能化的方法和装置。硅，锗和锗锗衬底表面通过等离子体处理中的一种或多种硫和硒进行功能化。

3. 发明申请

US20130288427A1 Methods Of Fabricating Dielectric Films From Metal Amidinate Precursors 有权
标题翻译：从金属脒前体制造介电薄膜的方法
公开(公告)号：US20130288427A1
公开(公告)日：2013-10-31
申请号：US13869182
申请日：2013-04-24
申请人： Steven Hung , Atif Noori , David Thompson , Yoshihide Senzaki
发明人： Steven Hung , Atif Noori , David Thompson , Yoshihide Senzaki
IPC分类号： H01L21/02
CPC分类号： H01L21/02565 , C23C16/40 , C23C16/45531 , C23C16/45553 , H01L21/02181 , H01L21/02186 , H01L21/02189 , H01L21/02192 , H01L21/02194 , H01L21/02274 , H01L21/0228 , H01L21/28194 , H01L29/517
摘要： Described are methods for atomic layer deposition of films comprising mixed metal oxides using metal amidinate precursors. The mixed metal oxide films may comprise a lanthanide and a transition metal such as hafnium, zirconium or titanium. Such mixed metal oxide films may be used as dielectric layers in capacitors, transistors, dynamic random access memory cells, resistive random access memory cells, flash memory cells and display panels.
摘要翻译：描述了使用金属脒前体的包含混合金属氧化物的膜的原子层沉积的方法。混合的金属氧化物膜可以包含镧系元素和过渡金属如铪，锆或钛。这种混合金属氧化物膜可以用作电容器，晶体管，动态随机存取存储器单元，电阻随机存取存储器单元，闪存单元和显示面板中的介电层。

4. 发明授权

US07678710B2 Method and apparatus for fabricating a high dielectric constant transistor gate using a low energy plasma system 有权
标题翻译：使用低能量等离子体系制造高介电常数晶体管栅的方法和装置
公开(公告)号：US07678710B2
公开(公告)日：2010-03-16
申请号：US11614019
申请日：2006-12-20
申请人： Thai Cheng Chua , Steven Hung , Patricia M. Liu , Tatsuya Sato , Alex M. Paterson , Valentin Todorov , John P. Holland
发明人： Thai Cheng Chua , Steven Hung , Patricia M. Liu , Tatsuya Sato , Alex M. Paterson , Valentin Todorov , John P. Holland
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/02175 , H01J37/32082 , H01J37/32146 , H01L21/02148 , H01L21/02266 , H01L21/0234 , H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/31155 , H01L21/3144 , H01L21/316 , H01L29/495 , H01L29/4966 , H01L29/513
摘要： The present invention generally provides methods and apparatuses that are adapted to form a high quality dielectric gate layer on a substrate. Embodiments contemplate a method wherein a metal plasma treatment process is used in lieu of a standard nitridization process to form a high dielectric constant layer on a substrate. Embodiments further contemplate an apparatus adapted to “implant” metal ions of relatively low energy in order to reduce ion bombardment damage to the gate dielectric layer, such as a silicon dioxide layer and to avoid incorporation of the metal atoms into the underlying silicon. In general, the process includes the steps of forming a high-k dielectric and then terminating the surface of the deposited high-k material to form a good interface between the gate electrode and the high-k dielectric material. Embodiments of the invention also provide a cluster tool that is adapted to form a high-k dielectric material, terminate the surface of the high-k dielectric material, perform any desirable post treatment steps, and form the polysilicon and/or metal gate layers.
摘要翻译：本发明通常提供适于在衬底上形成高质量电介质栅极层的方法和装置。实施例考虑了一种方法，其中使用金属等离子体处理工艺代替标准氮化工艺以在衬底上形成高介电常数层。实施例进一步考虑了一种适于“植入”相对较低能量的金属离子的装置，以便减少对诸如二氧化硅层的栅极介电层的离子轰击损伤，并避免将金属原子并入到下面的硅中。通常，该方法包括以下步骤：形成高k电介质，然后终止沉积的高k材料的表面，以在栅电极和高k电介质材料之间形成良好的界面。本发明的实施例还提供一种簇工具，其适于形成高k电介质材料，终止高k电介质材料的表面，执行任何期望的后处理步骤，并形成多晶硅和/或金属栅极层。

5. 发明申请

US20080238084A1 Basic hoisting ring labeling means 审中-公开
标题翻译：基本起吊环标签手段
公开(公告)号：US20080238084A1
公开(公告)日：2008-10-02
申请号：US11727411
申请日：2007-03-26
申请人： Steven Hung
发明人： Steven Hung
IPC分类号： G09F3/00
CPC分类号： G09F3/00 , G09F3/02
摘要： A basic hoisting ring labeling means to provide clear and permanent label for safe operation includes a hook, a cylindrical base, a threaded bolt, and an annual recess; the hook being coupled to the cylindrical base, the threaded bolt securing a work piece; the annual recess defining an area to show specification information specific to the ring, highlighted by a particular base color, and shield from impacts and frictions from and with other objects to maintain always clear and legible to avoid dangers resulted from drop of the work piece due to broken hoisting ring when a wrong basic hoisting ring is selected.
摘要翻译：提供安全操作的清晰和永久标签的基本起吊环标签装置包括钩，圆柱形基座，螺栓和年度凹槽; 所述钩联接到所述圆柱形基座，所述螺栓固定工件; 年度休会定义了一个区域，以显示特定于戒指的规格信息，由特定的基础颜色突出显示，并且防止与其他物体的碰撞和摩擦保持总是清晰易读，以避免工件掉落造成的危险当选择了错误的基础提升环时，打开提升环。

6. 发明申请

US20070218623A1 METHOD OF FABRICATING A HIGH DIELECTRIC CONSTANT TRANSISTOR GATE USING A LOW ENERGY PLASMA APPARATUS 失效
标题翻译：使用低能量等离子体装置制造高介电常数晶体闸门的方法
公开(公告)号：US20070218623A1
公开(公告)日：2007-09-20
申请号：US11614027
申请日：2006-12-20
申请人： Thai Cheng Chua , Alex M. Paterson , Steven Hung , Patricia M. Liu , Tatsuya Sato , Valentin Todorow , John P. Holland
发明人： Thai Cheng Chua , Alex M. Paterson , Steven Hung , Patricia M. Liu , Tatsuya Sato , Valentin Todorow , John P. Holland
IPC分类号： H01L21/8242
CPC分类号： H01L21/31645 , C23C14/10 , C23C14/345 , C23C14/3471 , H01L21/02148 , H01L21/02156 , H01L21/02161 , H01L21/02238 , H01L21/02255 , H01L21/02266 , H01L21/02321 , H01L21/02323 , H01L21/02329 , H01L21/02337 , H01L21/0234 , H01L21/28167 , H01L21/28185 , H01L21/28202 , H01L21/28273 , H01L21/28282 , H01L21/3141 , H01L21/3144 , H01L21/31612 , H01L21/3162 , H01L21/31641 , H01L29/51
摘要： The present invention generally provides methods and apparatuses that are adapted to form a high quality dielectric gate layer on a substrate. Embodiments contemplate a method wherein a metal plasma treatment process is used in lieu of a standard nitridization process to form a high dielectric constant layer on a substrate. Embodiments further contemplate an apparatus adapted to “implant” metal ions of relatively low energy in order to reduce ion bombardment damage to the gate dielectric layer, such as a silicon dioxide layer and to avoid incorporation of the metal atoms into the underlying silicon. In general, the process includes the steps of forming a high-k dielectric and then terminating the surface of the deposited high-k material to form a good interface between the gate electrode and the high-k dielectric material. Embodiments of the invention also provide a cluster tool that is adapted to form a high-k dielectric material, terminate the surface of the high-k dielectric material, perform any desirable post treatment steps, and form the polysilicon and/or metal gate layers.
摘要翻译：本发明通常提供适于在衬底上形成高质量电介质栅极层的方法和装置。实施例考虑了一种方法，其中使用金属等离子体处理工艺代替标准氮化工艺以在衬底上形成高介电常数层。实施例进一步考虑了一种适于“植入”相对较低能量的金属离子的装置，以便减少对诸如二氧化硅层的栅极介电层的离子轰击损伤，并避免将金属原子并入到下面的硅中。通常，该方法包括以下步骤：形成高k电介质，然后终止沉积的高k材料的表面，以在栅电极和高k电介质材料之间形成良好的界面。本发明的实施例还提供一种簇工具，其适于形成高k电介质材料，终止高k电介质材料的表面，执行任何期望的后处理步骤，并形成多晶硅和/或金属栅极层。

7. 发明申请

US20050253618A1 Work function controlled probe for measuring properties of a semiconductor wafer and method of use thereof 失效
标题翻译：用于测量半导体晶片的性能的工作功能控制探针及其使用方法
公开(公告)号：US20050253618A1
公开(公告)日：2005-11-17
申请号：US10845815
申请日：2004-05-14
申请人： William Howland , Robert Hillard , Steven Hung
发明人： William Howland , Robert Hillard , Steven Hung
IPC分类号： G01R31/26 , G01R1/067 , G01R31/319 , H01L21/66
CPC分类号： G01R31/2648 , G01R1/06711
摘要： In a method of measuring at least one electrical property of a semiconductor wafer, an elastically deformable conductive contact formed from an electrically conductive coating overlaying an electrically conductive base material is provided. The base material has a first work function and the coating has a second work function. A first electrical contact is formed between the conductive contact and a top surface of a semiconductor wafer. A second electrical contact is formed with the semiconductor wafer. An electrical stimulus is applied between the first and second electrical contacts and a response of the semiconductor wafer to the electrical stimulus is measured. At least one electrical property of the semiconductor wafer is determined from the response.
摘要翻译：在测量半导体晶片的至少一个电特性的方法中，提供了由覆盖导电基材的导电涂层形成的可弹性变形的导电接触。基材具有第一功能，涂层具有第二功能。在导电接触件和半导体晶片的顶表面之间形成第一电接触。与半导体晶片形成第二电接触。在第一和第二电触点之间施加电刺激，并且测量半导体晶片对电刺激的响应。根据响应确定半导体晶片的至少一个电性质。

8. 发明授权

US07867859B1 Gate electrode with depletion suppression and tunable workfunction 有权
标题翻译：具有耗尽抑制和可调功能的栅电极
公开(公告)号：US07867859B1
公开(公告)日：2011-01-11
申请号：US12140955
申请日：2008-06-17
申请人： Steven Hung , Judy L. Hoyt , James F. Gibbons
发明人： Steven Hung , Judy L. Hoyt , James F. Gibbons
IPC分类号： H01L21/336 , H01L21/20 , H01L21/4763 , H01L21/3205
CPC分类号： H01L29/1054 , H01L21/28079 , H01L29/4958
摘要： Semiconductor device performance is improved via a gate structure having a tunable effective workfunction and reduced gate depletion effects. According to an example embodiment, the design threshold voltage of a semiconductor device is adjusted in a manner that includes providing a gate having a workfunction that enables operation of the semiconductor device at a selected voltage. The gate is formed having two different conductive materials with different electric workfunctions that both significantly contribute to the overall workfunction of the gate. The relative composition, thickness, and arrangement of each of the two conductive materials is selected to attain a gate electrode workfunction that is different than the workfunctions of each of the two layers and that sets the threshold voltage of the semiconductor device. The adjustability of the effective workfunction of the gate electrode can be applied to a variety of semiconductor devices. The ability to reduce gate depletion effects also provides enhanced device current drive.
摘要翻译：通过具有可调谐的有效功函数和减少的栅极耗尽效应的栅极结构来提高半导体器件的性能。根据示例性实施例，半导体器件的设计阈值电压被调整为包括提供具有能够使半导体器件处于选定电压的功能的功能门的方式。栅极形成为具有不同电功能的两种不同的导电材料，这两种导电材料都显着地有助于栅极的整体功能。选择两种导电材料中的每一种的相对组成，厚度和布置，以获得不同于两层中的每一层的功函数的栅电极功函数，并设定半导体器件的阈值电压。栅电极的有效功函数的可调性可应用于各种半导体器件。降低栅极耗尽效应的能力还提供增强的器件电流驱动。

9. 发明申请

US20070209930A1 APPARATUS FOR FABRICATING A HIGH DIELECTRIC CONSTANT TRANSISTOR GATE USING A LOW ENERGY PLASMA SYSTEM 审中-公开
标题翻译：使用低能量等离子体系统制造高介电常数晶体闸门的装置
公开(公告)号：US20070209930A1
公开(公告)日：2007-09-13
申请号：US11614022
申请日：2006-12-20
申请人： Thai Cheng Chua , Alex M. Paterson , Steven Hung , Patricia M. Liu , Tatsuya Sato , Valentin Todorow , John P. Holland
发明人： Thai Cheng Chua , Alex M. Paterson , Steven Hung , Patricia M. Liu , Tatsuya Sato , Valentin Todorow , John P. Holland
IPC分类号： C23C14/00
CPC分类号： C23C8/10 , C23C8/36 , C23C14/021 , C23C14/027 , C23C14/48 , C23C14/5806 , C23C14/5826 , H01J37/32082 , H01J37/32146 , H01J37/32165 , H01L21/67207
摘要： The present invention generally provides methods and apparatuses that are adapted to form a high quality dielectric gate layer on a substrate. Embodiments contemplate a method wherein a metal plasma treatment process is used in lieu of a standard nitridization process to form a high dielectric constant layer on a substrate. Embodiments further contemplate an apparatus adapted to “implant” metal ions of relatively low energy in order to reduce ion bombardment damage to the gate dielectric layer, such as a silicon dioxide layer and to avoid incorporation of the metal atoms into the underlying silicon. In general, the process includes the steps of forming a high-k dielectric and then terminating the surface of the deposited high-k material to form a good interface between the gate electrode and the high-k dielectric material. Embodiments of the invention also provide a cluster tool that is adapted to form a high-k dielectric material, terminate the surface of the high-k dielectric material, perform any desirable post treatment steps, and form the polysilicon and/or metal gate layers.
摘要翻译：本发明通常提供适于在衬底上形成高质量电介质栅极层的方法和装置。实施例考虑了一种方法，其中使用金属等离子体处理工艺代替标准氮化工艺以在衬底上形成高介电常数层。实施例进一步考虑了一种适于“植入”相对较低能量的金属离子的装置，以便减少对诸如二氧化硅层的栅极介电层的离子轰击损伤，并避免将金属原子并入到下面的硅中。通常，该方法包括以下步骤：形成高k电介质，然后终止沉积的高k材料的表面，以在栅电极和高k电介质材料之间形成良好的界面。本发明的实施例还提供一种簇工具，其适于形成高k电介质材料，终止高k电介质材料的表面，执行任何期望的后处理步骤，并形成多晶硅和/或金属栅极层。

10. 外观设计

USD502089S1 Safe hook 失效
标题翻译：安全钩
公开(公告)号：USD502089S1
公开(公告)日：2005-02-22
申请号：US29204777
申请日：2004-05-05
申请人： Steven Hung
设计人： Steven Hung

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