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1. 发明授权

US07805618B2 Component indicators used during extended power-off service 失效
标题翻译：在延长关机服务期间使用的组件指示器
公开(公告)号：US07805618B2
公开(公告)日：2010-09-28
申请号：US11357147
申请日：2006-02-17
申请人： Kevin R. Covi , Gerald J. Fahr , Raymond J. Harrington , Raymond A. Longhi , Edward J. Seminaro
发明人： Kevin R. Covi , Gerald J. Fahr , Raymond J. Harrington , Raymond A. Longhi , Edward J. Seminaro
IPC分类号： G06F1/00 , G06F15/177
CPC分类号： G06F1/263 , G06F1/30 , G06F11/325
摘要： A method and related apparatus for servicing an electrical/electronic device during power shut offs is provided. The apparatus comprises a service logic having a memory and control component for storing device information during normal device operation and one or more indicators driven by the memory and control component after power shut off to provide service signals. The service logic also includes an auxiliary energy source selectively engageable to provide auxiliary power to the memory and control component during power shut off and to enable providing of service signals through the indicator(s).
摘要翻译：提供了一种用于在电源关闭期间维护电气/电子设备的方法和相关装置。该装置包括具有用于在正常设备操作期间存储设备信息的存储器和控制组件的服务逻辑以及在电源关闭之后由存储器和控制组件驱动以提供服务信号的一个或多个指示器。服务逻辑还包括辅助能量源，其选择性地可接合以在电源切断期间向存储器和控制部件提供辅助电力，并且能够通过指示器提供服务信号。

2. 发明授权

US07216051B2 Power short circuit testing of an electronics assembly employing pre-characterized power off resistance of an electronic component thereof from a power boundary 失效
标题翻译：电子组件的电力短路测试，其采用电力边界的电子部件的预定义的断电电阻
公开(公告)号：US07216051B2
公开(公告)日：2007-05-08
申请号：US11137878
申请日：2005-05-26
申请人： Frank E Bosco , Gerald J. Fahr , Raymond A. Longhi , Vincent P. Mulligan
发明人： Frank E Bosco , Gerald J. Fahr , Raymond A. Longhi , Vincent P. Mulligan
IPC分类号： G01R27/28 , G01R31/00 , G01R31/14 , G06F19/00
CPC分类号： G01R31/025
摘要： A technique for testing an electronics assembly for a power short circuit is provided. The technique includes pre-characterizing power off resistance of an electronic component(s) of a first packaging level from at least one power boundary of the electronic component(s). The characterizing of the power off resistance occurs prior to placement of the electronic component(s) into an electronics assembly of a higher packaging level. The technique further includes determining actual power off resistance of the electronics component(s) after placement thereof into the electronics assembly, with the actual power off resistance being determined from the at least one power boundary. Thereafter, the actual power off resistance of the electronic component(s) in the electronics assembly is compared with the pre-characterized power off resistance of the at least one electronic component(s), and a determination is made therefrom whether a power short circuit exists within the electronics assembly.
摘要翻译：提供了一种用于测试用于电源短路的电子组件的技术。该技术包括从电子部件的至少一个电源边界预先表征第一封装级别的电子部件的断电电阻。在将电子部件放置到更高封装水平的电子组件之前，断电阻力的表征发生。该技术还包括在将电子元件放入电子组件之后确定电子元件的实际断电电阻，其中实际断电电阻是从至少一个电源边界确定的。此后，将电子组件中的电子部件的实际断电电阻与至少一个电子部件的预表示的断电电阻进行比较，并且确定电力短路存在于电子组件内。

3. 发明授权

US07681073B2 Arbitration system for redundant controllers, with output interlock and automatic switching capabilities 失效
标题翻译：冗余控制器仲裁系统，具有输出互锁和自动切换功能
公开(公告)号：US07681073B2
公开(公告)日：2010-03-16
申请号：US12259447
申请日：2008-10-28
申请人： Gary D. Anderson , Gerald J. Fahr , Raymond J. Harrington
发明人： Gary D. Anderson , Gerald J. Fahr , Raymond J. Harrington
IPC分类号： G06F11/00
CPC分类号： G06F11/20 , G06F11/2017
摘要： An arbitration mechanism is provided for arbitrating between redundant controllers having outputs electrically connected together and provided as input to at least one device under control. The arbitration mechanism includes logic for automatically determining which controller of the redundant controllers is active controller, and a hardware output interlock for the redundant controllers to ensure that output controlled by only the active controller is enabled as input to the at least one device. The arbitration mechanism also includes logic for monitoring the active controller for failure, and upon detection of failure, for automatically switching active control to another controller of the redundant controllers transparent to the at least one device.
摘要翻译：提供仲裁机制用于在具有电连接在一起的输出的冗余控制器之间进行仲裁，并将其作为输入提供给被控制的至少一个设备。仲裁机制包括用于自动确定冗余控制器的哪个控制器是主动控制器的逻辑，以及用于冗余控制器的硬件输出互锁，以确保仅由主动控制器控制的输出被启用为至少一个设备的输入。仲裁机制还包括用于监视主动控制器用于故障的逻辑，以及在检测到故障时，用于将主动控制自动切换到对至少一个设备透明的冗余控制器的另一个控制器。

4. 发明授权

US07290170B2 Arbitration method and system for redundant controllers, with output interlock and automatic switching capabilities 失效
标题翻译：冗余控制器的仲裁方法和系统，具有输出互锁和自动切换功能
公开(公告)号：US07290170B2
公开(公告)日：2007-10-30
申请号：US10820177
申请日：2004-04-07
申请人： Gary D. Anderson , Gerald J. Fahr , Raymond J. Harrington
发明人： Gary D. Anderson , Gerald J. Fahr , Raymond J. Harrington
IPC分类号： G06F11/00
CPC分类号： G06F11/20 , G06F11/2017
摘要： An arbitration mechanism is provided for arbitrating between redundant controllers having outputs electrically connected together and provided as input to at least one device under control. The arbitration mechanism includes logic for automatically determining which controller of the redundant controllers is active controller, and a hardware output interlock for the redundant controllers to ensure that output controlled by only the active controller is enabled as input to the at least one device. The arbitration mechanism also includes logic for monitoring the active controller for failure, and upon detection of failure, for automatically switching active control to another controller of the redundant controllers transparent to the at least one device.
摘要翻译：提供仲裁机制用于在具有电连接在一起的输出的冗余控制器之间进行仲裁，并将其作为输入提供给被控制的至少一个设备。仲裁机制包括用于自动确定冗余控制器的哪个控制器是主动控制器的逻辑，以及用于冗余控制器的硬件输出互锁，以确保仅由主动控制器控制的输出被启用为至少一个设备的输入。仲裁机制还包括用于监视主动控制器用于故障的逻辑，以及在检测到故障时，用于将主动控制自动切换到对至少一个设备透明的冗余控制器的另一个控制器。

5. 发明授权

US07461291B2 Arbitration method and system for redundant controllers, with output interlock and automatic switching capabilities 失效
标题翻译：冗余控制器的仲裁方法和系统，具有输出互锁和自动切换功能
公开(公告)号：US07461291B2
公开(公告)日：2008-12-02
申请号：US11765143
申请日：2007-06-19
申请人： Gary D. Anderson , Gerald J. Fahr , Raymond J. Harrington
发明人： Gary D. Anderson , Gerald J. Fahr , Raymond J. Harrington
IPC分类号： G06F11/00
CPC分类号： G06F11/20 , G06F11/2017
摘要： A method of providing arbitration for redundant controllers is provided, which includes: providing logic for automatically determining which controller of redundant controllers is active controller, wherein outputs of the redundant controllers are electrically hardwired together and provided as input to a device; and providing first and second hardware arbitration components for first and second controllers of the redundant controllers, each hardware arbitration component ensuring that outputs of the respective controller are enabled only when the associated controller is active controller. The first and second hardware arbitration components are separate hardware components which communicate and cooperate as a distributed hardware interlock mechanism that ensures outputs of only one controller are enabled at a time. More particularly, the hardware arbitration components each include a hardware state machine to enable/disable outputs of the associated controller and ensure that outputs of only the active controller are enabled as input to the device.
摘要翻译：提供了一种为冗余控制器提供仲裁的方法，其包括：提供用于自动确定冗余控制器的哪个控制器是主动控制器的逻辑，其中冗余控制器的输出电连接在一起并作为设备的输入提供; 以及为冗余控制器的第一和第二控制器提供第一和第二硬件仲裁组件，每个硬件仲裁组件确保只有当相关联的控制器是主动控制器时才启用相应控制器的输出。第一和第二硬件仲裁组件是分开的硬件组件，其作为分布式硬件互锁机制进行通信和协作，确保一次只能启用一个控制器的输出。更具体地说，硬件仲裁组件各自包括硬件状态机以启用/禁用相关联的控制器的输出，并确保只有主动控制器的输出被启用作为设备的输入。

6. 发明授权

US07644216B2 System and method for providing an adapter for re-use of legacy DIMMS in a fully buffered memory environment 失效
标题翻译：用于提供用于在完全缓冲的存储器环境中重复使用传统DIMMS的适配器的系统和方法
公开(公告)号：US07644216B2
公开(公告)日：2010-01-05
申请号：US11735677
申请日：2007-04-16
申请人： Gerald J. Fahr , Raymond J. Harrington , Roger A. Rippens , Donald J. Swietek
发明人： Gerald J. Fahr , Raymond J. Harrington , Roger A. Rippens , Donald J. Swietek
IPC分类号： H05K7/10
CPC分类号： G06F13/16 , G06F13/385
摘要： A system and method for providing an adapter for re-use of legacy DIMMS in a fully buffered memory environment. The system includes a memory adapter card having two rows of contacts along a leading edge of a length of the card. The rows of contacts are adapted to be inserted into a socket that is connected to a daisy chain high-speed memory bus via a packetized multi-transfer interface. The memory adapter card also includes a socket installed on the trailing edge of the card. In addition, the memory adapter card includes a hub device for converting the packetized multi-transfer interface into a parallel interface having timings and interface levels that are operable with a memory module having a parallel interface that is inserted into the socket. In addition, the hub device converts the packetized multi-transfer interface into a parallel interface having timings and interface levels that are operable with a memory module having a parallel interface that is inserted into the socket. The hub device also converts the parallel interface into the packetized multi-transfer interface.
摘要翻译：一种用于在完全缓冲的存储器环境中提供用于重新使用传统DIMMS的适配器的系统和方法。该系统包括具有沿着卡的长度的前缘的两行触点的存储器适配器卡。触点行适于插入通过分组化的多传输接口连接到菊花链高速存储器总线的插座中。存储器适配器卡还包括安装在卡尾部的插座。此外，存储器适配器卡包括用于将打包的多传输接口转换成具有定时和接口级别的并行接口的集线器设备，该定时和接口级别可与具有插入插座的并行接口的存储器模块一起操作。此外，集线器设备将打包的多传输接口转换成具有定时和接口级别的并行接口，该定时和接口级别可与具有插入插座的并行接口的存储器模块一起操作。集线器设备还将并行接口转换为打包的多传输接口。

7. 发明申请

US20080256281A1 SYSTEM AND METHOD FOR PROVIDING AN ADAPTER FOR RE-USE OF LEGACY DIMMS IN A FULLY BUFFERED MEMORY ENVIRONMENT 失效
标题翻译：提供适配器的系统和方法，用于在完全缓冲的存储器环境中重新使用代码
公开(公告)号：US20080256281A1
公开(公告)日：2008-10-16
申请号：US11735677
申请日：2007-04-16
申请人： Gerald J. Fahr , Raymond J. Harrington , Roger A. Rippens , Donald J. Swietek
发明人： Gerald J. Fahr , Raymond J. Harrington , Roger A. Rippens , Donald J. Swietek
IPC分类号： G06F13/14
CPC分类号： G06F13/16 , G06F13/385
摘要： A system and method for providing an adapter for re-use of legacy DIMMS in a fully buffered memory environment. The system includes a memory adapter card having two rows of contacts along a leading edge of a length of the card. The rows of contacts are adapted to be inserted into a socket that is connected to a daisy chain high-speed memory bus via a packetized multi-transfer interface. The memory adapter card also includes a socket installed on the trailing edge of the card. In addition, the memory adapter card includes a hub device for converting the packetized multi-transfer interface into a parallel interface having timings and interface levels that are operable with a memory module having a parallel interface that is inserted into the socket. In addition, the hub device converts the packetized multi-transfer interface into a parallel interface having timings and interface levels that are operable with a memory module having a parallel interface that is inserted into the socket. The hub device also converts the parallel interface into the packetized multi-transfer interface.
摘要翻译：一种用于在完全缓冲的存储器环境中提供用于重新使用传统DIMMS的适配器的系统和方法。该系统包括具有沿着卡的长度的前缘的两行触点的存储器适配器卡。触点行适于插入通过分组化的多传输接口连接到菊花链高速存储器总线的插座中。存储器适配器卡还包括安装在卡尾部的插座。此外，存储器适配器卡包括用于将打包的多传输接口转换成具有定时和接口级别的并行接口的集线器设备，该定时和接口级别可与具有插入插座的并行接口的存储器模块一起操作。此外，集线器设备将打包的多传输接口转换成具有定时和接口级别的并行接口，该定时和接口级别可与具有插入插座的并行接口的存储器模块一起操作。集线器设备还将并行接口转换为打包的多传输接口。

8. 发明授权

US08018095B2 Power conversion, control, and distribution system 有权
标题翻译：电力转换，控制和配电系统
公开(公告)号：US08018095B2
公开(公告)日：2011-09-13
申请号：US12425267
申请日：2009-04-16
申请人： Ravi Kumar Arimilli , Edward Joseph Seminaro , Kevin Robert Covi , Gerald J. Fahr , Daniel James Barus
发明人： Ravi Kumar Arimilli , Edward Joseph Seminaro , Kevin Robert Covi , Gerald J. Fahr , Daniel James Barus
IPC分类号： H02J3/38
CPC分类号： H02J1/102 , Y10T307/352 , Y10T307/707
摘要： A power conversion, control, and distribution system includes multiple bulk power regulator (BPR) subassemblies, a bulk power distribution (BPD) subassembly, and a bulk power controller and hub (BPCH) subassembly. The BPR subassemblies are each configured to provide regulated DC power from both AC input power and DC input power. The BPD subassembly is configured to distribute the regulated DC power. The BPCH subassembly is coupled to the multiple BPR subassemblies and the BPD subassembly. The BPCH subassembly is configured to monitor and control the BPR assemblies and the BPD assembly.
摘要翻译：电力转换，控制和分配系统包括多个大功率调节器（BPR）子组件，大容量配电（BPD）子组件和大容量功率控制器和集线器（BPCH）子组件。 BPR子组件各自配置为从交流输入功率和直流输入功率提供稳压的直流电源。 BPD子组件被配置为分配调节的直流电力。 BPCH子组件耦合到多个BPR子组件和BPD子组件。 BPCH子组件被配置为监视和控制BPR组件和BPD组件。

9. 发明申请

US20080065786A1 INCREASED PERFORMANCE USING MIXED MEMORY TYPES 有权
标题翻译：使用混合存储器类型提高性能
公开(公告)号：US20080065786A1
公开(公告)日：2008-03-13
申请号：US11530341
申请日：2006-09-08
申请人： Douglas A. Baska , Gerald J. Fahr
发明人： Douglas A. Baska , Gerald J. Fahr
IPC分类号： G06F3/00
CPC分类号： G06F13/1694
摘要： A memory unit includes a system memory controller coupled to a plurality of memory clock oscillators and a plurality of respective voltage controllers, wherein each memory clock oscillator and respective voltage controller are coupled to a memory receptacle and thus provide a plurality of memory receptacles, each receptacle in the plurality of receptacles having a separate power boundary for operation of a memory type. The memory unit provides a computing system with capabilities to operate a variety of memory types. Methods and computer program products of operation of the memory unit are provided.
摘要翻译：存储器单元包括耦合到多个存储器时钟振荡器和多个相应电压控制器的系统存储器控制器，其中每个存储器时钟振荡器和相应的电压控制器耦合到存储器插座，并因此提供多个存储器插座，每个插座在具有用于存储器类型的操作的单独的电源边界的多个插座中。存储器单元为计算系统提供了操作各种存储器类型的能力。提供了存储单元操作的方法和计算机程序产品。

10. 发明授权

US07516293B2 Increased performance using mixed memory types 有权
标题翻译：使用混合内存类型提高性能
公开(公告)号：US07516293B2
公开(公告)日：2009-04-07
申请号：US11530341
申请日：2006-09-08
申请人： Douglas A. Baska , Gerald J. Fahr
发明人： Douglas A. Baska , Gerald J. Fahr
IPC分类号： G06F12/00
CPC分类号： G06F13/1694
摘要： A memory unit includes a system memory controller coupled to a plurality of memory clock oscillators and a plurality of respective voltage controllers, wherein each memory clock oscillator and respective voltage controller are coupled to a memory receptacle and thus provide a plurality of memory receptacles, each receptacle in the plurality of receptacles having a separate power boundary for operation of a memory type. The memory unit provides a computing system with capabilities to operate a variety of memory types. Methods and computer program products of operation of the memory unit are provided.
摘要翻译：存储器单元包括耦合到多个存储器时钟振荡器和多个相应电压控制器的系统存储器控制器，其中每个存储器时钟振荡器和相应的电压控制器耦合到存储器插座，并因此提供多个存储器插座，每个插座在具有用于存储器类型的操作的单独的电源边界的多个插座中。存储器单元为计算系统提供了操作各种存储器类型的能力。提供了存储单元操作的方法和计算机程序产品。

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