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1. 发明授权

US5430408A Transmission gate circuit 失效
标题翻译：传输门电路
公开(公告)号：US5430408A
公开(公告)日：1995-07-04
申请号：US259731
申请日：1994-06-14
申请人： Kevin Ovens , Clive Bittlestone , Bob Helmick
发明人： Kevin Ovens , Clive Bittlestone , Bob Helmick
IPC分类号： H03K17/041 , H03K17/567 , H03K17/04 , H03K17/12
CPC分类号： H03K17/04106 , H03K17/567
摘要： A transmission gate circuit 20 includes a pull-up control circuit 15, a pull-down control circuit 17, and an electrical switch 19. Pull-up control circuit 15 and electrical switch 19 provide fast, complete transition from low-to-high at the output of circuit 20 thus improving circuit 20 speed as well as improving the switching speed of subsequent gates. Pull-down control circuit 17 and electrical switch 19 provide complete transition from high-to-low at the output of circuit 20. Transmission gate circuit 17 also provides increased drive such that circuit 20 may provide a gate fanout increase of 3X.
摘要翻译：传输门电路20包括上拉控制电路15，下拉控制电路17和电开关19.上拉控制电路15和电开关19提供从低到高的快速，完全的过渡电路20的输出因此提高电路20的速度以及提高随后的门的切换速度。下拉控制电路17和电开关19在电路20的输出处提供从高到低的完全转变。传输门电路17还提供增加的驱动，使得电路20可以提供3X的栅极扇出增加。

2. 发明授权

US5381455A Interleaved shift register 失效
标题翻译：交错移位寄存器
公开(公告)号：US5381455A
公开(公告)日：1995-01-10
申请号：US53941
申请日：1993-04-28
申请人： Kevin Ovens , Clive Bittlestone , Bob Helmick
发明人： Kevin Ovens , Clive Bittlestone , Bob Helmick
IPC分类号： G11C19/00
CPC分类号： G11C19/00
摘要： An interleaved shift register 20 includes a plurality of data storage elements 22a-22d having a common data input signal. Each of the plurality of data storage elements 22a-22d has an enable control input that is connected to one of a plurality of clock signals, each of the plurality of clock signals being incrementally out of phase with one another. Interleaved shift register 20 provides multiple data bits of the data signal to be stored within a single clock period of one of the plurality of clock signals, thus greatly improving the data rate without increasing the storage rate of the plurality of data storage elements 22a-22d.
摘要翻译：交错移位寄存器20包括具有公共数据输入信号的多个数据存储元件22a-22d。多个数据存储元件22a-22d中的每一个具有连接到多个时钟信号之一的使能控制输入，多个时钟信号中的每一个彼此逐渐地异相。交错移位寄存器20提供要在多个时钟信号之一的单个时钟周期内存储的数据信号的多个数据位，从而大大提高数据速率，而不增加多个数据存储元件22a-22d的存储速率。

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