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1. 发明授权

US5430408A Transmission gate circuit 失效
标题翻译：传输门电路
公开(公告)号：US5430408A
公开(公告)日：1995-07-04
申请号：US259731
申请日：1994-06-14
申请人： Kevin Ovens , Clive Bittlestone , Bob Helmick
发明人： Kevin Ovens , Clive Bittlestone , Bob Helmick
IPC分类号： H03K17/041 , H03K17/567 , H03K17/04 , H03K17/12
CPC分类号： H03K17/04106 , H03K17/567
摘要： A transmission gate circuit 20 includes a pull-up control circuit 15, a pull-down control circuit 17, and an electrical switch 19. Pull-up control circuit 15 and electrical switch 19 provide fast, complete transition from low-to-high at the output of circuit 20 thus improving circuit 20 speed as well as improving the switching speed of subsequent gates. Pull-down control circuit 17 and electrical switch 19 provide complete transition from high-to-low at the output of circuit 20. Transmission gate circuit 17 also provides increased drive such that circuit 20 may provide a gate fanout increase of 3X.
摘要翻译：传输门电路20包括上拉控制电路15，下拉控制电路17和电开关19.上拉控制电路15和电开关19提供从低到高的快速，完全的过渡电路20的输出因此提高电路20的速度以及提高随后的门的切换速度。下拉控制电路17和电开关19在电路20的输出处提供从高到低的完全转变。传输门电路17还提供增加的驱动，使得电路20可以提供3X的栅极扇出增加。

2. 发明申请

US20070290270A1 Performance and Area Scalable Cell Architecture Technology 有权
标题翻译：性能和面积可扩展单元架构技术
公开(公告)号：US20070290270A1
公开(公告)日：2007-12-20
申请号：US11745250
申请日：2007-05-07
申请人： Uming Ko , Dharin Shah , Senthil Sundaramoorthy , Girishankar Gurumurthy , Sumanth Gururajarao , Rolf Lagerquist , Clive Bittlestone
发明人： Uming Ko , Dharin Shah , Senthil Sundaramoorthy , Girishankar Gurumurthy , Sumanth Gururajarao , Rolf Lagerquist , Clive Bittlestone
IPC分类号： H01L29/768 , G06F17/50
CPC分类号： G06F17/5072 , H01L27/0207 , H01L27/11807
摘要： An integrated circuit. The integrated circuit comprises an area having a layout aligned in rows. Each row is definable by a pair of row boundaries. The integrated circuit also comprises a plurality of cells, comprising a first set of cells. Each cell in the first set of cells spans at least two rows and comprises a PMOS transistor having a source/drain region that spans across one of the row boundaries and an NMOS transistor having a source/drain region that spans across one of the row boundaries.
摘要翻译：集成电路。集成电路包括具有排列成行的布局的区域。每行可由一对行边界定义。集成电路还包括多个单元，包括第一组单元。第一组单元中的每个单元跨过至少两行并且包括具有跨越行边界中的一个的源极/漏极区域的PMOS晶体管和具有跨越行边界之一的源极/漏极区域的NMOS晶体管。

3. 发明授权

US06909301B2 Oscillation based access time measurement 有权
标题翻译：基于振荡的访问时间测量
公开(公告)号：US06909301B2
公开(公告)日：2005-06-21
申请号：US10236328
申请日：2002-09-06
申请人： Steven P. Korson , Brian D. Borchers , Bryan Sheffield , Clive Bittlestone , Doug Counce
发明人： Steven P. Korson , Brian D. Borchers , Bryan Sheffield , Clive Bittlestone , Doug Counce
IPC分类号： G01R31/30 , G11C29/14 , G11C29/50 , G01R31/02
CPC分类号： G11C29/50012 , G01R31/3016 , G11C29/14 , G11C29/50
摘要： An embodiment of the invention is a method for measuring access time where the frequency of a ring oscillator is measured with and without a device under test 1 in the ring. Those two frequencies are compared to calculate the access time of the device under test 1. Another embodiment of the invention is circuitry 25 that measures the frequency of a ring oscillator with and without a device under test 1. Again the two frequencies are compared to calculate the access time of the device under test 1.
摘要翻译：本发明的一个实施例是一种测量接入时间的方法，其中测量环路振荡器的频率是否具有环中的被测器件1。比较这两个频率来计算被测设备1的访问时间。本发明的另一实施例是测量具有和不具有被测器件1的环形振荡器的频率的电路25。将两个频率再次进行比较，以计算被测器件1的访问时间。

4. 发明授权

US06734743B2 Oscillation based cycle time measurement 有权
标题翻译：基于振荡的循环时间测量
公开(公告)号：US06734743B2
公开(公告)日：2004-05-11
申请号：US10236329
申请日：2002-09-06
申请人： Steven P. Korson , Brian D. Borchers , Bryan Sheffield , Clive Bittlestone , Doug Counce
发明人： Steven P. Korson , Brian D. Borchers , Bryan Sheffield , Clive Bittlestone , Doug Counce
IPC分类号： H03B520
CPC分类号： G11C29/50012 , G01R31/31922 , G01R31/31937 , G11C29/50 , G11C29/56 , G11C29/56012
摘要： An embodiment of the invention is circuitry 25 that contains a programmable delay 8 and a pulse generator 16 that send clock signals of a certain frequency to a device under test 1. The programmable delay 8 increases the frequency of the clock signal to the device under test 1 until the device under test fails. The cycle time measurement of the device under test 1 is the period of maximum frequency at which the device under test 1 operates properly.
摘要翻译：本发明的实施例是包含可编程延迟8的电路25和向特定频率的时钟信号发送到被测器件1的脉冲发生器16.可编程延迟8将时钟信号的频率增加到被测器件 1，直到被测设备失败。被测设备1的周期时间测量是被测设备1正常工作的最大频率周期。

5. 发明授权

US06380593B1 Automated well-tie and substrate contact insertion methodology 有权
标题翻译：自动化配套和底层接触插入方法
公开(公告)号：US06380593B1
公开(公告)日：2002-04-30
申请号：US09464665
申请日：1999-12-15
申请人： Jay Maxey , Kevin M. Ovens , Clive Bittlestone
发明人： Jay Maxey , Kevin M. Ovens , Clive Bittlestone
IPC分类号： G06F1500
CPC分类号： G06F17/5068 , H01L27/11807
摘要： A modified flow for ASIC place an route software flow which allows incorporation into the flow, a process for tracking the locations of substrate contacts and well-ties within and outside the boundaries of placed cells and generating required supplemental placements, making possible an efficient use of silicon chip area expended in the adequate placement of substrate contacts and well-ties.
摘要翻译：用于ASIC的经修改的流程将路由软件流程允许并入流程中，跟踪在放置的单元的边界内和外部的衬底接触和关系的位置的过程，并且产生所需的补充放置，使得有可能有效地使用硅芯片面积弥补了基板接触和贴合的充分放置。

6. 发明授权

US07564077B2 Performance and area scalable cell architecture technology 有权
标题翻译：性能和面积可扩展单元架构技术
公开(公告)号：US07564077B2
公开(公告)日：2009-07-21
申请号：US11745250
申请日：2007-05-07
申请人： Uming Ko , Dharin Shah , Senthil Sundaramoorthy , Girishankar Gurumurthy , Sumanth Gururajarao , Rolf Lagerquist , Clive Bittlestone
发明人： Uming Ko , Dharin Shah , Senthil Sundaramoorthy , Girishankar Gurumurthy , Sumanth Gururajarao , Rolf Lagerquist , Clive Bittlestone
IPC分类号： H01L27/10 , H01L29/73
CPC分类号： G06F17/5072 , H01L27/0207 , H01L27/11807
摘要： An integrated circuit. The integrated circuit comprises an area having a layout aligned in rows. Each row is definable by a pair of row boundaries. The integrated circuit also comprises a plurality of cells, comprising a first set of cells. Each cell in the first set of cells spans at least two rows and comprises a PMOS transistor having a source/drain region that spans across one of the row boundaries and an NMOS transistor having a source/drain region that spans across one of the row boundaries.
摘要翻译：集成电路。集成电路包括具有排列成行的布局的区域。每行可由一对行边界定义。集成电路还包括多个单元，包括第一组单元。第一组单元中的每个单元跨过至少两行并且包括具有跨越行边界中的一个的源极/漏极区域的PMOS晶体管和具有跨越行边界之一的源极/漏极区域的NMOS晶体管。

7. 发明授权

US06308307B1 Method for power routing and distribution in an integrated circuit with multiple interconnect layers 有权
标题翻译：具有多个互连层的集成电路中的电力布线和分配方法
公开(公告)号：US06308307B1
公开(公告)日：2001-10-23
申请号：US09240126
申请日：1999-01-29
申请人： Francisco A. Cano , David A. Thomas , Clive Bittlestone
发明人： Francisco A. Cano , David A. Thomas , Clive Bittlestone
IPC分类号： G06F1750
CPC分类号： G06F17/5068 , G06F17/5077 , G06F2217/78 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit 210 has a power grid formed from a first set of power buses 201a and 202a on a metal interconnect level M1, a second set of power buses 203a and 204a on interconnect level M4, and a third set of power buses 205a and 206a on inter-connect level M5. The set of power buses on level M4 are oriented in the same direction as the set of power buses on level M1, and both sets of buses are located coincidentally. A high power logic cell 220 is pre-defined with a set of M1-M4 power vias 221 and 222 so that logic cell 220 can be positioned in a horizontal row unconstrained by pre-positioned M1-M4 power vias. Dummy cell 230 with M1-M4 power vias is positioned as needed so as not to exceed a maximum strapping distance D1. A maximum value for distance D1 is selected based on dynamic power requirements of nearby logic cells 250a-n as determined by simulation. A method for designing and fabricating integrated circuit 210 is described.
摘要翻译：集成电路210具有由金属互连级M1上的第一组电源总线201a和202a形成的电网，以及互连级M4上的第二组电源总线203a和204a以及第三组电源总线205a和206a 在连接间级别M5上。 M4级的电力总线集合方向与M1级的电力总线相同，两组总线同时定位。高功率逻辑单元220用一组M1-M4电源通孔221和222预定义，使得逻辑单元220可以被定位在不受预定义的M1-M4电源通孔约束的水平行中。具有M1-M4电源通孔的假电池230根据需要定位，以便不超过最大捆扎距离D1。基于通过仿真确定的附近的逻辑单元250a-n的动态功率要求来选择距离D1的最大值。描述了集成电路210的设计和制造方法。

8. 发明授权

US5612632A High speed flip-flop for gate array 失效
标题翻译：门阵列高速触发器
公开(公告)号：US5612632A
公开(公告)日：1997-03-18
申请号：US346562
申请日：1994-11-29
申请人： Shivaling Mahant-Shetti , Kevin Ovens , Clive Bittlestone , Robert C. Martin , Robert J. Landers
发明人： Shivaling Mahant-Shetti , Kevin Ovens , Clive Bittlestone , Robert C. Martin , Robert J. Landers
IPC分类号： H03K3/037 , H03K3/356 , H03K19/173 , H03K19/00
CPC分类号： H03K3/356173 , H03K3/037 , H03K3/356156
摘要： A flip-flop includes a data storage node for driving an inverter (62) and transfer gate (64) combination to transfer data stored on the data node (60) to a master storage node (66). A master cross-coupled latch (68) has two cross-coupled inverters (72) and (74) connected thereto such that the master storage node (66) is only connected to one side of the latch (68). The data node (66) directly drives a slave stage comprised of an inverter (76) and transfer gate (78) which in turn drives a slave storage node (80). The slave storage node (80) is connected to a slave cross-coupled latch (82) comprised of cross-coupled inverters (86) and (88). The slave storage node (80) comprises the Q-output of the inverter. The data is transferred to storage node (66) on the negative going edge of the clock signal and latched thereto on the positive going edge of the clock signal. ON the positive going edge of the clock signal, data is transferred from the storage node (66) to the slave storage node (80) and then latched in the latch (82) on the negative going edge of the clock signal. This results in a minimum number of inverters, thus decreasing the Clock-to-Q time.
摘要翻译：触发器包括用于驱动逆变器（62）和传送门（64）组合以将存储在数据节点（60）上的数据传送到主存储节点（66）的数据存储节点。主交叉耦合锁存器（68）具有连接到其上的两个交叉耦合的反相器（72）和（74），使得主存储节点（66）仅连接到锁存器（68）的一侧。数据节点（66）直接驱动由逆变器（76）和传输门（78）组成的从动级，后者又驱动从存储节点（80）。从存储节点（80）连接到由交叉耦合的反相器（86）和（88）组成的从交叉耦合锁存器（82）。从存储节点（80）包括逆变器的Q输出。数据被传送到时钟信号的负向边缘上的存储节点（66），并在时钟信号的正向沿被锁存在存储节点（66）上。在时钟信号的正向边缘上，数据从存储节点（66）传送到从存储节点（80），然后锁存在时钟信号的负沿的锁存器（82）中。这导致最小数量的反相器，从而减少了Clock-to-Q时间。

9. 发明授权

US06781411B2 Flip flop with reduced leakage current 有权
标题翻译：触发器具有减少的漏电流
公开(公告)号：US06781411B2
公开(公告)日：2004-08-24
申请号：US10256302
申请日：2002-09-27
申请人： Donald E. Steiss , Clive Bittlestone , Peter Cumming , Christopher Barr
发明人： Donald E. Steiss , Clive Bittlestone , Peter Cumming , Christopher Barr
IPC分类号： H03K19173
CPC分类号： H03K3/012 , H03K3/35625 , H03K17/693
摘要： A flip flop (30) comprising a master stage (34) comprising a first plurality of transistors (54, 56), wherein each of the first plurality of transistors comprises a selective conductive path between a source and drain. The flip flop also comprises a slave stage (42) comprising a second plurality of transistors (60, 62, 64, 66), wherein each of the second plurality of transistors comprises a selective conductive path between a source and drain. For the flip flop, in a low power mode the flip flop is operable to receive a first voltage (VDD) coupled to the selective conductive path for each of the first plurality of transistors. Also in the low power mode, the flip flop is operable to receive a second voltage (VDDL) coupled to the selective conductive path for each of the second plurality of transistors. Lastly, the second voltage is greater than the first voltage in the low power mode.
摘要翻译：一种触发器（30），包括包括第一多个晶体管（54,56）的主级（34），其中所述第一多个晶体管中的每一个包括在源极和漏极之间的选择性导电路径。触发器还包括由第二多个晶体管（60,62,64,66）组成的从级（42），其中第二多个晶体管中的每一个包括在源极和漏极之间的选择性导电路径。对于触发器，在低功率模式下，触发器可操作以接收耦合到第一多个晶体管中的每一个的选择导电路径的第一电压（VDD）。同样在低功率模式下，触发器可操作以接收耦合到第二多个晶体管中的每一个的选择性导电路径的第二电压（VDDL）。最后，第二电压大于低功率模式下的第一电压。

10. 发明授权

US06581201B2 Method for power routing and distribution in an integrated circuit with multiple interconnect layers 有权
标题翻译：具有多个互连层的集成电路中的电力布线和分配方法
公开(公告)号：US06581201B2
公开(公告)日：2003-06-17
申请号：US09969378
申请日：2001-10-02
申请人： Francisco A. Cano , David A. Thomas , Clive Bittlestone
发明人： Francisco A. Cano , David A. Thomas , Clive Bittlestone
IPC分类号： G06F1750
CPC分类号： G06F17/5068 , G06F17/5077 , G06F2217/78 , H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit 210 has a power grid formed from a first set of power buses 201a and 202a on a metal interconnect level M1, a second set of power buses 203a and 204a on interconnect level M4, and a third set of power buses 205a and 206a on interconnect level M5. The set of power buses on level M4 are oriented in the same direction as the set of power buses on level M1, and both sets of buses are located coincidentally. A high power logic cell 220 is pre-defined with a set of M1-M4 power vias 221 and 222 so that logic cell 220 can be positioned in a horizontal row unconstrained by pre-positioned M1-M4 power vias. Dummy cell 230 with M1-M4 power vias is positioned as needed so as not to exceed a maximum strapping distance D1. A maximum value for distance D1 is selected based on dynamic power requirements of nearby logic cells 250a-n as determined by simulation. A method for designing and fabricating integrated circuit 210 is described.
摘要翻译：集成电路210具有由金属互连级M1上的第一组电源总线201a和202a形成的电网，以及互连级M4上的第二组电源总线203a和204a以及第三组电源总线205a和206a 在互连级别M5上。 M4级的电力总线集合方向与M1级的电力总线相同，两组总线同时定位。高功率逻辑单元220用一组M1-M4电源通孔221和222预定义，使得逻辑单元220可以被定位在不受预定义的M1-M4电源通孔约束的水平行中。具有M1-M4电源通孔的假电池230根据需要定位，以便不超过最大捆扎距离D1。基于通过仿真确定的附近的逻辑单元250a-n的动态功率要求来选择距离D1的最大值。描述了集成电路210的设计和制造方法。

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