专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20070293031A1 SPLIT POLY-SiGe/POLY-Si ALLOY GATE STACK 有权
标题翻译：分散多晶硅/多晶硅合金栅极堆叠
公开(公告)号：US20070293031A1
公开(公告)日：2007-12-20
申请号：US11847384
申请日：2007-08-30
申请人： Kevin Chan , Jia Chen , Shih-Fen Huang , Edward Nowak
发明人： Kevin Chan , Jia Chen , Shih-Fen Huang , Edward Nowak
IPC分类号： H01L21/3205
CPC分类号： H01L21/2807 , H01L21/28052 , H01L21/28061 , H01L21/823835 , H01L21/823842 , H01L29/4916 , H01L29/4925 , H01L29/665
摘要： A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiO2 or SixGeyOz interfacial layer of 3 to 4 A thick. The thin SiO2 or SixGeyOz interfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of the subsequently deposited layer of cobalt. The gate electrode stack structure is used for both nFETs and pFETs.
摘要翻译：在栅极电介质上的硅纳米晶种子层上形成场效应晶体管器件的多层栅电极堆叠结构。硅纳米晶体层的小晶粒尺寸允许使用原位快速热化学气相沉积（RTCVD）沉积高达至少70％的[Ge]的均匀且连续的多晶硅层。在快速降低的温度下在氧气环境中原位吹扫沉积室导致薄的SiO 2或Si x O x O O 3至4厚的界面层。薄的SiO 2或Si x Si 2 O 3界面层足够薄且不连续以提供很小的电阻到栅极电流仍具有足够的[O]以在热处理期间有效地阻挡Ge扩散，从而允许后续沉积的钴的硅化物。栅电极堆叠结构用于nFET和pFET两者。

2. 发明申请

US20050199906A1 Split poly-SiGe/poly-Si alloy gate stack 有权
标题翻译：分离多晶硅/多晶硅合金栅叠层
公开(公告)号：US20050199906A1
公开(公告)日：2005-09-15
申请号：US11124978
申请日：2005-05-09
申请人： Kevin Chan , Jia Chen , Shih-Fen Huang , Edward Nowak
发明人： Kevin Chan , Jia Chen , Shih-Fen Huang , Edward Nowak
IPC分类号： H01L20060101 , H01L21/335 , H01L21/336 , H01L21/8238 , H01L29/24 , H01L29/49 , H01L29/76 , H01L31/072 , H01L31/119
CPC分类号： H01L21/2807 , H01L21/28052 , H01L21/28061 , H01L21/823835 , H01L21/823842 , H01L29/4916 , H01L29/4925 , H01L29/665
摘要： A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiO2 or SixGeyOz interfacial layer of 3 to 4 A thick. The thin SiO2 or SixGeyOz interfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of the subsequently deposited layer of cobalt. The gate electrode stack structure is used for both nFETs and pFETs.
摘要翻译：在栅极电介质上的硅纳米晶种子层上形成场效应晶体管器件的多层栅电极堆叠结构。硅纳米晶体层的小晶粒尺寸允许使用原位快速热化学气相沉积（RTCVD）沉积高达至少70％的[Ge]的均匀且连续的多晶硅层。在快速降低的温度下在氧气环境中原位吹扫沉积室导致薄的SiO 2或Si x O x O O 3至4厚的界面层。薄的SiO 2或Si x Si 2 O 3界面层足够薄且不连续以提供很小的电阻到栅极电流仍具有足够的[O]以在热处理期间有效地阻挡Ge扩散，从而允许后续沉积的钴的硅化物。栅电极堆叠结构用于nFET和pFET两者。

3. 发明申请

US20050073014A1 Split poly-SiGe/poly-Si alloy gate stack 有权
标题翻译：分离多晶硅/多晶硅合金栅叠层
公开(公告)号：US20050073014A1
公开(公告)日：2005-04-07
申请号：US10680820
申请日：2003-10-07
申请人： Kevin Chan , Jia Chen , Shih-Fen Huang , Edward Nowak
发明人： Kevin Chan , Jia Chen , Shih-Fen Huang , Edward Nowak
IPC分类号： H01L20060101 , H01L21/335 , H01L21/336 , H01L21/8238 , H01L29/24 , H01L29/49 , H01L29/76 , H01L31/072 , H01L31/119
CPC分类号： H01L21/2807 , H01L21/28052 , H01L21/28061 , H01L21/823835 , H01L21/823842 , H01L29/4916 , H01L29/4925 , H01L29/665
摘要： A multi-layered gate electrode stack structure of a field effect transistor device is formed on a silicon nano crystal seed layer on the gate dielectric. The small grain size of the silicon nano crystal layer allows for deposition of a uniform and continuous layer of poly-SiGe with a [Ge] of up to at least 70% using in situ rapid thermal chemical vapor deposition (RTCVD). An in-situ purge of the deposition chamber in a oxygen ambient at rapidly reduced temperatures results in a thin SiO2 or SixGeyOz interfacial layer of 3 to 4 A thick. The thin SiO2 or SixGeyOz interfacial layer is sufficiently thin and discontinuous to offer little resistance to gate current flow yet has sufficient [O] to effectively block upward Ge diffusion during heat treatment to thereby allow silicidation of the subsequently deposited layer of cobalt. The gate electrode stack structure is used for both nFETs and pFETs.
摘要翻译：在栅极电介质上的硅纳米晶种子层上形成场效应晶体管器件的多层栅电极堆叠结构。硅纳米晶体层的小晶粒尺寸允许使用原位快速热化学气相沉积（RTCVD）沉积高达至少70％的[Ge]的均匀且连续的多晶硅层。在快速降低的温度下在氧环境中原位吹扫沉积室导致3至4厚度的薄SiO 2或SixGeyOz界面层。薄的SiO 2或SixGeyOz界面层是足够薄且不连续的，以提供对栅极电流的很小的阻力，但是具有足够的[O]以在热处理期间有效阻挡向上的Ge扩散，从而允许随后沉积的钴的硅化物。栅电极堆叠结构用于nFET和pFET两者。

4. 发明申请

US20070122957A1 LOW-COST FEOL FOR ULTRA-LOW POWER, NEAR SUB-VTH DEVICE STRUCTURES 有权
标题翻译：低功耗超低功耗，小型设备结构
公开(公告)号：US20070122957A1
公开(公告)日：2007-05-31
申请号：US11164651
申请日：2005-11-30
申请人： Brent Anderson , Andres Bryant , William Clark , Jeffrey Gambino , Shih-Fen Huang , Edward Nowak , Anthony Stamper
发明人： Brent Anderson , Andres Bryant , William Clark , Jeffrey Gambino , Shih-Fen Huang , Edward Nowak , Anthony Stamper
IPC分类号： H01L21/8234 , H01L29/76 , H01L21/336
CPC分类号： H01L21/823412 , H01L21/823418 , H01L29/6653 , H01L29/66545 , H01L29/78
摘要： In order to reduce power dissipation requirements, obtain full potential transistor performance and avoid power dissipation limitations on transistor performance in high density integrated circuits, transistors are operated in a sub-threshold (sub-Vth) or a near sub-Vth voltage regime (generally about 0.2 volts rather than a super-Vth regime of about 1.2 volts or higher) and optimized for such operation, particularly through simplification of the transistor structure, since intrinsic channel resistance is dominant in sub-Vth operating voltage regimes. Such simplifications include an underlap or recess of the source and drain regions from the gate which avoids overlap capacitance to partially recover loss of switching speed otherwise caused by low voltage operation, an ultra-thin gate structure having a thickness of 500 Å or less which also simplifies forming connections to the transistor and an avoidance of silicidation or alloy formation in the source, drain and/or gate of transistors.
摘要翻译：为了降低功耗要求，获得全电位晶体管性能并避免在高密度集成电路中对晶体管性能的功率限制，晶体管以子阈值（sub-V thth th）或接近次级V th电压方式（通常约为0.2伏，而不是大于1.2伏特或更高的超V 2），并且针对这种操作进行了优化，特别是通过简化的晶体管结构，因为固有沟道电阻在次级V 3工作电压方面是主要的。这种简化包括来自栅极的源极和漏极区域的欠叠或凹陷，其避免重叠电容以部分恢复由低电压操作引起的切换速度的损失，厚度为或等于或小于500埃的超薄栅极结构简化了与晶体管的形成连接，避免了晶体管的源极，漏极和/或栅极中的硅化或合金形成。

5. 发明申请

US20070102747A1 COMPLEMENTARY CARBON NANOTUBE TRIPLE GATE TECHNOLOGY 有权
标题翻译：补充碳纳米管三叶栅技术
公开(公告)号：US20070102747A1
公开(公告)日：2007-05-10
申请号：US11164109
申请日：2005-11-10
申请人： Jia Chen , Edward Nowak
发明人： Jia Chen , Edward Nowak
IPC分类号： H01L29/76
CPC分类号： H01L51/055 , B82Y10/00 , H01L27/283 , H01L51/0048 , H01L51/0558 , Y10S977/742 , Y10S977/94
摘要： Disclosed is a CNT technology that overcomes the intrinsic ambipolar properties of CNTFETs. One embodiment of the invention provides either a stable p-type CNTFET or a stable n-type CNTFET. Another embodiment of the invention provides a complementary CNT device. In order to overcome the ambipolar properties of a CNTFET, source/drain gates are introduced below the CNT opposite the source/drain electrodes. These source/drain gates are used to apply either a positive or negative voltage to the ends of the CNT so as to configure the corresponding FET as either an n-type or p-type CNTFET, respectively. Two adjacent CNTFETs, configured such that one is an n-type CNTFET and the other is a p-type CNTFET, can be incorporated into a complementary CNT device. In order to independently adjust threshold voltage of an individual CNTFET, a back gate can also be introduced below the CNT and, particularly, below the channel region of the CNT opposite the front gate. In this manner parasitic capacitances and resistances are minimized.
摘要翻译：公开了克服CNTFET的固有双极性能的CNT技术。本发明的一个实施例提供稳定的p型CNTFET或稳定的n型CNTFET。本发明的另一实施例提供了一种互补的CNT器件。为了克服CNTFET的双极性质，源极/漏极栅极被引入到与源极/漏极电极相对的CNT之下。这些源极/漏极栅极用于向CNT的端部施加正或负电压，以将相应的FET分别构造为n型或p型CNTFET。可以将两个相邻的CNTFET配置成互补CNT器件，其被配置为使得一个是n型CNTFET，另一个是p型CNTFET。为了独立地调节各个CNTFET的阈值电压，也可以在CNT下面，特别是在与前栅极相对的CNT的沟道区下方引入背栅。以这种方式，寄生电容和电阻最小化。

6. 发明申请

US20120119681A1 LIGHT DEVICES AND SYSTEMS 审中-公开
标题翻译：光设备和系统
公开(公告)号：US20120119681A1
公开(公告)日：2012-05-17
申请号：US12946682
申请日：2010-11-15
申请人： Ken Seidl , Edward Nowak , Paul Li
发明人： Ken Seidl , Edward Nowak , Paul Li
IPC分类号： H05B37/00
CPC分类号： H05B37/0272
摘要： The present invention provides switches and sensors that automatically turn on and/or off an associated device. In particular, the present invention provides lighting devices containing switches and sensors associated with the device that power/depower the device and systems and objects containing the device.
摘要翻译：本发明提供了自动打开和/或关闭相关设备的开关和传感器。特别地，本发明提供了包含与该装置相关联的开关和传感器的照明装置，其对设备和包含该装置的系统和对象进行功率/耗尽。

7. 发明申请

US20080113476A1 DUAL-PLANE COMPLEMENTARY METAL OXIDE SEMICONDUCTOR 有权
标题翻译：双平面补充金属氧化物半导体
公开(公告)号：US20080113476A1
公开(公告)日：2008-05-15
申请号：US12014850
申请日：2008-01-16
申请人： Brent Anderson , Edward Nowak
发明人： Brent Anderson , Edward Nowak
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823828 , H01L29/7842 , H01L29/7848 , H01L29/785 , H01L29/78687
摘要： Embodiments herein present a device, method, etc. for a dual-plane complementary metal oxide semiconductor. The device comprises a fin-type transistor on a bulk silicon substrate. The fin-type transistor comprises outer fin regions and a center semiconductor fin region, wherein the center fin region has a {110} crystalline oriented channel surface. The outer fin regions comprise a strain inducing impurity that stresses the center semiconductor fin region. The strain inducing impurity contacts the bulk silicon substrate, wherein the strain inducing impurity comprises germanium and/or carbon. Further, the fin-type transistor comprises a thick oxide member on a top face thereof. The fin-type transistor also comprises a first transistor on a first crystalline oriented surface, wherein the device further comprises a second transistor on a second crystalline oriented surface that differs from the first crystalline oriented surface.
摘要翻译：本文的实施方案提供了用于双平面互补金属氧化物半导体的器件，方法等。该器件包括在体硅衬底上的鳍式晶体管。鳍型晶体管包括外鳍区域和中心半导体鳍片区域，其中中心鳍片区域具有{110}晶体取向沟道表面。外鳍区域包括应力诱导杂质的应变中心半导体鳍片区域的应变。诱发杂质的应变接触体硅衬底，其中应变诱导杂质包括锗和/或碳。此外，鳍型晶体管在其顶面包括厚氧化物构件。翅片型晶体管还包括在第一晶体取向表面上的第一晶体管，其中该器件还包括与第一结晶定向表面不同的第二晶体取向表面上的第二晶体管。

8. 发明申请

US20080042205A1 LOW-COST HIGH-PERFORMANCE PLANAR BACK-GATE CMOS 有权
标题翻译：低成本高性能平面背栅CMOS
公开(公告)号：US20080042205A1
公开(公告)日：2008-02-21
申请号：US11877865
申请日：2007-10-24
申请人： Edward Nowak
发明人： Edward Nowak
IPC分类号： H01L21/8238
CPC分类号： H01L21/823828 , H01L21/743 , H01L21/84 , H01L29/665 , H01L29/66553 , H01L29/66621 , H01L29/6675 , H01L29/78636 , H01L29/78648 , Y10S438/914
摘要： A method of fabricating a high-performance planar back-gate CMOS structure having superior short-channel characteristics and reduced capacitance using processing steps that are not too lengthy or costly is provided. Also provided is a high-performance planar back-gate CMOS structure that is formed utilizing the method of the present invention. The method includes forming an opening in an upper surface of a substrate. Thereafter, a dopant region is formed in the substrate through the opening. In accordance with the inventive method, the dopant region defines a back-gate conductor of the inventive structure. Next, a front gate conductor having at least a portion thereof is formed within the opening.
摘要翻译：提供了一种使用不太长或昂贵的处理步骤来制造具有优异的短沟道特性和减小电容的高性能平面背栅CMOS结构的方法。还提供了利用本发明的方法形成的高性能平面背栅CMOS结构。该方法包括在基板的上表面形成开口。此后，通过开口在衬底中形成掺杂剂区域。根据本发明的方法，掺杂剂区域限定本发明结构的背栅导体。接下来，在开口内形成具有至少一部分的前门导体。

9. 发明申请

US20070290250A1 MULTIPLE DIELECTRIC FINFET STRUCTURE AND METHOD 审中-公开
标题翻译：多电介质FinFET结构与方法
公开(公告)号：US20070290250A1
公开(公告)日：2007-12-20
申请号：US11845972
申请日：2007-08-28
申请人： William Clark , Edward Nowak
发明人： William Clark , Edward Nowak
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211 , H01L29/66795 , H01L29/66818
摘要： Disclosed is a method and structure for a fin-type field effect transistor (FinFET) structure that has different thickness gate dielectrics covering the fins extending from the substrate. These fins have a central channel region and source and drain regions on opposite sides of the channel region. The thicker gate dielectrics can comprise multiple layers of dielectric and the thinner gate dielectrics can comprise less layers of dielectric. A cap comprising a different material than the gate dielectrics can be positioned over the fins.
摘要翻译：公开了一种鳍式场效应晶体管（FinFET）结构的方法和结构，其具有覆盖从衬底延伸的翅片的不同厚度的栅极电介质。这些翅片在通道区域的相对侧具有中心通道区域和源极和漏极区域。较厚的栅极电介质可以包括多层电介质，较薄的栅极电介质可以包含更少的电介质层。包括与栅极电介质不同的材料的盖可以位于鳍片上方。

10. 发明申请

US20070252241A1 LOW-CAPACITANCE CONTACT FOR LONG GATE-LENGTH DEVICES WITH SMALL CONTACTED PITCH 有权
公开(公告)号：US20070252241A1
公开(公告)日：2007-11-01
申请号：US11767635
申请日：2007-06-25
申请人： Brent Anderson , Edward Nowak
发明人： Brent Anderson , Edward Nowak
IPC分类号： H01L29/94 , H01L21/336 , H01L29/76 , H01L29/06
CPC分类号： H01L29/785 , H01L21/823431 , H01L21/823456 , H01L27/088 , H01L27/0886 , H01L27/1211 , H01L29/41791 , H01L29/66795 , H01L2029/7858
摘要： Disclosed are planar and non-planar field effect transistor (FET) structures and methods of forming the structures. The structures comprise segmented active devices (e.g., multiple semiconductor fins for a non-planar transistor or multiple semiconductor layer sections for a planar transistor) connected at opposite ends to source/drain bridges. A gate electrode is patterned on the segmented active devices between the source/drain bridges such that it has a reduced length between the segments (i.e., between the semiconductor fins or sections). Source/drain contacts land on the source/drain bridges such that they are opposite only those portions of the gate electrode with the reduced gate length. These FET structures can be configured to simultaneously maximize the density of the transistor, minimize leakage power and maintain the parasitic capacitance between the source/drain contacts and the gate conductor below a preset level, depending upon the performance and density requirements.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式