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1. 发明申请

US20070290250A1 MULTIPLE DIELECTRIC FINFET STRUCTURE AND METHOD 审中-公开
标题翻译：多电介质FinFET结构与方法
公开(公告)号：US20070290250A1
公开(公告)日：2007-12-20
申请号：US11845972
申请日：2007-08-28
申请人： William Clark , Edward Nowak
发明人： William Clark , Edward Nowak
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L21/845 , H01L27/1211 , H01L29/66795 , H01L29/66818
摘要： Disclosed is a method and structure for a fin-type field effect transistor (FinFET) structure that has different thickness gate dielectrics covering the fins extending from the substrate. These fins have a central channel region and source and drain regions on opposite sides of the channel region. The thicker gate dielectrics can comprise multiple layers of dielectric and the thinner gate dielectrics can comprise less layers of dielectric. A cap comprising a different material than the gate dielectrics can be positioned over the fins.
摘要翻译：公开了一种鳍式场效应晶体管（FinFET）结构的方法和结构，其具有覆盖从衬底延伸的翅片的不同厚度的栅极电介质。这些翅片在通道区域的相对侧具有中心通道区域和源极和漏极区域。较厚的栅极电介质可以包括多层电介质，较薄的栅极电介质可以包含更少的电介质层。包括与栅极电介质不同的材料的盖可以位于鳍片上方。

2. 发明申请

US20070224743A1 THERMAL DISSIPATION STRUCTURES FOR FINFETS 有权
标题翻译： FINFET的热释放结构
公开(公告)号：US20070224743A1
公开(公告)日：2007-09-27
申请号：US11756078
申请日：2007-05-31
申请人： Brent Anderson , Edward Nowak , Jed Rankin , William Clark
发明人： Brent Anderson , Edward Nowak , Jed Rankin , William Clark
IPC分类号： H01L21/84
CPC分类号： H01L29/78606 , H01L27/0248 , H01L29/42384 , H01L29/785
摘要： A fin-type field effect transistor has an insulator layer above a substrate and a fin extending above the insulator layer. The fin has a channel region, and source and drain regions. A gate conductor is positioned over the channel region. The insulator layer includes a heat dissipating structural feature adjacent the fin, and a portion of the gate conductor contacts the heat dissipating structural feature. The heat dissipating structural feature can comprise a recess within the insulator layer or a thermal conductor extending through the insulator layer.
摘要翻译：翅片型场效应晶体管具有在衬底上方的绝缘体层和在绝缘体层上方延伸的翅片。鳍片有一个通道区域，以及源极和漏极区域。栅极导体位于沟道区域的上方。绝缘体层包括邻近翅片的散热结构特征，并且栅极导体的一部分接触散热结构特征。散热结构特征可以包括绝缘体层内的凹槽或延伸穿过绝缘体层的热导体。

3. 发明申请

US20050272195A1 Integrated circuit having pairs of parallel complementary finfets 失效
标题翻译：具有并联互补鳍对的集成电路
公开(公告)号：US20050272195A1
公开(公告)日：2005-12-08
申请号：US11186748
申请日：2005-07-21
申请人： Andres Bryant , William Clark , David Fried , Mark Jaffe , Edward Nowak , John Pekarik , Christopher Putnam
发明人： Andres Bryant , William Clark , David Fried , Mark Jaffe , Edward Nowak , John Pekarik , Christopher Putnam
IPC分类号： H01L21/308 , H01L21/336 , H01L21/84 , H01L27/12 , H01L29/786 , H01L21/8232
CPC分类号： H01L21/84 , H01L21/3086 , H01L21/3088 , H01L21/823821 , H01L27/1203 , H01L29/66795 , H01L29/785 , Y10S438/947
摘要： A method and structure for an integrated circuit structure that utilizes complementary fin-type field effect transistors (FinFETs) is disclosed. The invention has a first-type of FinFET which includes a first fin, and a second-type of FinFET which includes a second fin running parallel to the first fin. The invention also has an insulator fin positioned between the source/drain regions of the first first-type of FinFET and the second-type of FinFET. The insulator fin has approximately the same width dimensions as the first fin and the second fin, such that the spacing between the first-type of FinFET and the second-type of FinFET is approximately equal to the width of one fin. The invention also has a common gate formed over channel regions of the first-type of FinFET and the second-type of FinFET. The gate includes a first impurity doping region adjacent the first-type of FinFET and a second impurity doping region adjacent the second-type of FinFET. The differences between the first impurity doping region and the second impurity doping region provide the gate with different work functions related to differences between the first-type of FinFET and the second-type of FinFET. The first fin and the second fin have approximately the same width.
摘要翻译：公开了利用互补翅片型场效应晶体管（FinFET）的集成电路结构的方法和结构。本发明具有包括第一鳍片的第一类型的FinFET和包括与第一鳍片平行的第二鳍片的第二类型的FinFET。本发明还具有位于第一第一类型FinFET的源极/漏极区域和第二类型FinFET之间的绝缘体鳍片。绝缘体鳍片具有与第一鳍片和第二鳍片大致相同的宽度尺寸，使得第一类型的FinFET和第二类型的FinFET之间的间隔大致等于一个鳍片的宽度。本发明还具有形成在第一类型FinFET和第二类型FinFET的沟道区上的公共栅极。栅极包括与第一类型的FinFET相邻的第一杂质掺杂区域和与第二类型的FinFET相邻的第二杂质掺杂区域。第一杂质掺杂区域和第二杂质掺杂区域之间的差异为栅极提供与第一类型FinFET和第二类型FinFET之间的差异有关的不同功函数。第一鳍片和第二鳍片具有大致相同的宽度。

4. 发明申请

US20050001273A1 INTEGRATED CIRCUIT HAVING PAIRS OF PARALLEL COMPLEMENTARY FINFETS 有权
标题翻译：具有并联补偿器件对的集成电路
公开(公告)号：US20050001273A1
公开(公告)日：2005-01-06
申请号：US10604206
申请日：2003-07-01
申请人： Andres Bryant , William Clark , David Fried , Mark Jaffe , Edward Nowak , John Pekarik , Christopher Putnam
发明人： Andres Bryant , William Clark , David Fried , Mark Jaffe , Edward Nowak , John Pekarik , Christopher Putnam
IPC分类号： H01L21/308 , H01L21/336 , H01L21/84 , H01L27/12 , H01L29/786 , H01L33/00
CPC分类号： H01L21/84 , H01L21/3086 , H01L21/3088 , H01L21/823821 , H01L27/1203 , H01L29/66795 , H01L29/785 , Y10S438/947
摘要： A method and structure for an integrated circuit structure that utilizes complementary fin-type field effect transistors (FinFETs) is disclosed. The invention has a first-type of FinFET which includes a first fin, and a second-type of FinFET which includes a second fin running parallel to the first fin. The invention also has an insulator fin positioned between the source/drain regions of the first first-type of FinFET and the second-type of FinFET. The insulator fin has approximately the same width dimensions as the first fin and the second fin, such that the spacing between the first-type of FinFET and the second-type of FinFET is approximately equal to the width of one fin. The invention also has a common gate formed over channel regions of the first-type of FinFET and the second-type of FinFET. The gate includes a first impurity doping region adjacent the first-type of FinFET and a second impurity doping region adjacent the second-type of FinFET. The differences between the first impurity doping region and the second impurity doping region provide the gate with different work functions related to differences between the first-type of FinFET and the second-type of FinFET. The first fin and the second fin have approximately the same width.
摘要翻译：公开了利用互补翅片型场效应晶体管（FinFET）的集成电路结构的方法和结构。本发明具有包括第一鳍片的第一类型的FinFET和包括与第一鳍片平行的第二鳍片的第二类型的FinFET。本发明还具有位于第一第一类型FinFET的源极/漏极区域和第二类型FinFET之间的绝缘体鳍片。绝缘体鳍片具有与第一鳍片和第二鳍片大致相同的宽度尺寸，使得第一类型的FinFET和第二类型的FinFET之间的间隔大致等于一个鳍片的宽度。本发明还具有形成在第一类型FinFET和第二类型FinFET的沟道区上的公共栅极。栅极包括与第一类型的FinFET相邻的第一杂质掺杂区域和与第二类型的FinFET相邻的第二杂质掺杂区域。第一杂质掺杂区域和第二杂质掺杂区域之间的差异为栅极提供与第一类型FinFET和第二类型FinFET之间的差异有关的不同功函数。第一鳍片和第二鳍片具有大致相同的宽度。

5. 发明申请

US20070102789A1 BIPOLAR TRANSISTOR AND BACK-GATED TRANSISTOR STRUCTURE AND METHOD 审中-公开
标题翻译：双极晶体管和后置栅极结构和方法
公开(公告)号：US20070102789A1
公开(公告)日：2007-05-10
申请号：US11164071
申请日：2005-11-09
申请人： Andres Bryant , William Clark , Edward Nowak
发明人： Andres Bryant , William Clark , Edward Nowak
IPC分类号： H01L27/082
CPC分类号： H01L21/84 , H01L21/8249 , H01L27/0623 , H01L27/1203 , H01L29/0804 , H01L29/7327 , H01L29/78648
摘要： A structure is disclosed including a substrate including an insulator layer on a bulk layer, and a bipolar transistor in a first region of the substrate, the bipolar transistor including at least a portion of an emitter region in the insulator layer. Another disclosed structure includes an inverted bipolar transistor in a first region of a substrate including an insulator layer on a bulk layer, the inverted bipolar transistor including an emitter region, and a back-gated transistor in a second region of the substrate, wherein a back-gate conductor of the back-gated transistor and at least a portion of the emitter region are in the same layer of material. A method of forming the structures including a bipolar transistor and back-gated transistor together is also disclosed.
摘要翻译：公开了一种结构，其包括在体层上包括绝缘体层的衬底和在衬底的第一区域中的双极晶体管，所述双极晶体管包括绝缘体层中的发射极区域的至少一部分。另一公开的结构包括在衬底的第一区域中的反相双极晶体管，其包括体层上的绝缘体层，反相双极晶体管包括发射极区域，以及位于衬底的第二区域中的后栅极晶体管，其中背面背栅式晶体管的栅极导体和发射极区域的至少一部分处于相同的材料层中。还公开了一种将双极晶体管和后栅极晶体管组合在一起的结构的方法。

6. 发明申请

US20060234456A1 FOUR-BIT FINFET NVRAM MEMORY DEVICE 有权
标题翻译：四位FINFET NVRAM存储器件
公开(公告)号：US20060234456A1
公开(公告)日：2006-10-19
申请号：US11426623
申请日：2006-06-27
申请人： Brent Anderson , William Clark , Edward Nowak
发明人： Brent Anderson , William Clark , Edward Nowak
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , G11C16/0475 , H01L27/115 , H01L27/11521 , H01L29/66795 , H01L29/7887 , Y10S438/954
摘要： A four-bit FinFET memory cell, a method of fabricating a four-bit FinFET memory cell and an NVRAM formed of four-bit FINFET memory cells. The four-bit memory cell including two charge storage regions in opposite ends of a dielectric layer on a first sidewall of a fin of a FinFET and two additional charge storage regions in opposite ends of a dielectric layer on a second sidewall of the fin of the FinFET, the first and second sidewalls being opposite one another.
摘要翻译：四位FinFET存储单元，制造四位FinFET存储单元的方法和由四位FINFET存储单元形成的NVRAM。该四位存储单元包括在FinFET的鳍的第一侧壁上的电介质层的相对端中的两个电荷存储区，以及位于鳍的翅片的第二侧壁上的电介质层的相对端中的两个附加电荷存储区 FinFET，第一和第二侧壁彼此相对。

7. 发明申请

US20050275045A1 LOW CAPACITANCE FET FOR OPERATION AT SUBTHRESHOLD VOLTAGES 有权
标题翻译：用于低压电压运行的低电容FET
公开(公告)号：US20050275045A1
公开(公告)日：2005-12-15
申请号：US10710007
申请日：2004-06-11
申请人： Brent Anderson , Andres Bryant , William Clark , Edward Nowak
发明人： Brent Anderson , Andres Bryant , William Clark , Edward Nowak
IPC分类号： H01L21/336 , H01L29/10 , H01L29/76 , H01L29/78 , H01L29/786
CPC分类号： H01L29/7833 , H01L29/1045 , H01L29/66537 , H01L29/6656 , H01L29/66583 , H01L29/7835 , H01L29/785
摘要： A field effect transistor (FET) has underlap regions adjacent to the channel doping region. The underlap regions have very low dopant concentrations of less than 1×1017/cc or 5×1016/cc and so tend to have a high resistance. The underlap regions reduce overlap capacitance and thereby increase switching speed. High resistance of the underlap regions is not problematic at subthreshold voltages because the channel doping region also has a high resistance at subthreshold voltages. Consequently, the present FET has low capacitance and high speed and is particularly well suited for operation in the subthreshold regime.
摘要翻译：场效应晶体管（FET）具有与沟道掺杂区域相邻的底部区域。底层区域具有小于1×10 17 / cc或5×10 16 / cc的非常低的掺杂剂浓度，因此倾向于具有高电阻。下层区域减少重叠电容，从而提高开关速度。欠电压区域的高电阻在亚阈值电压下是没有问题的，因为沟道掺杂区域在亚阈值电压下也具有高电阻。因此，本FET具有低电容和高速度，并且特别适合于在亚阈值状态下操作。

8. 发明申请

US20070010049A1 THERMAL DISSIPATION STRUCTURES FOR FINFETS 失效
公开(公告)号：US20070010049A1
公开(公告)日：2007-01-11
申请号：US11160360
申请日：2005-06-21
申请人： Brent Anderson , Edward Nowak , Jed Rankin , William Clark
发明人： Brent Anderson , Edward Nowak , Jed Rankin , William Clark
IPC分类号： H01L21/8234
CPC分类号： H01L29/78606 , H01L27/0248 , H01L29/42384 , H01L29/785
摘要： A fin-type field effect transistor has an insulator layer above a substrate and a fin extending above the insulator layer. The fin has a channel region, and source and drain regions. A gate conductor is positioned over the channel region. The insulator layer includes a heat dissipating structural feature adjacent the fin, and a portion of the gate conductor contacts the heat dissipating structural feature. The heat dissipating structural feature can comprise a recess within the insulator layer or a thermal conductor extending through the insulator layer.

9. 发明申请

US20060244062A1 SILICON-ON-INSULATOR BASED RADIATION DETECTION DEVICE AND METHOD 有权
标题翻译：基于绝缘体的绝缘体辐射检测装置及方法
公开(公告)号：US20060244062A1
公开(公告)日：2006-11-02
申请号：US10908117
申请日：2005-04-28
申请人： William Clark , Edward Nowak
发明人： William Clark , Edward Nowak
IPC分类号： H01L27/12
CPC分类号： H01L29/78648
摘要： Structures and a method for detecting ionizing radiation using silicon-on-insulator (SOI) technology are disclosed. In one embodiment, the invention includes a substrate having a buried insulator layer formed over the substrate and an active layer formed over the buried insulator layer. Active layer may be fully depleted. A transistor is formed over the active layer, and includes a first gate conductor, a first gate dielectric and source/drain diffusion regions. The first gate conductor may include a material having a substantially (or fully) depleted doping concentration such that it has a resistivity higher than doped polysilicon such as intrinsic polysilicon. A second gate conductor is formed below the buried insulator layer and provides a second gate dielectric corresponding to the second gate conductor. A channel region between the first gate conductor and the second gate conductor is controlled by the second gate conductor (back gate) such that it acts as a radiation detector.
摘要翻译：公开了使用绝缘体上硅（SOI）技术检测电离辐射的结构和方法。在一个实施例中，本发明包括具有在衬底上形成的掩埋绝缘体层的衬底和形成在掩埋绝缘体层上的有源层。活性层可能完全耗尽。在有源层上形成晶体管，并且包括第一栅极导体，第一栅极电介质和源极/漏极扩散区。第一栅极导体可以包括具有基本（或完全）耗尽的掺杂浓度的材料，使得其具有比诸如本征多晶硅的掺杂多晶硅更高的电阻率。第二栅极导体形成在掩埋绝缘体层下方，并提供对应于第二栅极导体的第二栅极电介质。第一栅极导体和第二栅极导体之间的沟道区域由第二栅极导体（背栅极）控制，使得其作为辐射检测器。

10. 发明申请

US20070187769A1 ULTRA-THIN LOGIC AND BACKGATED ULTRA-THIN SRAM 失效
标题翻译：超薄逻辑和背面超薄SRAM
公开(公告)号：US20070187769A1
公开(公告)日：2007-08-16
申请号：US11276135
申请日：2006-02-15
申请人： Brent Anderson , Andres Bryant , William Clark , Edward Nowak
发明人： Brent Anderson , Andres Bryant , William Clark , Edward Nowak
IPC分类号： H01L21/337 , H01L29/94
CPC分类号： H01L27/1203 , H01L21/84 , H01L27/11
摘要： Disclosed are embodiments of a structure that comprises a first device, having multiple FETs, and a second device, having at least one FET. Sections of a first portion of a semiconductor layer below the first device are doped and contacted to form back gates. A second portion of the semiconductor layer below the second device remains un-doped and un-contacted and, thus, functions as an insulator. Despite the performance degradation of the first device due to back gate capacitance, the back gates result in a net gain for devices such as, SRAM cells, which require precise Vt control. Contrarily, despite marginal Vt control in the second device due to the absence of back gates, the lack of capacitance loading and the added insulation result in a net gain for high performance devices such as, logic circuits.
摘要翻译：公开了包括具有多个FET的第一器件和具有至少一个FET的第二器件的结构的实施例。第一器件下方的半导体层的第一部分的部分被掺杂并接触以形成后栅极。第二器件下方的半导体层的第二部分保持未掺杂和未接触，并因此用作绝缘体。尽管由于背栅电容而导致第一器件的性能下降，但是后栅导致需要精确Vt控制的诸如SRAM单元的器件的净增益。相反，尽管由于不存在后门而导致第二器件中的边缘Vt控制，但由于缺少电容负载和增加的绝缘，导致高性能器件（如逻辑电路）的净增益。

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