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1. 发明授权

US07380179B2 High reliability memory module with a fault tolerant address and command bus 有权
标题翻译：高可靠性存储器模块，具有容错地址和命令总线
公开(公告)号：US07380179B2
公开(公告)日：2008-05-27
申请号：US11406669
申请日：2006-04-20
申请人： Kevin C. Gower , Bruce Hazelzet , Mark W. Kellogg , David T. Perlman
发明人： Kevin C. Gower , Bruce Hazelzet , Mark W. Kellogg , David T. Perlman
IPC分类号： G06F11/00 , G11C29/00
CPC分类号： H05K1/117 , G06F11/1044 , G11C5/04 , G11C2029/0409 , H05K2201/09145 , H05K2203/167
摘要： A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32K bit serial EE PROM and a 28 bit and a 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/Parity register. By providing the module with a fault tolerant address and command bus fault-tolerance and self-healing aspects necessary for autonomic computing systems compatible with industry-standards is realized. The memory module corrects single bit errors on the command or address bus and permits continuous memory operation independent of the existence of these errors and can determine any double bit error condition. The redundant contacts on the module prevents what would otherwise be single points of failure.
摘要翻译：具有容错地址和命令总线的高可靠性双列直插式存储器模块，用于服务器。存储器模块是大约151.35mm或5.97英寸长的卡，其具有大约多个触点，其中一些是冗余的，多个DRAM，锁相环，2或32K位串行EE PROM和28位和具有纠错码（ECC），奇偶校验，用于经由独立总线读取的多字节故障报告电路的1至2寄存器和用于确定和报告耦合到服务器存储器的可纠正错误和不可校正错误状况的实时错误行接口芯片和存储器控制器或处理器，使得存储器控制器通过地址/命令行将地址和命令信息与用于纠错目的的校验位一起发送到ECC /奇偶校验寄存器。通过为模块提供与行业标准兼容的自主计算系统所需的容错地址和命令总线容错和自修复方面。存储器模块纠正命令或地址总线上的单位错误，并允许连续存储器操作，而不管这些错误是否存在，并且可以确定任何双位错误条件。模块上的冗余联系人可防止出现单点故障。

2. 发明授权

US08489936B2 High reliability memory module with a fault tolerant address and command bus 有权
标题翻译：高可靠性存储器模块，具有容错地址和命令总线
公开(公告)号：US08489936B2
公开(公告)日：2013-07-16
申请号：US11741319
申请日：2007-04-27
申请人： Kevin C. Gower , Bruce Hazelzet , Mark W. Kellogg , David J. Perlman
发明人： Kevin C. Gower , Bruce Hazelzet , Mark W. Kellogg , David J. Perlman
IPC分类号： G06F11/10
CPC分类号： H05K1/117 , G06F11/1044 , G11C5/04 , G11C2029/0409 , H05K2201/09145 , H05K2203/167
摘要： A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32K bit serial EE PROM and a 28 bit and a 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/ Parity register. By providing the module with a fault tolerant address and command bus fault-tolerance and self-healing aspects necessary for autonomic computing systems compatible with industry-standards is realized. The memory module corrects single bit errors on the command or address bus and permits continuous memory operation independent of the existence of these errors and can determine any double bit error condition. The redundant contacts on the module prevents what would otherwise be single points of failure.
摘要翻译：具有容错地址和命令总线的高可靠性双列直插式存储器模块，用于服务器。存储器模块是大约151.35mm或5.97英寸长的卡，其具有大约多个触点，其中一些是冗余的，多个DRAM，锁相环，2或32K位串行EE PROM和28位和具有纠错码（ECC），奇偶校验，用于经由独立总线读取的多字节故障报告电路的1至2寄存器和用于确定和报告耦合到服务器存储器的可纠正错误和不可校正错误状况的实时错误行接口芯片和存储器控制器或处理器，使得存储器控制器通过地址/命令行将地址和命令信息与用于纠错目的的校验位一起发送到ECC /奇偶校验寄存器。通过为模块提供与行业标准兼容的自主计算系统所需的容错地址和命令总线容错和自修复方面。存储器模块纠正命令或地址总线上的单位错误，并允许连续存储器操作，而不管这些错误是否存在，并且可以确定任何双位错误条件。模块上的冗余联系人可防止出现单点故障。

3. 发明授权

US07761771B2 High reliability memory module with a fault tolerant address and command bus 有权
标题翻译：高可靠性存储器模块，具有容错地址和命令总线
公开(公告)号：US07761771B2
公开(公告)日：2010-07-20
申请号：US11406718
申请日：2006-04-20
申请人： Kevin C. Gower , Bruce Hazelzet , Mark W. Kellogg , David J. Perlman
发明人： Kevin C. Gower , Bruce Hazelzet , Mark W. Kellogg , David J. Perlman
IPC分类号： G11C29/00
CPC分类号： H05K1/117 , G06F11/1044 , G11C5/04 , G11C2029/0409 , H05K2201/09145 , H05K2203/167
摘要： A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32 K bit serial EE PROM and a 28 bit and a 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/Parity register. By providing the module with a fault tolerant address and command bus fault-tolerance and self-healing aspects necessary for autonomic computing systems compatible with industry-standards is realized. The memory module corrects single bit errors on the command or address bus and permits continuous memory operation independent of the existence of these errors and can determine any double bit error condition. The redundant contacts on the module prevents what would otherwise be single points of failure.
摘要翻译：具有容错地址和命令总线的高可靠性双列直插式存储器模块，用于服务器。存储器模块是大约151.35mm或5.97英寸长的卡，其具有大约多个触点，其中一些是冗余的，多个DRAM，锁相环，2或32K位串行EE PROM和28位具有纠错码（ECC）的1至2寄存器，奇偶校验，用于经由独立总线读取的多字节故障报告电路以及用于确定和报告可纠正错误的实时错误线以及耦合到服务器存储器接口芯片和存储器控制器或处理器，使得存储器控制器通过地址/命令行与地址/命令行一起发送地址和命令信息以及用于纠错目的的校验位给ECC /奇偶校验寄存器。通过为模块提供与行业标准兼容的自主计算系统所需的容错地址和命令总线容错和自修复方面。存储器模块纠正命令或地址总线上的单位错误，并允许连续存储器操作，而不管这些错误是否存在，并且可以确定任何双位错误条件。模块上的冗余联系人可防止出现单点故障。

4. 发明授权

US07366947B2 High reliability memory module with a fault tolerant address and command bus 有权
公开(公告)号：US07366947B2
公开(公告)日：2008-04-29
申请号：US11406719
申请日：2006-04-20
申请人： Kevin C. Gower , Bruce Hazelzet , Mark W. Kellogg , David J. Perhnan
发明人： Kevin C. Gower , Bruce Hazelzet , Mark W. Kellogg , David J. Perhnan
IPC分类号： G06F11/30
CPC分类号： H05K1/117 , G06F11/1044 , G11C5/04 , G11C2029/0409 , H05K2201/09145 , H05K2203/167
摘要： A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32K bit serial EE PROM and a 28 bit and a 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/Parity register. By providing the module with a fault tolerant address and command bus fault-tolerance and self-healing aspects necessary for autonomic computing systems compatible with industry-standards is realized. The memory module corrects single bit errors on the command or address bus and permits continuous memory operation independent of the existence of these errors and can determine any double bit error condition. The redundant contacts on the module prevents what would otherwise be single points of failure.

5. 发明授权

US07363533B2 High reliability memory module with a fault tolerant address and command bus 有权
标题翻译：高可靠性存储器模块，具有容错地址和命令总线
公开(公告)号：US07363533B2
公开(公告)日：2008-04-22
申请号：US11406717
申请日：2006-04-20
申请人： Kevin C. Gower , Bruce Hazelzet , Mark W. Kellogg , David J. Perlman
发明人： Kevin C. Gower , Bruce Hazelzet , Mark W. Kellogg , David J. Perlman
IPC分类号： G06F11/10
CPC分类号： H05K1/117 , G06F11/1044 , G11C5/04 , G11C2029/0409 , H05K2201/09145 , H05K2203/167
摘要： A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card provided with a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32K bit serial EE PROM, and a 28 bit 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/Parity register.
摘要翻译：具有容错地址和命令总线的高可靠性双列直插式存储器模块，用于服务器。存储器模块是设置有多个触点的卡，其中一些是多余的触点，多个DRAM，多个DRAM，锁相环，2或32K位串行EE PROM以及具有纠错码的28位1到2寄存器 ECC），奇偶校验，用于通过独立总线读取的多字节故障报告电路和用于确定和报告耦合到服务器的存储器接口芯片和存储器控制器或处理器的可纠正错误和不可校正错误状况的实时错误行，使得存储器控制器通过地址/命令行将地址和命令信息与校验位一起发送到ECC /奇偶校验寄存器。

6. 发明授权

US07234099B2 High reliability memory module with a fault tolerant address and command bus 有权
标题翻译：高可靠性存储器模块，具有容错地址和命令总线
公开(公告)号：US07234099B2
公开(公告)日：2007-06-19
申请号：US10413605
申请日：2003-04-14
申请人： Kevin C. Gower , Bruce Hazelzet , Mark W. Kellogg , David J. Perlman
发明人： Kevin C. Gower , Bruce Hazelzet , Mark W. Kellogg , David J. Perlman
IPC分类号： H05K1/11
CPC分类号： H05K1/117 , G06F11/1044 , G11C5/04 , G11C2029/0409 , H05K2201/09145 , H05K2203/167
摘要： A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32K bit serial EE PROM and a 28 bit, a 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/Parity register. By providing the module with a fault tolerant address and command bus fault-tolerance and self-healing aspects necessary for autonomic computing systems compatible with industry-standards is realized. The memory module corrects single bit errors on the command or address bus and permits continuous memory operation independent of the existence of these errors and can determine any double bit error condition. The redundant contacts on the module prevents what would otherwise be single points of failure.
摘要翻译：具有容错地址和命令总线的高可靠性双列直插式存储器模块，用于服务器。存储器模块是大约151.35mm或5.97英寸长的卡，其具有大约多个触点，其中一些是冗余的，多个DRAM，锁相环，2或32K位串行EE PROM和28位，具有纠错码（ECC），奇偶校验，用于经由独立总线读取的多字节故障报告电路的1至2寄存器和用于确定和报告耦合到服务器存储器的可纠正错误和不可校正错误状况的实时错误行接口芯片和存储器控制器或处理器，使得存储器控制器通过地址/命令行将地址和命令信息与用于纠错目的的校验位一起发送到ECC /奇偶校验寄存器。通过为模块提供与行业标准兼容的自主计算系统所需的容错地址和命令总线容错和自修复方面。存储器模块纠正命令或地址总线上的单位错误，并允许连续存储器操作，而不管这些错误是否存在，并且可以确定任何双位错误条件。模块上的冗余联系人可防止出现单点故障。

7. 发明授权

US08296541B2 Memory subsystem with positional read data latency 失效
标题翻译：具有位置读数据延迟的内存子系统
公开(公告)号：US08296541B2
公开(公告)日：2012-10-23
申请号：US12369037
申请日：2009-02-11
申请人： Kevin C. Gower , Kevin W. Kark , Mark W. Kellogg , Warren E. Maule
发明人： Kevin C. Gower , Kevin W. Kark , Mark W. Kellogg , Warren E. Maule
IPC分类号： G06F12/00 , G06F13/28
CPC分类号： G06F13/1673 , G06F13/1689
摘要： A memory subsystem with positional read data latency that includes one or more memory modules, a memory controller and one or more memory busses is provided. The memory controller includes instructions for providing positional read data latency. The memory modules and the memory controller are interconnected via the memory busses.
摘要翻译：提供具有包括一个或多个存储器模块，存储器控制器和一个或多个存储器总线的位置读取数据延迟的存储器子系统。存储器控制器包括用于提供位置读取数据等待时间的指令。存储器模块和存储器控制器通过存储器总线相互连接。

8. 发明授权

US07539800B2 System, method and storage medium for providing segment level sparing 有权
标题翻译：系统，方法和存储介质，用于提供段级备份
公开(公告)号：US07539800B2
公开(公告)日：2009-05-26
申请号：US10903188
申请日：2004-07-30
申请人： Timothy J. Dell , Frank D. Ferraiolo , Kevin C. Gower , Kevin W. Kark , Mark W. Kellogg , Warren E. Maule
发明人： Timothy J. Dell , Frank D. Ferraiolo , Kevin C. Gower , Kevin W. Kark , Mark W. Kellogg , Warren E. Maule
IPC分类号： G06F13/00 , G06F11/00
CPC分类号： G06F11/201 , G06F11/104
摘要： A memory subsystem that includes segment level sparing. The memory subsystem includes a cascaded interconnect system with segment level sparing. The cascaded interconnect system includes two or more memory assemblies and a memory bus. The memory bus includes multiple segments and the memory assemblies are interconnected via the memory bus.
摘要翻译：一个内存子系统，包括段级备份。存储器子系统包括具有段级保护的级联互连系统。级联互连系统包括两个或多个存储器组件和存储器总线。存储器总线包括多个段，并且存储器组件经由存储器总线互连。

9. 发明授权

US07512762B2 System, method and storage medium for a memory subsystem with positional read data latency 失效
标题翻译：具有位置读数据延迟的存储器子系统的系统，方法和存储介质
公开(公告)号：US07512762B2
公开(公告)日：2009-03-31
申请号：US10977038
申请日：2004-10-29
申请人： Kevin C. Gower , Kevin W. Kark , Mark W. Kellogg , Warren E. Maule
发明人： Kevin C. Gower , Kevin W. Kark , Mark W. Kellogg , Warren E. Maule
IPC分类号： G06F13/00 , G06F12/00
CPC分类号： G06F13/1673 , G06F13/1689
摘要： A memory subsystem with positional read data latency that includes a cascaded interconnect system with one or more memory modules, a memory controller and one or more memory busses. The memory controller includes instructions for providing positional read data latency. The memory modules and the memory controller are interconnected by a packetized multi-transfer interface via the memory busses.
摘要翻译：具有位置读数据延迟的存储器子系统，其包括具有一个或多个存储器模块的级联互连系统，存储器控制器和一个或多个存储器总线。存储器控制器包括用于提供位置读取数据等待时间的指令。存储器模块和存储器控制器通过分组化的多传输接口经由存储器总线互连。

10. 发明申请

US20080183957A1 276-PIN BUFFERED MEMORY MODULE WITH ENHANCED FAULT TOLERANCE 失效
标题翻译： 276引脚缓冲存储器模块，具有增强的故障容限
公开(公告)号：US20080183957A1
公开(公告)日：2008-07-31
申请号：US12060992
申请日：2008-04-02
申请人： Daniel M. Dreps , Frank D. Ferraiolo , Kevin C. Gower , Mark W. Kellogg , Roger A. Rippens
发明人： Daniel M. Dreps , Frank D. Ferraiolo , Kevin C. Gower , Mark W. Kellogg , Roger A. Rippens
IPC分类号： G06F12/00 , G06F11/00
CPC分类号： G11C5/04
摘要： A dual inline memory module (DIMM) includes a card having a length of about 151.2 to about 151.5 millimeters, a plurality of individual local memory devices attached to the card, and a buffer device attached to the card, the buffer device configured for converting a packetized memory interface. The card includes at least 276 pins configured thereon.
摘要翻译：双列直插式存储器模块（DIMM）包括具有大约151.2至大约151.5毫米的长度的卡，连接到卡的多个单独的本地存储器件以及连接到卡的缓冲器装置，缓冲器装置被配置为将打包内存界面。该卡片包括至少276个配置在其上的针脚。

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