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1. 发明申请

US20050154802A1 Parallel pattern detection engine 有权
标题翻译：并行模式检测引擎
公开(公告)号：US20050154802A1
公开(公告)日：2005-07-14
申请号：US10757187
申请日：2004-01-14
申请人： Kerry Kravec , Ali Saidi , Jan Slyfield , Pascal Tannhof
发明人： Kerry Kravec , Ali Saidi , Jan Slyfield , Pascal Tannhof
IPC分类号： G06F3/00 , G06K9/00 , G06K9/64
CPC分类号： G06K9/6202 , G06K9/00986
摘要： A parallel pattern detection engine (PPDE) comprise multiple processing units (PUs) customized to do various modes of pattern recognition. The PUs are loaded with different patterns and the input data to be matched is provided to the PUs in parallel. Each pattern has an Opcode that defines what action to take when a particular data in the input data stream either matches or does not match the corresponding data being compared during a clock cycle. Each of the PUs communicate selected information so that PUs may be cascaded to enable longer patterns to be matched or to allow more patterns to be processed in parallel for a particular input data stream.
摘要翻译：并行模式检测引擎（PPDE）包括定制的多个处理单元（PU），以执行各种模式识别模式。 PU装载有不同的图案，并且要匹配的输入数据并行提供给PU。每个模式都有一个操作码，定义当输入数据流中的特定数据与时钟周期中正在比较的对应数据匹配或不匹配时要执行的操作。每个PU通信所选择的信息，使得PU可以被级联以使得能够匹配更长的模式或允许针对特定的输入数据流并行地处理更多的模式。

2. 发明申请

US20070150621A1 Parallel Pattern Detection Engine 有权
公开(公告)号：US20070150621A1
公开(公告)日：2007-06-28
申请号：US11682547
申请日：2007-03-06
申请人： Kerry Kravec , Ali Saidi , Jan Slyfield , Pascal Tannhof
发明人： Kerry Kravec , Ali Saidi , Jan Slyfield , Pascal Tannhof
IPC分类号： G06F3/00
CPC分类号： G06K9/6202 , G06K9/00986
摘要： A parallel pattern detection engine (PPDE) comprise multiple processing units (PUs) customized to do various modes of pattern recognition. The PUs are loaded with different patterns and the input data to be matched is provided to the PUs in parallel. Each pattern has an Opcode that defines what action to take when a particular data in the input data stream either matches or does not match the corresponding data being compared during a clock cycle. Each of the PUs communicate selected information so that PUs may be cascaded to enable longer patterns to be matched or to allow more patterns to be processed in parallel for a particular input data stream.

3. 发明申请

US20050154916A1 Intrusion detection using a network processor and a parallel pattern detection engine 有权
标题翻译：使用网络处理器和并行模式检测引擎的入侵检测
公开(公告)号：US20050154916A1
公开(公告)日：2005-07-14
申请号：US10756904
申请日：2004-01-14
申请人： Marc Boulanger , Clark Jeffries , C. Kinard , Kerry Kravec , Ravinder Sabhikhi , Ali Saidi , Jan Slyfield , Pascal Tannhof
发明人： Marc Boulanger , Clark Jeffries , C. Kinard , Kerry Kravec , Ravinder Sabhikhi , Ali Saidi , Jan Slyfield , Pascal Tannhof
IPC分类号： H04L9/00 , H04L12/24 , H04L29/06
CPC分类号： H04L63/1416 , H04L63/1441
摘要： An intrusion detection system (IDS) comprises a network processor (NP) coupled to a memory unit for storing programs and data. The NP is also coupled to one or more parallel pattern detection engines (PPDE) which provide high speed parallel detection of patterns in an input data stream. Each PPDE comprises many processing units (PUs) each designed to store intrusion signatures as a sequence of data with selected operation codes. The PUs have configuration registers for selecting modes of pattern recognition. Each PU compares a byte at each clock cycle. If a sequence of bytes from the input pattern match a stored pattern, the identification of the PU detecting the pattern is outputted with any applicable comparison data. By storing intrusion signatures in many parallel PUs, the IDS can process network data at the NP processing speed. PUs may be cascaded to increase intrusion coverage or to detect long intrusion signatures.
摘要翻译：入侵检测系统（IDS）包括耦合到用于存储程序和数据的存储器单元的网络处理器（NP）。 NP还耦合到一个或多个并行模式检测引擎（PPDE），其提供对输入数据流中的模式的高速并行检测。每个PPDE包括许多处理单元（PU），每个处理单元被设计为将入侵签名存储为具有所选操作码的数据序列。 PU具有用于选择模式识别模式的配置寄存器。每个PU在每个时钟周期比较一个字节。如果来自输入模式的字节序列与存储的模式匹配，则用任何适用的比较数据输出检测模式的PU的识别。通过在多个并行PU中存储入侵签名，IDS可以以NP处理速度处理网络数据。 PU可以级联以增加入侵覆盖或检测长入侵签名。

4. 发明申请

US20070150622A1 Parallel Pattern Detection Engine 有权
标题翻译：并行模式检测引擎
公开(公告)号：US20070150622A1
公开(公告)日：2007-06-28
申请号：US11682576
申请日：2007-03-06
申请人： Kerry Kravec , Ali Saidi , Jan Slyfield , Pascal Tannhof
发明人： Kerry Kravec , Ali Saidi , Jan Slyfield , Pascal Tannhof
IPC分类号： G06F3/00
CPC分类号： G06K9/6202 , G06K9/00986
摘要： A parallel pattern detection engine (PPDE) comprise multiple processing units (PUs) customized to do various modes of pattern recognition. The PUs are loaded with different patterns and the input data to be matched is provided to the PUs in parallel. Each pattern has an Opcode that defines what action to take when a particular data in the input data stream either matches or does not match the corresponding data being compared during a clock cycle. Each of the PUs communicate selected information so that PUs may be cascaded to enable longer patterns to be matched or to allow more patterns to be processed in parallel for a particular input data stream.
摘要翻译：并行模式检测引擎（PPDE）包括定制的多个处理单元（PU），以执行各种模式识别模式。 PU装载有不同的图案，并且要匹配的输入数据并行提供给PU。每个模式都有一个操作码，定义当输入数据流中的特定数据与时钟周期中正在比较的对应数据匹配或不匹配时要执行的操作。每个PU通信所选择的信息，使得PU可以被级联以使得能够匹配更长的模式或允许针对特定的输入数据流并行地处理更多的模式。

5. 发明申请

US20050154858A1 Configurable bi-directional bus for communicating between autonomous units 失效
标题翻译：可配置双向总线，用于在自主单元之间进行通信
公开(公告)号：US20050154858A1
公开(公告)日：2005-07-14
申请号：US10757673
申请日：2004-01-14
申请人： Kerry Kravec , Ali Saidi , Jan Slyfield , Pascal Tannhof
发明人： Kerry Kravec , Ali Saidi , Jan Slyfield , Pascal Tannhof
IPC分类号： G06F13/40 , G06F15/00
CPC分类号： G06F13/4027
摘要： Processing units (PUs) are coupled with a gated bi-directional bus structure that allows the PUs to be cascaded. Each PUn has communication logic and function logic. Each PUn is physically coupled to two other PUs, a PUp and a PUf. The communication logic receives Link Out data from a PUp and sends Link In data to a PUf. The communication logic has register bits for enabling and disabling the data transmission. The communication logic couples the Link Out data from a PUp to the function logic and couples Link In data to the PUp from the function logic in response to the register bits. The function logic receives output data from the PUn and Link In data from the communication logic and forms Link Out data which is coupled to the PUf. The function logic couples Link In data from the PUf to the PUn and to the communication logic.
摘要翻译：处理单元（PU）与门控双向总线结构耦合，允许将PU级联。每个PUn具有通信逻辑和功能逻辑。每个PUn物理耦合到另外两个PU，PUp和PUf。通信逻辑从PUp接收Link Out数据，并将Link In数据发送到PUf。通信逻辑具有用于启用和禁用数据传输的寄存器位。通信逻辑将链路输出数据从PUp耦合到功能逻辑，并且响应于寄存器位将Link In数据从功能逻辑耦合到PUp。功能逻辑从通信逻辑的PUn和Link In数据接收输出数据，并形成耦合到PUf的Link Out数据。功能逻辑将来自PUf的链接数据耦合到PUn和通信逻辑。

6. 发明申请

US20050138324A1 PROCESSING UNIT HAVING A DUAL CHANNEL BUS ARCHITECTURE 审中-公开
标题翻译：具有双通道总线架构的处理单元
公开(公告)号：US20050138324A1
公开(公告)日：2005-06-23
申请号：US10905100
申请日：2004-12-15
申请人： Pascal Tannhof , Jan Slyfield
发明人： Pascal Tannhof , Jan Slyfield
IPC分类号： G06F15/00 , G06F15/173
CPC分类号： G06F15/17368
摘要： A processing unit having a dual channel bus architecture associated with a specific instruction set, configured to receive an input message and transmit an output message that is identical or derived therefrom. A message consists of one opcode, with or without associated data, used to control each processing unit depending on logic conditions stored in dedicated registers in each unit. Processing units are serially connected but can work simultaneously for a total pipelined operation. This dual architecture is organized around two channels labeled Channel 1 and Channel 2. Channel 1 mainly transmits an input message to all units while Channel 2 mainly transmits the results after processing in a unit as an output message. Depending on the logic conditions, an input message not processed in a processing unit may be transmitted to the next one without any change.
摘要翻译：一种具有与特定指令集相关联的双通道总线架构的处理单元，其被配置为接收输入消息并发送相同或从其导出的输出消息。消息由一个操作码组成，具有或不具有关联数据，用于根据存储在每个单元中的专用寄存器中的逻辑条件来控制每个处理单元。处理单元串联连接，但可以同时工作进行总体流水线操作。该双重架构围绕标记为通道1和通道2的两个通道组合。通道1主要向所有单元发送输入消息，而通道2主要在以单元处理之后将结果作为输出消息发送。根据逻辑条件，在处理单元中未处理的输入消息可以被发送到下一个，而没有任何改变。

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