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    • 1. 发明申请
    • OPTICAL POINTING APPARATUS AND PORTABLE ELECTRONIC APPARATUS WITH THE SAME
    • 光学指示装置和便携式电子设备
    • US20110018800A1
    • 2011-01-27
    • US12933707
    • 2009-03-03
    • Keon Joon AhnJae Dong KimSang Il Park
    • Keon Joon AhnJae Dong KimSang Il Park
    • G06F3/033
    • G06F3/042G06F1/1616G06F1/1626G06F1/169
    • An optical pointing device and a portable electronic device having the same, in which external noise light and/or noise light due to diffused reflection or the like is prevented from being introduced into an optical sensor enhancing precision of operation and providing a housing with improved structure. The device includes an infrared source; a cover having a cover plate transmitting infrared rays from the IR source for reaching a subject out of the cover plate and a cover frame that supports the cover plate; an optical unit in the cover and on which the infrared ray reflected from the subject is incident; and an optical sensor sensing the infrared ray incident thereon from the optical unit; the cover plate has a base coupled to the cover frame, and an IR band-pass filter layer provided on one side of the base.
    • 具有这样的光学指示装置和便携式电子装置,其中防止由于扩散反射等引起的外部噪声光和/或噪声光被引入到提高操作精度的光学传感器中并提供具有改进结构的壳体 。 该装置包括红外源; 具有盖板,其将来自所述IR源的红外线传送到所述盖板外的被检体,盖框支撑所述盖板; 盖子上的光学单元,从被摄体反射的红外线入射到该光学单元上; 以及感测从光学单元入射到其上的红外线的光学传感器; 盖板具有联接到盖框架的基座和设置在基座的一侧上的IR带通滤波器层。
    • 7. 发明授权
    • Memory device for reducing leakage current
    • 用于减少漏电流的存储器件
    • US07193926B2
    • 2007-03-20
    • US11158492
    • 2005-06-22
    • Sang Il ParkSang Kwon Lee
    • Sang Il ParkSang Kwon Lee
    • G11C8/00
    • G11C29/83
    • Disclosed is a memory device for reducing leakage current generated by a bridge between a word line and a bit line when the memory device is in a waiting mode. The memory device includes: N memory cell blocks each of which includes plurality of memory cell blocks, wherein N represents a natural number; (N+1) sense amp blocks corresponding to the N memory cell blocks; 2N switching blocks connecting the N memory cell blocks to the (N+1) sense amp blocks, respectively; and N controllers for controlling the 2N switching blocks, respectively, wherein the N controllers turn off the 2N switching blocks when the memory device is in a waiting mode, and the N controllers selectively turn on the 2N switching blocks when the memory device is in an operation mode.
    • 公开了一种用于在存储器件处于等待模式时减少由字线和位线之间的桥产生的泄漏电流的存储器件。 存储器件包括:N个存储单元块,每个存储单元块包括多个存储单元块,其中N代表自然数; (N + 1)个对应于所述N个存储单元块的读出放大器块; 2N个切换块,分别将N个存储单元块连接到(N + 1)个读出放大器块; 和N个控制器,用于分别控制2N个切换块,其中N个控制器在存储器件处于等待模式时关闭2N个切换块,并且当存储器件处于等待模式时,N个控制器选择性地接通2N个切换块 操作模式。
    • 8. 发明授权
    • Method of manufacturing CMOS thin film transistor
    • 制造CMOS薄膜晶体管的方法
    • US06753235B2
    • 2004-06-22
    • US10086629
    • 2002-03-04
    • Woo Young SoKyung Jin YooSang Il Park
    • Woo Young SoKyung Jin YooSang Il Park
    • H01L21331
    • H01L27/1288H01L27/1214
    • A method of manufacturing a CMOS TFT including forming first and second semiconductor layers on an insulating substrate using a first mask, respectively, the substrate having first and second regions, the first semiconductor layer formed on the first region, the second semiconductor layer formed on the second region; forming sequentially a first insulating layer, a first metal layer and a second insulating layer over the whole surface of the substrate; etching a portion of the first metal layer and a portion of the second insulating layer over the first region of the substrate using a second mask to form a first gate electrode and a first capping layer; forming first spacers on both side wall portion of the first gate electrode and the first capping layer; ion-implanting a first conductive-type high-density impurity into the first semiconductor layer using the first spacers and the first gate electrode as a mask to form first high-density source and drain regions; etching a portion of the first metal layer and a portion of the second insulating layer over the second region of the substrate using a third mask to form a second gate electrode and a second capping layer; and ion-implanting a second conductive-type high density impurity into the second semiconductor layer using the third mask to form second high-density source and drain regions.
    • 一种制造CMOS TFT的方法,包括分别使用第一掩模在绝缘基板上形成第一和第二半导体层,所述基板具有第一和第二区域,所述第一半导体层形成在第一区域上,第二半导体层形成在 第二区 在基板的整个表面上依次形成第一绝缘层,第一金属层和第二绝缘层; 使用第二掩模在所述衬底的所述第一区域上蚀刻所述第一金属层的一部分和所述第二绝缘层的一部分,以形成第一栅电极和第一覆盖层; 在所述第一栅电极和所述第一覆盖层的两侧壁部分上形成第一间隔物; 使用第一间隔物和第一栅电极作为掩模,将第一导电型高密度杂质离子注入第一半导体层,以形成第一高密度源极和漏极区; 使用第三掩模在所述基板的所述第二区域上蚀刻所述第一金属层的一部分和所述第二绝缘层的一部分,以形成第二栅电极和第二封盖层; 以及使用所述第三掩模将第二导电型高密度杂质离子注入到所述第二半导体层中以形成第二高密度源极和漏极区。
    • 10. 发明授权
    • Semiconductor memory apparatus
    • 半导体存储装置
    • US08391100B2
    • 2013-03-05
    • US12845568
    • 2010-07-28
    • Sun Mo AnSang Il Park
    • Sun Mo AnSang Il Park
    • G11C8/04
    • G11C11/40611G11C2211/4068
    • A semiconductor memory apparatus includes a counting control circuit and an address counting circuit. The counting control circuit is configured to generate a first counting start signal, a second counting start signal and a counting count signal in response to an auto-refresh signal, a voltage stabilization signal and a fuse control signal. The address counting circuit is configured to count a plurality of count addresses in response to the first counting start signal, and to count one or more specified count addresses from among the plurality of count addresses in response to the second counting start signal and the counting control signal.
    • 半导体存储装置包括计数控制电路和地址计数电路。 计数控制电路被配置为响应于自动刷新信号,电压稳定信号和熔丝控制信号产生第一计数开始信号,第二计数开始信号和计数计数信号。 地址计数电路被配置为响应于第一计数开始信号对多个计数地址进行计数,并且响应于第二计数开始信号和计数控制对多个计数地址中的一个或多个指定的计数地址进行计数 信号。