专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08607024B2 Virtual address cache memory, processor and multiprocessor 有权
公开(公告)号：US08607024B2
公开(公告)日：2013-12-10
申请号：US12958298
申请日：2010-12-01
申请人： Kenta Yasufuku , Shigeaki Iwasa , Yasuhiko Kurosawa , Hiroo Hayashi , Seiji Maeda , Mitsuo Saito
发明人： Kenta Yasufuku , Shigeaki Iwasa , Yasuhiko Kurosawa , Hiroo Hayashi , Seiji Maeda , Mitsuo Saito
IPC分类号： G06F13/14
CPC分类号： G06F12/1063 , G06F12/0831 , G06F12/1027 , G06F12/1054 , G06F12/1081 , G06F12/12 , Y02D10/13
摘要： An embodiment provides a virtual address cache memory including: a TLB virtual page memory configured to, when a rewrite to a TLB occurs, rewrite entry data; a data memory configured to hold cache data using a virtual page tag or a page offset as a cache index; a cache state memory configured to hold a cache state for the cache data stored in the data memory, in association with the cache index; a first physical address memory configured to, when the rewrite to the TLB occurs, rewrite a held physical address; and a second physical address memory configured to, when the cache data is written to the data memory after the occurrence of the rewrite to the TLB, rewrite a held physical address.

2. 发明授权

US08949572B2 Effective address cache memory, processor and effective address caching method 有权
标题翻译：有效的地址缓存内存，处理器和有效的地址缓存方法
公开(公告)号：US08949572B2
公开(公告)日：2015-02-03
申请号：US12580732
申请日：2009-10-16
申请人： Yasuhiko Kurosawa , Shigeaki Iwasa , Seiji Maeda , Nobuhiro Yoshida , Mitsuo Saito , Hiroo Hayashi
发明人： Yasuhiko Kurosawa , Shigeaki Iwasa , Seiji Maeda , Nobuhiro Yoshida , Mitsuo Saito , Hiroo Hayashi
IPC分类号： G06F12/10
CPC分类号： G06F12/1054 , G06F12/0831
摘要： An effective address cache memory includes a TLB effective page memory configured to retain entry data including an effective page tag of predetermined high-order bits of an effective address of a process, and output a hit signal when the effective page tag matches the effective page tag from a processor; a data memory configured to retain cache data with the effective page tag or a page offset as a cache index; and a cache state memory configured to retain a cache state of the cache data stored in the data memory, in a manner corresponding to the cache index.
摘要翻译：有效地址高速缓冲存储器包括：TLB有效页存储器，被配置为保留包括处理的有效地址的预定高位的有效页标签的条目数据，并且当有效页标签与有效页标签匹配时输出命中信号从处理器数据存储器，被配置为将高效数据与有效页面标签或页面偏移量保持为高速缓存索引; 以及高速缓存状态存储器，被配置为以与高速缓存索引对应的方式保存存储在数据存储器中的高速缓存数据的高速缓存状态。

3. 发明申请

US20100100685A1 EFFECTIVE ADDRESS CACHE MEMORY, PROCESSOR AND EFFECTIVE ADDRESS CACHING METHOD 有权
标题翻译：有效的地址缓存存储器，处理器和有效的地址缓存方法
公开(公告)号：US20100100685A1
公开(公告)日：2010-04-22
申请号：US12580732
申请日：2009-10-16
申请人： Yasuhiko Kurosawa , Shigeaki Iwasa , Seiji Maeda , Nobuhiro Yoshida , Mitsuo Saito , Hiroo Hayashi
发明人： Yasuhiko Kurosawa , Shigeaki Iwasa , Seiji Maeda , Nobuhiro Yoshida , Mitsuo Saito , Hiroo Hayashi
IPC分类号： G06F12/08 , G06F12/00 , G06F12/10
CPC分类号： G06F12/1054 , G06F12/0831
摘要： An effective address cache memory includes a TLB effective page memory configured to retain entry data including an effective page tag of predetermined high-order bits of an effective address of a process, and output a hit signal when the effective page tag matches the effective page tag from a processor; a data memory configured to retain cache data with the effective page tag or a page offset as a cache index; and a cache state memory configured to retain a cache state of the cache data stored in the data memory, in a manner corresponding to the cache index.
摘要翻译：有效地址高速缓冲存储器包括：TLB有效页存储器，被配置为保留包括处理的有效地址的预定高位的有效页标签的条目数据，并且当有效页标签与有效页标签匹配时输出命中信号从处理器数据存储器，被配置为将高效数据与有效页面标签或页面偏移量保持为高速缓存索引; 以及高速缓存状态存储器，被配置为以与高速缓存索引对应的方式保存存储在数据存储器中的高速缓存数据的高速缓存状态。

4. 发明授权

US08145804B2 Systems and methods for transferring data to maintain preferred slot positions in a bi-endian processor 有权
标题翻译：用于传送数据以维持双端处理器中优选插槽位置的系统和方法
公开(公告)号：US08145804B2
公开(公告)日：2012-03-27
申请号：US12563756
申请日：2009-09-21
申请人： Brian King Flachs , Brad William Michael , Nicolas Maeding , Shigeaki Iwasa , Seiji Maeda , Hiroo Hayashi
发明人： Brian King Flachs , Brad William Michael , Nicolas Maeding , Shigeaki Iwasa , Seiji Maeda , Hiroo Hayashi
IPC分类号： G06F13/28
CPC分类号： G06F9/30007 , G06F9/3824
摘要： A bi-endian multiprocessor system having multiple processing elements, each of which includes a processor core, a local memory and a memory flow controller. The memory flow controller transfers data between the local memory and data sources external to the processing element. If the processing element and the data source implement data representations having the same endian-ness, each multi-word line of data is stored in the local memory in the same word order as in the data source. If the processing element and the data source implement data representations having different endian-ness, the words of each multi-word line of data are transposed when data is transferred between local memory and the data source. The processing element may incorporate circuitry to add doublewords, wherein the circuitry can alternately carry bits from a first word to a second word or vice versa, depending upon whether the words in lines of data are transposed.
摘要翻译：一种具有多个处理元件的双端式多处理器系统，每个处理单元包括处理器核心，本地存储器和存储器流控制器。存储器流控制器在本地存储器和处理元件外部的数据源之间传送数据。如果处理元件和数据源实现具有相同字节数的数据表示，则每个多字数据行以与数据源中相同的字顺序存储在本地存储器中。如果处理元件和数据源实现具有不同端点的数据表示，则当数据在本地存储器和数据源之间传送时，每个多字数据行的字被转置。处理元件可以包括用于添加双字的电路，其中，根据数据行中的字是否被转置，电路可以交替地将位从第一个字运送到第二个字，反之亦然。

5. 发明申请

US20110072170A1 Systems and Methods for Transferring Data to Maintain Preferred Slot Positions in a Bi-endian Processor 有权
标题翻译：用于传输数据以保持双端处理器中优选插槽位置的系统和方法
公开(公告)号：US20110072170A1
公开(公告)日：2011-03-24
申请号：US12563756
申请日：2009-09-21
申请人： Brian King Flachs , Brad William Michael , Nicolas Maeding , Shigeaki Iwasa , Seiji Maeda , Hiroo Hayashi
发明人： Brian King Flachs , Brad William Michael , Nicolas Maeding , Shigeaki Iwasa , Seiji Maeda , Hiroo Hayashi
IPC分类号： G06F13/28 , G06F12/00 , G06F12/08
CPC分类号： G06F9/30007 , G06F9/3824
摘要： A bi-endian multiprocessor system having multiple processing elements, each of which includes a processor core, a local memory and a memory flow controller. The memory flow controller transfers data between the local memory and data sources external to the processing element. If the processing element and the data source implement data representations having the same endian-ness, each multi-word line of data is stored in the local memory in the same word order as in the data source. If the processing element and the data source implement data representations having different endian-ness, the words of each multi-word line of data are transposed when data is transferred between local memory and the data source. The processing element may incorporate circuitry to add doublewords, wherein the circuitry can alternately carry bits from a first word to a second word or vice versa, depending upon whether the words in lines of data are transposed.
摘要翻译：一种具有多个处理元件的双端式多处理器系统，每个处理单元包括处理器核心，本地存储器和存储器流控制器。存储器流控制器在本地存储器和处理元件外部的数据源之间传送数据。如果处理元件和数据源实现具有相同字节数的数据表示，则每个多字数据行以与数据源中相同的字顺序存储在本地存储器中。如果处理元件和数据源实现具有不同端点的数据表示，则当数据在本地存储器和数据源之间传送时，每个多字数据行的字被转置。处理元件可以包括用于添加双字的电路，其中，根据数据行中的字是否被转置，电路可以交替地将位从第一个字运送到第二个字，反之亦然。

6. 发明申请

US20110055647A1 PROCESSOR 失效
标题翻译：处理器
公开(公告)号：US20110055647A1
公开(公告)日：2011-03-03
申请号：US12862081
申请日：2010-08-24
申请人： Seiji Maeda , Kenta Yasufuku
发明人： Seiji Maeda , Kenta Yasufuku
IPC分类号： G11C29/04 , G06F11/22
CPC分类号： G06F11/1048
摘要： A processor has an ALU, a load/store unit, a timer, an ECC calculator, and a plurality of ECC registers. When the load/store unit writes data in a main memory, the load/store unit writes written data and a count value of a timer in the main memory, and sets ECC status flag which indicates that an ECC about the written data is not correct in the main memory, and causes the ECC calculator to calculate the ECC about the written data after setting the ECC status flag, and writes the calculated ECC in the main memory and resets the ECC status flag after the ECC is calculated.
摘要翻译：处理器具有ALU，加载/存储单元，定时器，ECC计算器和多个ECC寄存器。当加载/存储单元将数据写入主存储器时，加载/存储单元将写入数据和定时器的计数值写入主存储器，并设置ECC状态标志，其指示关于写入数据的ECC不正确在主存储器中，并且使ECC计算器在设置ECC状态标志之后计算关于写入数据的ECC，并将计算的ECC写入主存储器中，并且在ECC计算之后复位ECC状态标志。

7. 发明申请

US20110099336A1 CACHE MEMORY CONTROL CIRCUIT AND CACHE MEMORY CONTROL METHOD 审中-公开
标题翻译：高速缓存存储器控制电路和高速缓存存储器控制方法
公开(公告)号：US20110099336A1
公开(公告)日：2011-04-28
申请号：US12882588
申请日：2010-09-15
申请人： Kenta YASUFUKU , Seiji Maeda
发明人： Kenta YASUFUKU , Seiji Maeda
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0864 , G06F2212/1028 , Y02D10/13
摘要： A cache memory control circuit has a plurality of counters, each of which is provided per set and per memory space and configured to count how many pieces of data of a corresponding memory space is stored in a corresponding set. The cache memory control circuit controls activation of a tag memory and a data memory of each of a plurality of sets according to a count value of each of the plurality of counters.
摘要翻译：高速缓冲存储器控制电路具有多个计数器，每个计数器按照每个存储空间和每个存储器空间提供，并且被配置为对相应存储器空间的数据数量存储在对应的集合中。高速缓冲存储器控制电路根据多个计数器中的每一个的计数值来控制多个集合中的每一个的标签存储器和数据存储器的激活。

8. 发明授权

US08484520B2 Processor capable of determining ECC errors 失效
标题翻译：能够确定ECC错误的处理器
公开(公告)号：US08484520B2
公开(公告)日：2013-07-09
申请号：US12862081
申请日：2010-08-24
申请人： Seiji Maeda , Kenta Yasufuku
发明人： Seiji Maeda , Kenta Yasufuku
IPC分类号： G11C29/00
CPC分类号： G06F11/1048
摘要： A processor has an ALU, a load/store unit, a timer, an ECC calculator, and a plurality of ECC registers. When the load/store unit writes data in a main memory, the load/store unit writes written data and a count value of a timer in the main memory, and sets ECC status flag which indicates that an ECC about the written data is not correct in the main memory, and causes the ECC calculator to calculate the ECC about the written data after setting the ECC status flag, and writes the calculated ECC in the main memory and resets the ECC status flag after the ECC is calculated.
摘要翻译：处理器具有ALU，加载/存储单元，定时器，ECC计算器和多个ECC寄存器。当加载/存储单元将数据写入主存储器时，加载/存储单元将写入数据和定时器的计数值写入主存储器，并设置ECC状态标志，其指示关于写入数据的ECC不正确在主存储器中，并且使ECC计算器在设置ECC状态标志之后计算关于写入数据的ECC，并将计算的ECC写入主存储器中，并且在ECC计算之后复位ECC状态标志。

9. 发明授权

US09267912B2 Apparatus for analyzing gas information 有权
标题翻译：气体信息分析装置
公开(公告)号：US09267912B2
公开(公告)日：2016-02-23
申请号：US13323015
申请日：2011-12-12
申请人： Seiji Maeda
发明人： Seiji Maeda
IPC分类号： G01M15/10 , G01N27/406
CPC分类号： G01N27/4067
摘要： A gas information estimation apparatus (100) is connected to a gas sensor element for detecting the concentration of gas flowing through an internal combustion engine (11), and estimates gas information other than the concentration. The apparatus includes gas sensor element provisional temperature calculation means (51) for calculating a provisional temperature of the gas sensor element using a predetermined simulation model, and inputting a reference value to the model as the parameter value; gas sensor element actual temperature measurement means (53), (54); gas information calculation means (55) for calculating the true value of the parameter value which can be input to the model in place of the reference value such that the provisional temperature of the gas sensor element approaches the actual temperature; and gas information obtaining means (57) for obtaining an estimative value of the gas information from the true value.
摘要翻译：气体信息估计装置（100）连接到用于检测流过内燃机（11）的气体浓度的气体传感器元件，并且估计浓度以外的气体信息。该装置包括用于使用预定模拟模型计算气体传感器元件的临时温度并将参考值作为参数值输入到模型的气体传感器元件临时温度计算装置（51）气体传感器元件实际温度测量装置（53），（54）; 气体信息计算装置（55），用于计算可以输入到模型的参数值的真实值代替参考值，使得气体传感器元件的临时温度接近实际温度; 以及用于从真实值获得气体信息的估计值的气体信息获取装置（57）。

10. 发明申请

US20120035606A1 Body Tissue Incision Apparatus 审中-公开
标题翻译：身体组织切开装置
公开(公告)号：US20120035606A1
公开(公告)日：2012-02-09
申请号：US13277502
申请日：2011-10-20
申请人： Akihito Kano , Hideyuki Kasahara , Seiji Maeda , Randal J. Kadykowski , Lyne M. Charron-Keller
发明人： Akihito Kano , Hideyuki Kasahara , Seiji Maeda , Randal J. Kadykowski , Lyne M. Charron-Keller
IPC分类号： A61B18/14 , A61B17/3205
CPC分类号： A61B10/0266 , A61B10/04 , A61B17/00008 , A61B18/1492 , A61B2018/00208 , A61B2018/00601 , A61B2018/1861
摘要： The body tissue harvesting instrument is provided with a cutter which is disposed at the distal end of an insertion member that is inserted into the body to sever tissue inside the body. The cutter includes a slit that extends from the distal end toward the base end; a first high-frequency electrode disposed along the two side edges of the slit on the outer surface of the cutter body and a second high-frequency electrode disposed at the base end of the slit; and a mechanism which is disposed on both sides of the distal end of the slit in the projection of the cutter body which rotates as a result of being pressed by the tissue, and which feeds the tissue toward the interior of the slit. Parts located on both sides of the distal end of the slit in the projection may mutually separate in the thickness direction.
摘要翻译：身体组织收集器设置有切割器，其设置在插入体内的插入部件的远端，以切断身体内的组织。切割器包括从远端朝向基端延伸的狭缝; 沿切割器外表面上的狭缝的两个侧边缘设置的第一高频电极和设置在狭缝的基端的第二高频电极; 以及机构，其设置在由于被组织按压而旋转的刀体的突出部中的狭缝的远端的两侧，并且将组织朝向狭缝的内部供给。位于突起中的狭缝的远端的两侧的部分可以在厚度方向上相互分离。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式