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1. 发明授权

US08607024B2 Virtual address cache memory, processor and multiprocessor 有权
公开(公告)号：US08607024B2
公开(公告)日：2013-12-10
申请号：US12958298
申请日：2010-12-01
申请人： Kenta Yasufuku , Shigeaki Iwasa , Yasuhiko Kurosawa , Hiroo Hayashi , Seiji Maeda , Mitsuo Saito
发明人： Kenta Yasufuku , Shigeaki Iwasa , Yasuhiko Kurosawa , Hiroo Hayashi , Seiji Maeda , Mitsuo Saito
IPC分类号： G06F13/14
CPC分类号： G06F12/1063 , G06F12/0831 , G06F12/1027 , G06F12/1054 , G06F12/1081 , G06F12/12 , Y02D10/13
摘要： An embodiment provides a virtual address cache memory including: a TLB virtual page memory configured to, when a rewrite to a TLB occurs, rewrite entry data; a data memory configured to hold cache data using a virtual page tag or a page offset as a cache index; a cache state memory configured to hold a cache state for the cache data stored in the data memory, in association with the cache index; a first physical address memory configured to, when the rewrite to the TLB occurs, rewrite a held physical address; and a second physical address memory configured to, when the cache data is written to the data memory after the occurrence of the rewrite to the TLB, rewrite a held physical address.

2. 发明申请

US20110055647A1 PROCESSOR 失效
标题翻译：处理器
公开(公告)号：US20110055647A1
公开(公告)日：2011-03-03
申请号：US12862081
申请日：2010-08-24
申请人： Seiji Maeda , Kenta Yasufuku
发明人： Seiji Maeda , Kenta Yasufuku
IPC分类号： G11C29/04 , G06F11/22
CPC分类号： G06F11/1048
摘要： A processor has an ALU, a load/store unit, a timer, an ECC calculator, and a plurality of ECC registers. When the load/store unit writes data in a main memory, the load/store unit writes written data and a count value of a timer in the main memory, and sets ECC status flag which indicates that an ECC about the written data is not correct in the main memory, and causes the ECC calculator to calculate the ECC about the written data after setting the ECC status flag, and writes the calculated ECC in the main memory and resets the ECC status flag after the ECC is calculated.
摘要翻译：处理器具有ALU，加载/存储单元，定时器，ECC计算器和多个ECC寄存器。当加载/存储单元将数据写入主存储器时，加载/存储单元将写入数据和定时器的计数值写入主存储器，并设置ECC状态标志，其指示关于写入数据的ECC不正确在主存储器中，并且使ECC计算器在设置ECC状态标志之后计算关于写入数据的ECC，并将计算的ECC写入主存储器中，并且在ECC计算之后复位ECC状态标志。

3. 发明授权

US08484520B2 Processor capable of determining ECC errors 失效
标题翻译：能够确定ECC错误的处理器
公开(公告)号：US08484520B2
公开(公告)日：2013-07-09
申请号：US12862081
申请日：2010-08-24
申请人： Seiji Maeda , Kenta Yasufuku
发明人： Seiji Maeda , Kenta Yasufuku
IPC分类号： G11C29/00
CPC分类号： G06F11/1048
摘要： A processor has an ALU, a load/store unit, a timer, an ECC calculator, and a plurality of ECC registers. When the load/store unit writes data in a main memory, the load/store unit writes written data and a count value of a timer in the main memory, and sets ECC status flag which indicates that an ECC about the written data is not correct in the main memory, and causes the ECC calculator to calculate the ECC about the written data after setting the ECC status flag, and writes the calculated ECC in the main memory and resets the ECC status flag after the ECC is calculated.
摘要翻译：处理器具有ALU，加载/存储单元，定时器，ECC计算器和多个ECC寄存器。当加载/存储单元将数据写入主存储器时，加载/存储单元将写入数据和定时器的计数值写入主存储器，并设置ECC状态标志，其指示关于写入数据的ECC不正确在主存储器中，并且使ECC计算器在设置ECC状态标志之后计算关于写入数据的ECC，并将计算的ECC写入主存储器中，并且在ECC计算之后复位ECC状态标志。

4. 发明申请

US20070233963A1 DATA PROCESSING SYSTEM AND METHOD FOR PROCESSING DATA 有权
标题翻译：数据处理系统和数据处理方法
公开(公告)号：US20070233963A1
公开(公告)日：2007-10-04
申请号：US11693231
申请日：2007-03-29
申请人： Kenta Yasufuku
发明人： Kenta Yasufuku
IPC分类号： G06F12/00
CPC分类号： G06F12/0864 , G06F12/0877 , G06F2212/1028 , Y02D10/13
摘要： A data processing system includes: a cache memory comprising a plurality of ways, each of which stores a data line including a data and address information of the data; an analysis module that analyzes whether or not a data requested in a read instruction is to be used in a subsequent instruction to be executed within a predetermined time period after the execution of the read instruction is started; a mode selection module that selects one of a plurality of access modes for accessing the cache memory based on a result of the analysis module; and an access unit that accesses the cache memory in the selected one of the access modes when the read instruction is executed.
摘要翻译：数据处理系统包括：高速缓存存储器，包括多个方式，每个路径存储包括数据的数据线和数据的地址信息; 分析模块，其在执行所述读取指令之后的预定时间段内分析在所述读取指令中请求的数据是否被使用在待执行的后续指令中; 模式选择模块，其基于所述分析模块的结果选择用于访问高速缓冲存储器的多个访问模式之一; 以及访问单元，当执行读取指令时，访问所选择的一个访问模式中的高速缓冲存储器。

5. 发明授权

US08131977B2 Microprocessor inhibiting instruction storage in cache and not decoding based on pre-analysis information to reduce power consumption 有权
标题翻译：微处理器禁止指令存储在缓存中，而不是基于预分解信息进行解码来降低功耗
公开(公告)号：US08131977B2
公开(公告)日：2012-03-06
申请号：US12200257
申请日：2008-08-28
申请人： Kenta Yasufuku
发明人： Kenta Yasufuku
IPC分类号： G06F9/30
CPC分类号： G06F12/0855 , G06F9/30145 , G06F9/3802 , G06F9/382 , G06F9/3822 , G06F9/3853 , Y02D10/13
摘要： A microprocessor includes: a processor core that performs pipeline processing; an instruction analyzing section that analyzes an instruction to be processed by the processor core and outputs analysis information indicating whether the instruction matches with a specific instruction; and a memory that temporary stores the instruction with the analysis information, wherein the processor core includes: an instruction fetch unit that fetches the instruction stored in the memory; an instruction decode unit that decodes the instruction fetched by the instruction fetch unit; an instruction execute unit that executes the instruction decoded by the instruction decode unit; and a specific instruction execute controller that reads out the analysis information stored in the memory and controls operation of at least one of the instruction fetch unit and the instruction decode unit when the analysis instruction indicates that the instruction matches with the specific instruction.
摘要翻译：微处理器包括：执行流水线处理的处理器核心; 指令分析部，分析由处理器核心处理的指令，并输出指示所述指令是否与特定指令匹配的分析信息; 以及存储器，其用所述分析信息临时存储所述指令，其中所述处理器核心包括：指令获取单元，其取出存储在所述存储器中的指令; 指令解码单元，其对由所述指令获取单元获取的指令进行解码; 指令执行单元，执行由指令解码单元解码的指令; 以及特定指令执行控制器，当分析指令指示指令与特定指令匹配时，读出存储在存储器中的分析信息并控制指令提取单元和指令解码单元中的至少一个的操作。

6. 发明授权

US07769954B2 Data processing system and method for processing data 有权
标题翻译：数据处理系统和数据处理方法
公开(公告)号：US07769954B2
公开(公告)日：2010-08-03
申请号：US11693231
申请日：2007-03-29
申请人： Kenta Yasufuku
发明人： Kenta Yasufuku
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0864 , G06F12/0877 , G06F2212/1028 , Y02D10/13
摘要： A data processing system includes: a cache memory comprising a plurality of ways, each of which stores a data line including a data and address information of the data; an analysis module that analyzes whether or not a data requested in a read instruction is to be used in a subsequent instruction to be executed within a predetermined time period after the execution of the read instruction is started; a mode selection module that selects one of a plurality of access modes for accessing the cache memory based on a result of the analysis module; and an access unit that accesses the cache memory in the selected one of the access modes when the read instruction is executed.
摘要翻译：数据处理系统包括：高速缓存存储器，包括多个方式，每个路径存储包括数据的数据线和数据的地址信息; 分析模块，其在执行所述读取指令之后的预定时间段内分析在所述读取指令中请求的数据是否被使用在待执行的后续指令中; 模式选择模块，其基于所述分析模块的结果选择用于访问高速缓冲存储器的多个访问模式之一; 以及访问单元，当执行读取指令时，访问所选择的一个访问模式中的高速缓冲存储器。

7. 发明授权

US08612692B2 Variable write back timing to nonvolatile semiconductor memory 有权
标题翻译：可变写回定时到非易失性半导体存储器
公开(公告)号：US08612692B2
公开(公告)日：2013-12-17
申请号：US13052203
申请日：2011-03-21
申请人： Kenta Yasufuku , Masaki Miyagawa , Goh Uemura , Tsutomu Owa , Tsutomu Unesaki , Atsushi Kunimatsu
发明人： Kenta Yasufuku , Masaki Miyagawa , Goh Uemura , Tsutomu Owa , Tsutomu Unesaki , Atsushi Kunimatsu
IPC分类号： G06F12/12
CPC分类号： G06F12/0893 , G06F12/0804 , G06F12/126 , G06F2212/2022
摘要： According to one embodiment, an information processing device includes a first determination section and a setting section. The first determination section determines inconsistency between first data and second data. The first data is stored in a nonvolatile semiconductor memory. The second data is corresponding to the first data and stored in a semiconductor memory. The setting section sets execution timing of write back based on access frequency information associated with the second data.
摘要翻译：根据一个实施例，信息处理设备包括第一确定部分和设置部分。第一确定部分确定第一数据与第二数据之间的不一致性。第一数据存储在非易失性半导体存储器中。第二数据对应于第一数据并存储在半导体存储器中。设置部分基于与第二数据相关联的访问频率信息来设置回写的执行定时。

8. 发明授权

US08151036B2 Memory controller, memory system, and access control method of flash memory 有权
标题翻译：内存控制器，内存系统和闪存的访问控制方法
公开(公告)号：US08151036B2
公开(公告)日：2012-04-03
申请号：US12392276
申请日：2009-02-25
申请人： Kenta Yasufuku
发明人： Kenta Yasufuku
IPC分类号： G06F12/00 , G06F11/10
CPC分类号： G06F12/0246 , G06F2212/7203 , Y02D10/13
摘要： A memory controller adds dummy data to write data by referring to instruction information about a descriptor transfer of the write data if a size of the write data to be written according to a data-write request information does not match a page size unit, thereby adjusting the size of the write data to the page size unit and then outputs the write data.
摘要翻译：如果要根据数据写入请求信息写入的写入数据的大小与页面大小单位不匹配，则通过参考关于写入数据的描述符传送的指令信息，将存储器控制器添加伪数据以写入数据，由此调整将写入数据的大小写入页面大小单元，然后输出写入数据。

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