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1. 发明授权

US06833337B2 Method for fabricating shaped monolithic ceramics and ceramic composites through displacive compensation of porosity, and ceramics and composites made thereby 失效
标题翻译：通过孔隙度的置换补偿制造成形的整体陶瓷和陶瓷复合材料的方法，以及由此制成的陶瓷和复合材料
公开(公告)号：US06833337B2
公开(公告)日：2004-12-21
申请号：US10158600
申请日：2002-05-30
申请人： Kenneth H. Sandhage , Pragati Kumar
发明人： Kenneth H. Sandhage , Pragati Kumar
IPC分类号： C04B3800
CPC分类号： C22C1/1036 , C04B35/622 , Y10T428/249957
摘要： The present invention is a method for fabricating shaped monolithic ceramics and ceramic composites, and the ceramics and composites made thereby. The method of the present invention includes three basic steps: (1) Synthesis or other acquisition of a porous preform with an appropriate composition, pore fraction, and overall shape is prepared or obtained. The pore fraction of the preform is tailored so that the reaction-induced increase in solid volume can compensate partially or completely for such porosity. It will be understood that the porous preform need only be sufficiently dimensionally stable to resist the capillary action of the infiltrated liquid reactant; (2) Infiltration: The porous preform is infiltrated with a liquid reactant; and (3) Reaction: The liquid reactant is allowed to react partially or completely with the solid preform to produce a dense, shaped body containing desired ceramic phase(s). The reaction in step (3) above is a displacement reaction of the following general type between a liquid species, M(l), and a solid preform comprising the compound, NBXC(s): AM(l)+NBXC(s)=AMXC/A(s)+BN(l/g) where MXC/A(s) is a solid reaction product (X is a metalloid element, such as, for example, oxygen, nitrogen, sulfur, etc.) and N(l/g) is a fluid (liquid or gas) reaction product. A, B and C are molar coefficients.
摘要翻译：本发明是一种制造成形的整体陶瓷和陶瓷复合材料的方法，以及由此制成的陶瓷和复合材料。本发明的方法包括三个基本步骤：（1）制备或获得具有适当组成，孔隙分数和整体形状的多孔预型体的合成或其它方法。定制预制件的孔隙分数，使得反应引起的固体体积增加可以部分地或完全地补偿这种孔隙率。应当理解，多孔预成型件仅需要足够的尺寸稳定性以抵抗渗透的液体反应物的毛细管作用; （2）渗透：多孔预型体用液体反应物渗透; 和（3）反应：使液体反应物部分或完全与固体预成型体反应，以产生含有所需陶瓷相的致密的成型体。上述步骤（3）中的反应是液体物质M（1）和包含该化合物NBXC的固体预制品之间的以下通用类型的置换反应：AM（1）+ NBXC（s）= AMXC / A（s）+ BN（1 / g）其中MXC / A（s）是固体反应产物（X是类金属元素，例如氧，氮，硫等）和N（ l / g）是流体（液体或气体）反应产物。 A，B和C是摩尔系数。

2. 发明授权

US06407022B1 Method for fabricating shaped monolithic ceramics 失效
标题翻译：成型整体陶瓷的制造方法
公开(公告)号：US06407022B1
公开(公告)日：2002-06-18
申请号：US09296138
申请日：1999-04-21
申请人： Kenneth H. Sandhage , Pragati Kumar
发明人： Kenneth H. Sandhage , Pragati Kumar
IPC分类号： C04B3800
CPC分类号： C22C1/1036 , C04B35/622 , Y10T428/249957
摘要： The process of the present invention comprises a method for fabricating shaped monolithic ceramics and ceramic composites through displacive compensation of porosity, and ceramics and composites made thereby. The method of the present invention includes three basic steps: 1) Synthesis or other acquisition of a porous preform: A porous preform with an appropriate composition, pore fraction, and overall shape is prepared or obtained. The pore fraction of the preform is tailored so that the reaction-induced increase in solid volume can compensate partially or completely for such porosity. It will be understood that the porous preform need only be sufficiently dimensionally stable to resist the capillary action of the infiltrated liquid reactant; 2) Infiltration: The porous preform is infiltrated with a liquid reactant; and 3) Reaction: The liquid reactant is allowed to react partially or completely with the solid preform to produce a dense, shaped body containing desired ceramic phase(s). The reaction in step 3) above is a displacement reaction of the following general type between a liquid species, M(l), and a solid preform comprising the compound, NBXC(s): AM(l)+NBXC(s)=AMXC/A(s)+BN(l/g)(2) where MXC/A(s) is a solid reaction product (X is a metalloid element, such as, for example, oxygen, nitrogen, sulfur, etc.) and N(l/g) is a fluid (liquid or gas) reaction product. A, B and C are molar coefficients.
摘要翻译：本发明的方法包括通过孔隙度的置换补偿制造成形的整体陶瓷和陶瓷复合材料的方法，以及由此制成的陶瓷和复合材料。本发明的方法包括三个基本步骤：1）多孔预型体的合成或其它的获取：制备或获得具有适当组成，孔隙率和整体形状的多孔预成型体。定制预制件的孔隙分数，使得反应引起的固体体积增加可以部分地或完全地补偿这种孔隙率。应当理解，多孔预成型件仅需要足够的尺寸稳定性以抵抗渗透的液体反应物的毛细管作用; 2）渗透：多孔预型体用液体反应物渗透; 和3）反应：使液体反应物部分或完全与固体预成型体反应，以产生含有所需陶瓷相的致密的成型体。上述步骤3）中的反应是以下通用类型的位移反应液体物质M（1）和包含该化合物NBXC的固体预制品：其中MXC / A（s）是固体反应产物（X是类金属元素，例如氧，氮，硫等）和N（1 / g）是流体（液体或气体）反应产物。 A，B和C是摩尔系数。

3. 发明授权

US08486727B2 System and method for step coverage measurement 失效
标题翻译：步骤覆盖测量的系统和方法
公开(公告)号：US08486727B2
公开(公告)日：2013-07-16
申请号：US12946846
申请日：2010-11-15
申请人： Hanhong Chen , Edward Haywood , Pragati Kumar
发明人： Hanhong Chen , Edward Haywood , Pragati Kumar
IPC分类号： G01R31/26 , H01L21/66
CPC分类号： G01N23/223 , H01L22/12
摘要： Determining an unknown step coverage of a thin film deposited on a 3D wafer includes exposing a planar wafer comprising a first film deposited thereon to X-ray radiation to create first fluorescent radiation; detecting the first fluorescent radiation; measuring a number of XRF counts on the planar wafer; creating an XRF model of the planar wafer; providing a portion of the 3D wafer comprising troughs and a second film deposited thereon; determining a multiplier factor between the portion of the 3D wafer and the planar wafer; exposing the portion of the 3D wafer to X-ray radiation to create second fluorescent radiation; detecting the second fluorescent radiation; measuring a number of XRF counts on the portion of the 3D wafer; calculating a step coverage of the portion of the 3D wafer; and determining a uniformity of the 3D wafer based on the step coverage of the portion of the 3D wafer.
摘要翻译：确定沉积在3D晶片上的薄膜的未知步骤覆盖包括将包括沉积在其上的第一膜的平面晶片暴露于X射线辐射以产生第一荧光辐射; 检测第一荧光辐射; 测量平面晶片上的XRF数量; 创建平面晶片的XRF模型; 提供包括槽的3D晶片的一部分和沉积在其上的第二膜; 确定所述3D晶片的所述部分和所述平面晶片之间的乘数; 将3D晶片的部分暴露于X射线辐射以产生第二荧光辐射; 检测第二荧光辐射; 测量3D晶片部分上的XRF数量; 计算3D晶片的部分的台阶覆盖; 以及基于所述3D晶片的所述部分的台阶覆盖来确定所述3D晶片的均匀性。

4. 发明授权

US08481338B2 ALD processing techniques for forming non-volatile resistive-switching memories 有权
标题翻译：用于形成非易失性电阻式切换存储器的ALD处理技术
公开(公告)号：US08481338B2
公开(公告)日：2013-07-09
申请号：US13184335
申请日：2011-07-15
申请人： Nobi Fuchigami , Pragati Kumar , Prashant Phatak
发明人： Nobi Fuchigami , Pragati Kumar , Prashant Phatak
IPC分类号： H01L21/00
CPC分类号： H01L45/146 , H01L27/2409 , H01L27/2463 , H01L45/08 , H01L45/10 , H01L45/1233 , H01L45/1253 , H01L45/1616
摘要： ALD processing techniques for forming non-volatile resistive-switching memories are described. In one embodiment, a method includes forming a first electrode on a substrate, maintaining a pedestal temperature for an atomic layer deposition (ALD) process of less than 100° Celsius, forming at least one metal oxide layer over the first electrode, wherein the forming the at least one metal oxide layer is performed using the ALD process using a purge duration of less than 20 seconds, and forming a second electrode over the at least one metal oxide layer.
摘要翻译：描述用于形成非易失性电阻式切换存储器的ALD处理技术。在一个实施例中，一种方法包括在衬底上形成第一电极，保持小于100℃的原子层沉积（ALD）工艺的基座温度，在第一电极上形成至少一个金属氧化物层，其中形成所述至少一个金属氧化物层使用ALD工艺，使用小于20秒的吹扫持续时间，并在所述至少一个金属氧化物层上形成第二电极。

5. 发明授权

US08367463B2 Methods for forming resistive-switching metal oxides for nonvolatile memory elements 有权
标题翻译：用于形成用于非易失性存储元件的电阻式开关金属氧化物的方法
公开(公告)号：US08367463B2
公开(公告)日：2013-02-05
申请号：US13111230
申请日：2011-05-19
申请人： Pragati Kumar , Sandra G. Malhotra , Sean Barstow , Tony Chiang
发明人： Pragati Kumar , Sandra G. Malhotra , Sean Barstow , Tony Chiang
IPC分类号： H01L21/00 , H01L21/16 , H01L21/20 , H01L21/36
CPC分类号： H01L45/1625 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/1641
摘要： Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed from resistive-switching metal oxide layers. Metal oxide layers may be formed using sputter deposition at relatively low sputtering powers, relatively low duty cycles, and relatively high sputtering gas pressures. Dopants may be incorporated into a base oxide layer at an atomic concentration that is less than the solubility limit of the dopant in the base oxide. At least one oxidation state of the metal in the base oxide is preferably different than at least one oxidation sate of the dopant. The ionic radius of the dopant and the ionic radius of the metal may be selected to be close to each other. Annealing and oxidation operations may be performed on the resistive switching metal oxides. Bistable metal oxides with relatively large resistivities and large high-state-to-low state resistivity ratios may be produced.
摘要翻译：提供具有电阻开关金属氧化物的非易失性存储元件。非易失性存储元件可以由电阻式开关金属氧化物层形成。金属氧化物层可以使用相对低的溅射功率，相对低的占空比和较高的溅射气体压力的溅射沉积形成。掺杂剂可以以小于基底氧化物中的掺杂剂的溶解度极限的原子浓度结合到基底氧化物层中。基底氧化物中金属的至少一种氧化态优选不同于掺杂剂的至少一种氧化态。可以选择掺杂剂的离子半径和金属的离子半径彼此接近。可以对电阻式开关金属氧化物进行退火和氧化操作。可以制造具有相对较大的电阻率和大的高 - 低 - 电阻率比的双稳态金属氧化物。

6. 发明申请

US20120319070A1 RESISTIVE-SWITCHING NONVOLATILE MEMORY ELEMENTS 有权
标题翻译：电阻开关非易失性存储器元件
公开(公告)号：US20120319070A1
公开(公告)日：2012-12-20
申请号：US13333742
申请日：2011-12-21
申请人： Pragati Kumar , Sandra G. Malhotra , Sean Barstow , Tony Chiang
发明人： Pragati Kumar , Sandra G. Malhotra , Sean Barstow , Tony Chiang
IPC分类号： H01L47/00
CPC分类号： H01L45/1253 , G11C13/0007 , G11C13/003 , G11C2213/32 , G11C2213/51 , G11C2213/52 , G11C2213/56 , G11C2213/71 , G11C2213/72 , G11C2213/74 , G11C2213/76 , G11C2213/79 , H01L27/2409 , H01L27/2463 , H01L29/861 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/1608 , H01L45/165
摘要： Nonvolatile memory elements are provided comprising switching metal oxides. The nonvolatile memory elements may be formed in one or more layers on an integrated circuit. Each memory element may have a first conductive layer, a metal oxide layer, and a second conductive layer. Electrical devices may be coupled in series with the memory elements. The first conductive layer may be formed from a metal nitride. The metal oxide layer may contain the same metal as the first conductive layer. The metal oxide may form an ohmic contact or a Schottky contact with the first conductive layer. The second conductive layer may form an ohmic contact or a Schottky contact with the metal oxide layer. The first conductive layer, the metal oxide layer, and the second conductive layer may include sublayers. The second conductive layer may include an adhesion or barrier layer and a workfunction control layer.
摘要翻译：提供包括开关金属氧化物的非易失性存储元件。非易失性存储元件可以形成在集成电路上的一个或多个层中。每个存储元件可以具有第一导电层，金属氧化物层和第二导电层。电气设备可以与存储器元件串联耦合。第一导电层可以由金属氮化物形成。金属氧化物层可以包含与第一导电层相同的金属。金属氧化物可以与第一导电层形成欧姆接触或肖特基接触。第二导电层可以与金属氧化物层形成欧姆接触或肖特基接触。第一导电层，金属氧化物层和第二导电层可以包括子层。第二导电层可以包括粘合或阻挡层和功函数控制层。

7. 发明申请

US20120256155A1 Closed loop sputtering controlled to enhance electrical characteristics in deposited layer 有权
标题翻译：控制闭环溅射以增强沉积层中的电特性
公开(公告)号：US20120256155A1
公开(公告)日：2012-10-11
申请号：US13249631
申请日：2011-09-30
申请人： Wayne French , Pragati Kumar , Prashant Phatak , Tony Chiang
发明人： Wayne French , Pragati Kumar , Prashant Phatak , Tony Chiang
IPC分类号： H01L45/00
CPC分类号： C23C14/083 , C23C14/0042 , C23C14/54 , H01L27/2409 , H01L27/2463 , H01L45/08 , H01L45/1233 , H01L45/146 , H01L45/1625 , H01L45/1641 , H01L45/165
摘要： This disclosure provides a method of fabricating a semiconductor device layer and an associated memory cell. Empirical data may be used to generate a hysteresis curve associated with deposition for a metal-insulator-metal structure, with curve measurements reflecting variance of an electrical property as a function of cathode voltage used during a sputtering process. By generating at least one voltage level to be used during the sputtering process, where the voltage reflects a suitable value for the electrical property from among the values obtainable in mixed-mode deposition, a semiconductor device layer may be produced with improved characteristics and durability. A multistable memory cell or array of such cells manufactured according to this process can, for a set of given materials, be fabricated to have minimal leakage or “off” current characteristics (Ileak or Ioff, respectively) or a maximum ratio of “on” current to “off” current (Ion/Ioff).
摘要翻译：本公开提供了制造半导体器件层和相关联的存储单元的方法。经验数据可用于产生与金属 - 绝缘体 - 金属结构的沉积相关联的滞后曲线，其中曲线测量反映作为在溅射过程中使用的阴极电压的函数的电特性的变化。通过在溅射过程中产生要使用的至少一个电压电平，其中电压从混合模式沉积中可获得的值中反映适合的电特性值，可以制造具有改进的特性和耐久性的半导体器件层。对于一组给定材料制造的这种电池的多电平存储器单元或阵列可以被制造成具有最小的泄漏或截止电流特性（分别为Ileak或Ioff）或电流与截止电流的最大比率（Ion / Ioff）。

8. 发明申请

US20120088328A1 NON-VOLATILE RESISTIVE-SWITCHING MEMORIES 有权
标题翻译：非易失性电阻开关存储器
公开(公告)号：US20120088328A1
公开(公告)日：2012-04-12
申请号：US13329253
申请日：2011-12-17
申请人： Prashant Phatak , Tony Chiang , Pragati Kumar , Michael Miller
发明人： Prashant Phatak , Tony Chiang , Pragati Kumar , Michael Miller
IPC分类号： H01L21/8239
CPC分类号： H01L45/146 , G11C13/0007 , G11C2213/32 , G11C2213/55 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L29/8615 , H01L45/08 , H01L45/10 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/1616 , H01L45/1625 , H01L45/1641 , H01L45/165 , H01L45/1658 , H01L47/00
摘要： Non-volatile resistive-switching memories are described, including a memory element having a first electrode, a second electrode, a metal oxide between the first electrode and the second electrode. The metal oxide switches using bulk-mediated switching, has a bandgap greater than 4 electron volts (eV), has a set voltage for a set operation of at least one volt per one hundred angstroms of a thickness of the metal oxide, and has a leakage current density less than 40 amps per square centimeter (A/cm2) measured at 0.5 volts (V) per twenty angstroms of the thickness of the metal oxide.
摘要翻译：描述了非易失性电阻式切换存储器，包括在第一电极和第二电极之间具有第一电极，第二电极，金属氧化物的存储元件。使用大容量介导的开关的金属氧化物开关具有大于4电子伏特（eV）的带隙，具有用于金属氧化物的厚度每100埃至少一伏特的设定操作的设定电压，并且具有漏电流密度小于每平方厘米40安培（A / cm2），每0.5伏（V），金属氧化物厚度每20埃测得。

9. 发明授权

US08144498B2 Resistive-switching nonvolatile memory elements 有权
标题翻译：电阻式开关非易失性存储元件
公开(公告)号：US08144498B2
公开(公告)日：2012-03-27
申请号：US12114667
申请日：2008-05-02
申请人： Pragati Kumar , Sandra G. Malhotra , Sean Barstow , Tony Chiang
发明人： Pragati Kumar , Sandra G. Malhotra , Sean Barstow , Tony Chiang
IPC分类号： G11C11/00
CPC分类号： H01L45/1253 , G11C13/0007 , G11C13/003 , G11C2213/32 , G11C2213/51 , G11C2213/52 , G11C2213/56 , G11C2213/71 , G11C2213/72 , G11C2213/74 , G11C2213/76 , G11C2213/79 , H01L27/2409 , H01L27/2463 , H01L29/861 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/1608 , H01L45/165
摘要： Nonvolatile memory elements are provided that have resistive switching metal oxides. The nonvolatile memory elements may be formed in one or more layers on an integrated circuit. Each memory element may have a first conductive layer, a metal oxide layer, and a second conductive layer. Electrical devices such as diodes may be coupled in series with the memory elements. The first conductive layer may be formed from a metal nitride. The metal oxide layer may contain the same metal as the first conductive layer. The metal oxide may form an ohmic contact or a Schottky contact with the first conductive layer. The second conductive layer may form an ohmic contact or a Schottky contact with the metal oxide layer. The first conductive layer, the metal oxide layer, and the second conductive layer may include sublayers. The second conductive layer may include an adhesion or barrier layer and a workfunction control layer.
摘要翻译：提供具有电阻开关金属氧化物的非易失性存储元件。非易失性存储元件可以形成在集成电路上的一个或多个层中。每个存储元件可以具有第一导电层，金属氧化物层和第二导电层。诸如二极管的电气设备可以与存储器元件串联耦合。第一导电层可以由金属氮化物形成。金属氧化物层可以包含与第一导电层相同的金属。金属氧化物可以与第一导电层形成欧姆接触或肖特基接触。第二导电层可以与金属氧化物层形成欧姆接触或肖特基接触。第一导电层，金属氧化物层和第二导电层可以包括子层。第二导电层可以包括粘合或阻挡层和功函数控制层。

10. 发明申请

US20110014359A1 Yttrium and Titanium High-K Dielectric Film 有权
标题翻译：钇和钛高K电介质膜
公开(公告)号：US20110014359A1
公开(公告)日：2011-01-20
申请号：US12921776
申请日：2009-04-17
申请人： Imran Hashim , Indranil De , Tony Chiang , Edward Haywood , Hanhong Chen , Nobi Fuchigami , Pragati Kumar , Sandra Malhotra , Sunil Shanker
发明人： Imran Hashim , Indranil De , Tony Chiang , Edward Haywood , Hanhong Chen , Nobi Fuchigami , Pragati Kumar , Sandra Malhotra , Sunil Shanker
IPC分类号： B05D5/12
CPC分类号： H01L28/65 , C23C16/405 , C23C16/45529 , C23C16/45531 , H01L21/02697 , H01L21/3141 , H01L21/31604 , H01L27/10852 , H01L28/40
摘要： This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on yttrium and titanium to have a high dielectric constant and low leakage characteristic and (b) related devices and structures. An oxide layer having both yttrium and titanium may be fabricated either as an amorphous oxide or as an alternating series of monolayers. In several embodiments, the oxide is characterized by a yttrium contribution to total metal that is specifically controlled. The oxide layer can be produced as the result of a reactive process, if desired, via either a PVD process or, alternatively, via an atomic layer deposition process that employs specific precursor materials to allow for a common process temperature window for both titanium and yttrium reactions.
摘要翻译：本公开内容提供（a）制造基于钇和钛的氧化物层（例如，电介质层）具有高介电常数和低泄漏特性的方法，以及（b）相关的器件和结构。具有钇和钛的氧化物层可以制成无定形氧化物或交替的单层系列。在几个实施方案中，氧化物的特征在于对特定控制的总金属的钇贡献。如果需要，可以通过PVD工艺或者通过使用特定的前体材料以允许钛和钇的共同工艺温度窗口的原子层沉积工艺，作为反应过程的结果来生产氧化物层反应。

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