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1. 发明申请

US20100245663A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND TRANSMITTER APPARATUS HAVING THE SAME 有权
标题翻译：半导体集成电路及其发送装置
公开(公告)号：US20100245663A1
公开(公告)日：2010-09-30
申请号：US12376405
申请日：2007-07-31
申请人： Manabu Kawabata , Ryogo Yanagisawa , Toru Iwata , Hirokazu Sugimoto
发明人： Manabu Kawabata , Ryogo Yanagisawa , Toru Iwata , Hirokazu Sugimoto
IPC分类号： H04N7/01 , G06F1/04 , H04N5/05
CPC分类号： H03K5/135 , H03L7/18 , H03M9/00 , H04L7/0008
摘要： A semiconductor integrated circuit (10D) for receiving a parallel data signal and a first clock signal and outputting a serial data signal and a second clock signal, wherein a first clock generation circuit (15) produces a third clock signal obtained by multiplying the first clock signal by X/Y. A second clock generation circuit (11) has a variable transmission characteristic, and produces a fourth clock signal obtained by multiplying the third clock signal by N. A parallel/serial conversion section (12) converts the parallel data signal, which has been converted by a scaler (16), to the serial data signal in synchronism with the fourth clock signal. A frequency divider (13) produces a fifth clock signal obtained by dividing a frequency of the fourth clock signal by N. A selector (14) selectively outputs, as the second clock signal, one of the third and fifth clock signals.
摘要翻译：一种用于接收并行数据信号和第一时钟信号并输出串行数据信号和第二时钟信号的半导体集成电路（10D），其中第一时钟产生电路（15）产生通过将第一时钟信号X / Y。第二时钟发生电路（11）具有可变的传输特性，并且产生通过将第三时钟信号乘以N而获得的第四时钟信号。并行/串行转换部分（12）将已被转换的并行数据信号缩放器（16），与第四时钟信号同步地连接到串行数据信号。分频器（13）产生通过将第四时钟信号的频率除以N而获得的第五时钟信号。选择器（14）有选择地输出第三和第五时钟信号之一作为第二时钟信号。

2. 发明授权

US08004433B2 Semiconductor integrated circuit and transmitter apparatus having the same 有权
标题翻译：具有相同的半导体集成电路和发射机装置
公开(公告)号：US08004433B2
公开(公告)日：2011-08-23
申请号：US12376405
申请日：2007-07-31
申请人： Manabu Kawabata , Ryogo Yanagisawa , Toru Iwata , Hirokazu Sugimoto
发明人： Manabu Kawabata , Ryogo Yanagisawa , Toru Iwata , Hirokazu Sugimoto
IPC分类号： H03M9/00
CPC分类号： H03K5/135 , H03L7/18 , H03M9/00 , H04L7/0008
摘要： A semiconductor integrated circuit (10D) for receiving a parallel data signal and a first clock signal and outputting a serial data signal and a second clock signal, wherein a first clock generation circuit (15) produces a third clock signal obtained by multiplying the first clock signal by X/Y. A second clock generation circuit (11) has a variable transmission characteristic, and produces a fourth clock signal obtained by multiplying the third clock signal by N. A parallel/serial conversion section (12) converts the parallel data signal, which has been converted by a scaler (16), to the serial data signal in synchronism with the fourth clock signal. A frequency divider (13) produces a fifth clock signal obtained by dividing a frequency of the fourth clock signal by N. A selector (14) selectively outputs, as the second clock signal, one of the third and fifth clock signals.
摘要翻译：一种用于接收并行数据信号和第一时钟信号并输出串行数据信号和第二时钟信号的半导体集成电路（10D），其中第一时钟产生电路（15）产生通过将第一时钟信号X / Y。第二时钟发生电路（11）具有可变的传输特性，并且产生通过将第三时钟信号乘以N而获得的第四时钟信号。并行/串行转换部分（12）将已被转换的并行数据信号缩放器（16），与第四时钟信号同步地连接到串行数据信号。分频器（13）产生通过将第四时钟信号的频率除以N而获得的第五时钟信号。选择器（14）有选择地输出第三和第五时钟信号之一作为第二时钟信号。

3. 发明授权

US07864252B2 Video signal processor capable of suppressing excessive heat generation, method using the same, display device and method using the same 有权
标题翻译：能够抑制过度发热的视频信号处理器，使用其的方法，显示装置及使用其的方法
公开(公告)号：US07864252B2
公开(公告)日：2011-01-04
申请号：US11071190
申请日：2005-03-04
申请人： Satoshi Takahashi , Ryogo Yanagisawa , Toru Iwata
发明人： Satoshi Takahashi , Ryogo Yanagisawa , Toru Iwata
IPC分类号： H04N5/63 , H04N17/00 , H04N5/44 , H03L7/00
CPC分类号： G09G5/006 , G09G3/2092
摘要： A video signal processor for processing input video data in accordance with an input clock signal includes: an input section for changing the format of the video data and outputting resultant data; a logic section for decoding the data output from the input section and outputting decoded data; and a frequency detector for detecting that the clock signal has a frequency higher than a given frequency and outputting a result of the detection as a detection signal. When the frequency of the clock signal is higher than the given frequency, operation of at least part of circuits constituting the video signal processor is stopped in accordance with the detection signal.
摘要翻译：用于根据输入时钟信号处理输入视频数据的视频信号处理器包括：输入部分，用于改变视频数据的格式并输出结果数据; 逻辑部分，用于对从输入部分输出的数据进行解码并输出解码数据; 以及频率检测器，用于检测时钟信号具有高于给定频率的频率，并将检测结果作为检测信号输出。当时钟信号的频率高于给定频率时，根据检测信号停止构成视频信号处理器的电路的至少一部分的操作。

4. 发明授权

US08515065B2 Video input device and video display system 有权
标题翻译：视频输入设备和视频显示系统
公开(公告)号：US08515065B2
公开(公告)日：2013-08-20
申请号：US13371097
申请日：2012-02-10
申请人： Shinya Murakami , Ryogo Yanagisawa , Syuji Kato , Toru Iwata
发明人： Shinya Murakami , Ryogo Yanagisawa , Syuji Kato , Toru Iwata
IPC分类号： H04N7/167
CPC分类号： H04N21/4367 , H04N21/43635
摘要： An input processing circuit decodes a digital video signal selected by an input signal selector. Decryption circuits each decrypt the encryption of a video signal output from the input processing circuit, and generate an authentication key of the encryption. A video signal selector selects and outputs one of the video signals output from the decryption circuits, to a monitor. The decryption circuits each include a pseudo-signal generation circuit which extracts information from the video signal, and based on the extracted information, generates a pseudo-video signal.
摘要翻译：输入处理电路解码由输入信号选择器选择的数字视频信号。解密电路各自解密从输入处理电路输出的视频信号的加密，并生成加密的认证密钥。视频信号选择器将从解密电路输出的视频信号中的一个选择并输出到监视器。解密电路各自包括从视频信号提取信息的伪信号生成电路，并且基于所提取的信息，生成伪视频信号。

5. 发明申请

US20110007043A1 VIDEO SIGNAL PROCESSOR CAPABLE OF SUPPRESSING EXCESSIVE HEAT GENERATION, METHOD USING THE SAME, DISPLAY DEVICE AND METHOD USING THE SAME 审中-公开
标题翻译：能够抑制过热发生的视频信号处理器，使用其的方法，显示装置和使用该方法的方法
公开(公告)号：US20110007043A1
公开(公告)日：2011-01-13
申请号：US12887107
申请日：2010-09-21
申请人： Satoshi TAKAHASHI , Ryogo Yanagisawa , Toru Iwata
发明人： Satoshi TAKAHASHI , Ryogo Yanagisawa , Toru Iwata
IPC分类号： G09G5/00
CPC分类号： G09G5/006 , G09G3/2092
摘要： A video signal processor for processing input video data in accordance with an input clock signal includes: an input section for changing the format of the video data and outputting resultant data; a logic section for decoding the data output from the input section and outputting decoded data; and a frequency detector for detecting that the clock signal has a frequency higher than a given frequency and outputting a result of the detection as a detection signal. When the frequency of the clock signal is higher than the given frequency, operation of at least part of circuits constituting the video signal processor is stopped in accordance with the detection signal.
摘要翻译：用于根据输入时钟信号处理输入视频数据的视频信号处理器包括：输入部分，用于改变视频数据的格式并输出结果数据; 逻辑部分，用于对从输入部分输出的数据进行解码并输出解码数据; 以及频率检测器，用于检测时钟信号具有高于给定频率的频率，并将检测结果作为检测信号输出。当时钟信号的频率高于给定频率时，根据检测信号停止构成视频信号处理器的电路的至少一部分的操作。

6. 发明申请

US20050231493A1 Video signal processor, method using the same, display device and method using the same 有权
标题翻译：视频信号处理器，使用该方法的方法，显示装置和使用其的方法
公开(公告)号：US20050231493A1
公开(公告)日：2005-10-20
申请号：US11071190
申请日：2005-03-04
申请人： Satoshi Takahashi , Ryogo Yanagisawa , Toru Iwata
发明人： Satoshi Takahashi , Ryogo Yanagisawa , Toru Iwata
IPC分类号： G09G5/00 , G06F13/14 , G09G3/20 , H03K5/19 , H03L7/00 , H04N5/14
CPC分类号： G09G5/006 , G09G3/2092
摘要： A video signal processor for processing input video data in accordance with an input clock signal includes: an input section for changing the format of the video data and outputting resultant data; a logic section for decoding the data output from the input section and outputting decoded data; and a frequency detector for detecting that the clock signal has a frequency higher than a given frequency and outputting a result of the detection as a detection signal. When the frequency of the clock signal is higher than the given frequency, operation of at least part of circuits constituting the video signal processor is stopped in accordance with the detection signal.
摘要翻译：用于根据输入时钟信号处理输入视频数据的视频信号处理器包括：输入部分，用于改变视频数据的格式并输出结果数据; 逻辑部分，用于对从输入部分输出的数据进行解码并输出解码数据; 以及频率检测器，用于检测时钟信号具有高于给定频率的频率，并将检测结果作为检测信号输出。当时钟信号的频率高于给定频率时，根据检测信号停止构成视频信号处理器的电路的至少一部分的操作。

7. 发明申请

US20090028280A1 TRANSMITTER AND TRANSMITTER/RECEIVER 审中-公开
标题翻译：发射机和发射机/接收机
公开(公告)号：US20090028280A1
公开(公告)日：2009-01-29
申请号：US12280726
申请日：2007-01-09
申请人： Ryogo Yanagisawa , Satoshi Takahashi , Yoshihiro Tabira
发明人： Ryogo Yanagisawa , Satoshi Takahashi , Yoshihiro Tabira
IPC分类号： H04L7/00
CPC分类号： H04L7/0008 , G09G5/008 , G09G2370/12 , H04N21/242 , H04N21/4302
摘要： A clock control circuit 22 in a control circuit 21 provided in a transmitter 25 controls a gate circuit 12 based on an instruction from a microcomputer 32 to stop the output of the clock to a cable 115 for a first predetermined period of time. Then, a read-out circuit in the microcomputer 32 accesses an EDID 31 stored in an information storing circuit of a receiver 43 via the cable 115, and specifies the first predetermined period of time based on the EDID 31. A reconfiguration circuit 42 provided in the receiver 43 counts the clock-holding state, and resets at least one of the receiver 43 and a TV 114 if the clock has been stopped for a second predetermined period of time. This reset operation suppresses the display of noise on the TV 114. Therefore, the occurrence of noise due to mis-latching between the clock and the data can be reduced even after a signal switching that entails a change in the clock frequency.
摘要翻译：设置在发送器25中的控制电路21中的时钟控制电路22基于来自微型计算机32的指令来控制门电路12，以在第一预定时间段内将时钟的输出停止到电缆115。然后，微计算机32中的读出电路通过电缆115访问存储在接收机43的信息存储电路中的EDID 31，并基于EDID 31指定第一预定时间段。一种重配置电路42，接收器43计数时钟保持状态，并且如果时钟已经停止了第二预定时间段，则复位接收器43和TV 114中的至少一个。该复位操作抑制TV 114上的噪声的显示。因此，即使在需要时钟频率变化的信号切换之后，也可以减少由于时钟和数据之间的误锁而引起的噪声的发生。

8. 发明申请

US20090257453A1 TRANSMISSION APPARATUS AND RECEIVING APPARATUS 审中-公开
标题翻译：传输装置和接收装置
公开(公告)号：US20090257453A1
公开(公告)日：2009-10-15
申请号：US12420506
申请日：2009-04-08
申请人： Ryogo Yanagisawa , Syuji Kato , Satoshi Takahashi
发明人： Ryogo Yanagisawa , Syuji Kato , Satoshi Takahashi
IPC分类号： H04J1/00
CPC分类号： H04N7/083 , G09G5/008 , G09G2370/12 , H03L7/093 , H03L7/18 , H04L7/0008
摘要： In an audio and video transmission apparatus, a frequency division parameter control unit outputs a frequency division parameter Pt, Qt for relating a pixel clock (frequency: pclk) for video data with an audio clock (frequency: ft) for audio data. An audio/video/packet multiplexing unit converts audio data and the frequency division parameter Pt, Qt into packets, and superimposes the packets into blanking intervals of video data, thereby producing transmission data. The frequency division parameter Pt, Qt satisfies a relationship represented by: pclk/Pt=ft/Qt=fpt, and cause fpt to have a value that falls outside of a predetermined band that is determined as the band of audio data.
摘要翻译：在音频和视频传输装置中，分频参数控制单元输出用于将视频数据的像素时钟（频率：pclk）与用于音频数据的音频时钟（频率：ft）相关联的分频参数Pt，Qt。音频/视频/分组复用单元将音频数据和分频参数Pt，Qt转换为分组，并将分组叠加到视频数据的消隐间隔中，从而产生传输数据。分频参数Pt，Qt满足由pclk / Pt = ft / Qt = fpt表示的关系，并且使得fpt具有落在被确定为音频数据的频带的预定频带之外的值。

9. 发明授权

US07512962B2 Multichannel display data generating apparatus, medium, and informational set 有权
标题翻译：多通道显示数据生成装置，介质和信息集
公开(公告)号：US07512962B2
公开(公告)日：2009-03-31
申请号：US11129088
申请日：2005-05-13
申请人： Shoichi Gotoh , Yoshiki Kuno , Hiroyuki Iitsuka , Masazumi Yamada , Ryogo Yanagisawa , Hirotoshi Uehara , Toshiaki Tsuji
发明人： Shoichi Gotoh , Yoshiki Kuno , Hiroyuki Iitsuka , Masazumi Yamada , Ryogo Yanagisawa , Hirotoshi Uehara , Toshiaki Tsuji
IPC分类号： G06F3/00 , G06F13/00 , H04N5/445
CPC分类号： H04N21/4305 , H04L12/40117 , H04N5/04 , H04N5/4401 , H04N5/45 , H04N21/4316 , H04N21/434 , H04N21/4344 , H04N21/43632
摘要： A multichannel display data generating apparatus for generating data for displaying AV data on a multiscreen has a plurality of screens for displaying AV data of a plurality of channels, said apparatus comprising: input means for inputting AV data of a plurality of channels being transferred using a transport packet of a transport stream; a smaller number of PCR extracting means for extracting in a time-sharing mode the PCR of a plurality of channels displayed on said plurality of screens than the number of said plurality of screens; the same number of PLL means for establishing PLL synchronization by using said extracted PCR as the number of said plurality of screens; the same number of STC (system time clock) counter means for counting the times of the channels displayed on said plurality of screens by using the oscillation frequency of said PLL means as the number of said plurality of screens; AV decoding means for AV-decoding the AV data of the channels displayed on said multiscreen in AV synchronization with said STC counter means; and output means for outputting said AV-decoded AV data; and wherein said output AV data is displayed on said multiscreen.
摘要翻译：一种用于生成用于在多画面上显示AV数据的数据的多声道显示数据产生装置具有用于显示多个声道的AV数据的多个画面，所述装置包括：输入装置，用于输入正在传送的多个频道的AV数据，传输流的传输分组; 较少数量的PCR提取装置，用于以分时模式提取在所述多个屏幕上显示的多个频道的PCR，而不是所述多个屏幕的数量; 通过使用所述提取的PCR作为所述多个屏幕的数量来建立PLL同步的相同数量的PLL装置; 相同数量的STC（系统时钟）计数器装置，用于通过使用所述PLL装置的振荡频率作为所述多个屏幕的数量来对显示在所述多个屏幕上的频道的时间进行计数; AV解码装置，用于与所述STC计数器装置AV同步地AV解码在所述多画面上显示的频道的AV数据; 以及输出装置，用于输出所述AV解码的AV数据; 并且其中所述输出AV数据显示在所述多画面上。

10. 发明申请

US20090052599A1 TRANSMITTER AND TRANSMITTER/RECEIVER 审中-公开
标题翻译：发射机和发射机/接收机
公开(公告)号：US20090052599A1
公开(公告)日：2009-02-26
申请号：US12279765
申请日：2006-11-30
申请人： Ryogo Yanagisawa , Satoshi Takahashi , Yoshihiro Tabira
发明人： Ryogo Yanagisawa , Satoshi Takahashi , Yoshihiro Tabira
IPC分类号： H04L7/00
CPC分类号： H04L7/0083 , G09G5/008 , G09G2320/0238 , H03L7/16 , H03M9/00 , H04N21/4122 , H04N21/43632
摘要： The present invention provides a transmitter capable of reducing the occurrence of noise when switching from the SD signal to the HD signal, for example. A microcomputer (151) controls a 10-times multiplication PLL (13) to increase the amount of jitter of a multiplied clock (CLK1×10) upon signal switching, i.e., when switching the frequency of an input clock (CLK1) from one to another. Alternatively, it controls a phase adjustment section (31) to increase the amount of jitter of a transmit clock (CLK2). Alternatively, it controls a fixed data producing section (61) to set transmit data (DATA2) to predetermined fixed data stored in a fixed data storing section (62).
摘要翻译：本发明提供了一种例如在从SD信号切换到HD信号时能够减少噪声的发生的发送机。微控制器（151）控制10倍乘法PLL（13），以便在信号切换时，即当将输入时钟（CLK1）的频率从一个切换到另一个时，增加倍增时钟（CLK1×10）的抖动量。或者，它控制相位调整部分（31）以增加发送时钟（CLK2）的抖动量。或者，它控制固定数据产生部分（61）将发送数据（DATA2）设置为存储在固定数据存储部分（62）中的预定固定数据。

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