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1. 发明授权

US08380917B2 Command control for synchronous memory device 有权
标题翻译：同步存储设备的命令控制
公开(公告)号：US08380917B2
公开(公告)日：2013-02-19
申请号：US12138307
申请日：2008-06-12
申请人： Kenji Shibata , Mitsuhiro Nagao , Satoru Kawmoto
发明人： Kenji Shibata , Mitsuhiro Nagao , Satoru Kawmoto
IPC分类号： G06F12/00 , G06F13/28 , G06F13/00
CPC分类号： G11C16/10 , G11C7/10 , G11C7/1072
摘要： Systems, methods, and circuits for command control for synchronous memory device are disclosed. In one embodiment, a memory device comprises a first synchronous memory controlled by a second group of commands which includes a first command receiving section for receiving a first group of commands, and a second command receiving section for receiving a command that is unique to the first synchronous memory and different from the first group of commands during execution of the first group of commands received by the first command receiving section. The synchronous memory further comprises a second synchronous memory controlled by the first group of commands, where the first synchronous memory and the second synchronous memory are coupled to a same data bus, and where the second group of commands is different from the first group of commands.
摘要翻译：公开了用于同步存储装置的命令控制的系统，方法和电路。在一个实施例中，存储器设备包括由第二组命令控制的第一同步存储器，该第二组命令包括用于接收第一组命令的第一命令接收部分和用于接收第一命令的唯一命令的第二命令接收部分同步存储器，并且在执行由第一命令接收部分接收的第一组命令期间与第一组命令不同。同步存储器还包括由第一组命令控制的第二同步存储器，其中第一同步存储器和第二同步存储器耦合到相同的数据总线，并且其中第二组命令与第一组命令不同。

2. 发明授权

US08122204B2 Shadow write and transfer schemes for memory devices 有权
标题翻译：存储设备的影子写入和传输方案
公开(公告)号：US08122204B2
公开(公告)日：2012-02-21
申请号：US12137443
申请日：2008-06-11
申请人： Mitsuhiro Nagao , Kenji Shibata , Satoru Kawmoto
发明人： Mitsuhiro Nagao , Kenji Shibata , Satoru Kawmoto
IPC分类号： G06F13/00 , G06F13/28 , G06F1/00 , G06F3/00 , G11C7/10 , G11C7/00
CPC分类号： G06F13/1694 , G06F11/1666 , G11C7/1045 , G11C7/1072 , G11C11/406 , G11C11/40622 , G11C11/4096 , Y02D10/14
摘要： Systems and methods for controlling memory devices are disclosed. In one embodiment, a memory system comprises a memory controller for forwarding a command signal and an address signal and for receiving and forwarding a data signal, and a first memory device for receiving the command signal and the address signal from the memory controller, where the first memory device comprises a first command judging circuit for receiving and forwarding the data signal and for decoding the command signal. The memory system further comprises a second memory device for receiving the command signal and the address signal from the memory controller, where the second memory device comprises a second command judging circuit for receiving and generating the data signal and for decoding the command signal. The command signal, the address signal and the data signal are commonly connected to the first memory device and the second memory device.
摘要翻译：公开了用于控制存储器件的系统和方法。在一个实施例中，存储器系统包括用于转发命令信号和地址信号并用于接收和转发数据信号的存储器控制器，以及用于从存储器控制器接收命令信号和地址信号的第一存储器件，其中第一存储装置包括用于接收和转发数据信号并用于对命令信号进行解码的第一命令判断电路。存储器系统还包括用于从存储器控制器接收命令信号和地址信号的第二存储器件，其中第二存储器件包括用于接收和产生数据信号并用于解码命令信号的第二命令判断电路。命令信号，地址信号和数据信号共同连接到第一存储器件和第二存储器件。

3. 发明申请

US20060291305A1 Semiconductor device and program data redundancy method therefor 有权
标题翻译：半导体器件及其程序数据冗余方法
公开(公告)号：US20060291305A1
公开(公告)日：2006-12-28
申请号：US11444251
申请日：2006-05-30
申请人： Norikatsu Suzuki , Makoto Niimi , Satoru Kawmoto
发明人： Norikatsu Suzuki , Makoto Niimi , Satoru Kawmoto
IPC分类号： G11C29/00
CPC分类号： G11C29/76
摘要： A semiconductor device (1) is provided which includes a regular cell array unit (30), a redundant cell array unit (31) that is provided in relation to the regular cell array unit (30), and a PGM/ER state machine (20) that controls reprogramming in which, when programming of a sector in the regular cell array unit fails (step S3), data involved in the programming that fails and data already stored in the sector in the regular cell array unit are written (step S8) into the redundant cell array unit (31). Since reprogramming is performed to write the data already written in the sector as well as the data involved in the programming that fails into the redundant cell array unit (31), data loss can be prevented and data can be secured, thereby increasing the reliability of the system.
摘要翻译：提供一种半导体器件（1），其包括正常单元阵列单元（30），相对于正常单元阵列单元（30）提供的冗余单元阵列单元（31）和PGM / ER状态机 20），其控制重编程，其中当正规单元阵列单元中的扇区的编程失败时（步骤S 3），写入编程失败的数据和已经存储在正常单元阵列单元中的扇区中的数据被写入（步骤 S 8）插入到冗余单元阵列单元（31）中。由于执行重编程以将已经写入扇区的数据以及编程中涉及的数据写入冗余单元阵列单元（31），所以可以防止数据丢失并且可以确保数据的可靠性系统。

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