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    • 2. 发明授权
    • Ultrasonic diagnosis apparatus, automatic support apparatus, and automatic support method
    • 超声波诊断装置,自动支持装置和自动支持方法
    • US08721548B2
    • 2014-05-13
    • US12822618
    • 2010-06-24
    • Tatsuro BabaNaohisa KamiyamaShuichi KawasakiCong YaoKenji Hamada
    • Tatsuro BabaNaohisa KamiyamaShuichi KawasakiCong YaoKenji Hamada
    • A61B8/00
    • A61B8/065A61B8/488A61B8/5223G06F19/00G06K9/6215G06T7/0012G06T2207/10132G06T2207/30004G16H50/20G16H50/70
    • According to one embodiment, an ultrasonic diagnosis apparatus includes a storage unit, a ultrasonic probe, a transmission/reception unit, a measured value calculation unit, a distance calculation unit, and a determination unit. The storage unit stores data of a state space based on a first measured values of a measurement item associated with an able-bodied person. The transmission/reception unit transmits ultrasonic waves to a subject via an ultrasonic probe, and generates reception signals corresponding to an ultrasonic waves reflected by the subject. The measured value calculation unit calculates a second measured value of the measurement item associated with the subject based on the reception signals. The distance calculation unit calculates a Mahalanobis distance of the subject based on the state space and the second measured value. The determination unit compares the Mahalanobis distance with a threshold to determine whether the subject has the disease evaluated by the measurement item.
    • 根据一个实施例,超声波诊断装置包括存储单元,超声波探头,发送/接收单元,测量值计算单元,距离计算单元和确定单元。 存储单元基于与健壮人相关联的测量项目的第一测量值来存储状态空间的数据。 发送/接收单元经由超声波探头向对象发送超声波,生成与被检体反射的超声波对应的接收信号。 测量值计算单元基于接收信号计算与被摄体相关联的测量项目的第二测量值。 距离计算单元基于状态空间和第二测量值来计算被摄体的马氏距离距离。 确定单元将马哈拉诺比斯距离与阈值进行比较,以确定受试者是否具有由测量项目评估的疾病。
    • 6. 发明授权
    • Circuitry for clock and method for providing clock signal
    • 时钟电路和提供时钟信号的方法
    • US08570087B2
    • 2013-10-29
    • US13311069
    • 2011-12-05
    • Shiming HeLiqian ChenCong YaoXiang LiYu LiuJiayin Lu
    • Shiming HeLiqian ChenCong YaoXiang LiYu LiuJiayin Lu
    • H03K3/00
    • H03L7/0997
    • The present invention provide a clock circuit and a method for providing a clock signal. The clock circuit includes: an adaptive clock generation circuit, configured to output an adaptive clock signal; and an adaptive clock driven circuit, configured to be driven by the adaptive clock signal to work. A maximum workable frequency of the adaptive clock driven circuit is higher than or equal to a frequency of the adaptive clock signal. When a working condition of the adaptive clock driven circuit is changed, the maximum workable frequency of the adaptive clock driven circuit is changed, the frequency of the adaptive clock signal which is output by the adaptive clock generation circuit is changed, and a changing direction of the frequency of an adaptive clock signal is consistent with that of the maximum workable frequency. The clock circuit and method may be used in design or manufacturing of a digital circuit.
    • 本发明提供一种提供时钟信号的时钟电路和方法。 时钟电路包括:自适应时钟产生电路,被配置为输出自适应时钟信号; 以及自适应时钟驱动电路,被配置为由自适应时钟信号驱动工作。 自适应时钟驱动电路的最大可工作频率高于或等于自适应时钟信号的频率。 当自适应时钟驱动电路的工作状态改变时,自适应时钟驱动电路的最大可工作频率改变,由自适应时钟发生电路输出的自适应时钟信号的频率改变,并且改变方向 自适应时钟信号的频率与最大可工作频率的频率一致。 时钟电路和方法可用于数字电路的设计或制造。
    • 7. 发明申请
    • CIRCUITRY FOR CLOCK AND METHOD FOR PROVIDING CLOCK SIGNAL
    • 用于提供时钟信号的时钟和方法的电路
    • US20120139596A1
    • 2012-06-07
    • US13311069
    • 2011-12-05
    • Shiming HeLiqian ChenCong YaoXiang LiYu LiuJiayin Lu
    • Shiming HeLiqian ChenCong YaoXiang LiYu LiuJiayin Lu
    • H03L7/085
    • H03L7/0997
    • The present invention provide a clock circuit and a method for providing a clock signal. The clock circuit includes: an adaptive clock generation circuit, configured to output an adaptive clock signal; and an adaptive clock driven circuit, configured to be driven by the adaptive clock signal to work. A maximum workable frequency of the adaptive clock driven circuit is higher than or equal to a frequency of the adaptive clock signal. When a working condition of the adaptive clock driven circuit is changed, the maximum workable frequency of the adaptive clock driven circuit is changed, the frequency of the adaptive clock signal which is output by the adaptive clock generation circuit is changed, and a changing direction of the frequency of an adaptive clock signal is consistent with that of the maximum workable frequency. The clock circuit and method may be used in design or manufacturing of a digital circuit.
    • 本发明提供一种提供时钟信号的时钟电路和方法。 时钟电路包括:自适应时钟产生电路,被配置为输出自适应时钟信号; 以及自适应时钟驱动电路,被配置为由自适应时钟信号驱动工作。 自适应时钟驱动电路的最大可工作频率高于或等于自适应时钟信号的频率。 当自适应时钟驱动电路的工作状态改变时,自适应时钟驱动电路的最大可工作频率改变,由自适应时钟发生电路输出的自适应时钟信号的频率改变,并且改变方向 自适应时钟信号的频率与最大可工作频率的频率一致。 时钟电路和方法可用于数字电路的设计或制造。
    • 8. 发明申请
    • VARIABLE-FREQUENCY BUS ADAPTER, ADAPTING METHOD AND SYSTEM
    • 可变频率总线适配器,适配方法和系统
    • US20110179207A1
    • 2011-07-21
    • US13007332
    • 2011-01-14
    • Cong YaoQiwei LiuYu LiuXiang LiLiqian ChenShiming HeJiayin Lu
    • Cong YaoQiwei LiuYu LiuXiang LiLiqian ChenShiming HeJiayin Lu
    • G06F13/14
    • G06F13/382
    • A variable-frequency bus adapter, a variable-frequency bus adapting method and a variable-frequency bus adapting system are provided. The method includes: generating a bus blocking indication according to a dynamic frequency scaling (DFS) request signal sent by a bus side; blocking a current bus transfer according to the bus blocking indication; and feeding back a DFS response signal to the bus side after blocking the current bus transfer, where the DFS response signal is adapted to enable the bus side to perform a DFS operation. In the method, the bus transfer is temporarily blocked during the DFS, so that undesired influence on peripheral components caused by unstable bus block during the bus DFS is reduced without increasing the number of clock domains of the system or modifying the peripheral components, thus reducing the complexity of the implementation of the system, and improving the applicability of dynamic voltage frequency scaling (DVFS).
    • 提供了可变频率总线适配器,可变频率总线适配方法和可变频率总线适配系统。 该方法包括:根据由总线端发送的动态频率缩放(DFS)请求信号产生总线阻塞指示; 根据总线阻塞指示阻止当前总线传输; 并且在阻止当前总线传输之后将DFS响应信号反馈给总线侧,其中DFS响应信号适于使总线端执行DFS操作。 在该方法中,在DFS期间暂时阻塞总线传输,从而在不增加系统的时钟域数量或修改外围组件的情况下减少总线DFS期间由不稳定总线块引起的对外围组件的不良影响,从而减少 实现系统的复杂性,并提高动态电压频率缩放(DVFS)的适用性。
    • 9. 发明授权
    • Ultrasonic diagnostic apparatus, positional information acquiring method, and computer program product
    • 超声波诊断装置,位置信息获取方法以及计算机程序产品
    • US08926513B2
    • 2015-01-06
    • US12688259
    • 2010-01-15
    • Cong YaoNaohisa KamiyamaYoko Okamura
    • Cong YaoNaohisa KamiyamaYoko Okamura
    • A61B8/00G06K9/00G06K9/34G06K9/40A61B8/08
    • A61B8/5223A61B8/0825A61B8/14A61B8/463A61B8/54
    • The analysis image generating unit generates section images from volume analysis data that is collected by sending an ultrasound wave down to a region under the ribs. The right/left identifying unit identifies the right or left breast from cyclic motion components in the section images. The extending direction detecting unit analyzes plane-A images or plane-B images generated from the same volume analysis data, or a plane-C thickness-added MIP image, and detects the rib extending direction. The extending direction detecting unit also determines the position of the ultrasound probe based on the relative displacement of the extending direction. The body mark generating unit generates a body mark from the analysis results obtained by the right/left identifying unit and the extending direction detecting unit. The image synthesizing unit integrates the display image generated by the display image generating unit and the body mark, and displays it on the monitor.
    • 分析图像生成单元从通过将超声波发送到肋下的区域而收集的体积分析数据生成截面图像。 右/左识别单元从截面图像中的循环运动分量识别右乳房或左乳房。 延伸方向检测单元分析从相同体积分析数据或平面C厚度增加的MIP图像生成的平面A图像或平面B图像,并且检测肋延伸方向。 延伸方向检测单元还基于延伸方向的相对位移来确定超声波探头的位置。 体标记生成单元根据由左右识别单元和延伸方向检测单元获得的分析结果生成体标记。 图像合成单元将由显示图像生成单元生成的显示图像和体标记进行积分,并将其显示在监视器上。
    • 10. 发明授权
    • Variable-frequency bus adapter, adapting method and system
    • 变频总线适配器,适配方式和系统
    • US08468286B2
    • 2013-06-18
    • US13007332
    • 2011-01-14
    • Cong YaoQiwei LiuYu LiuXiang LiLiqian ChenShiming HeJiayin Lu
    • Cong YaoQiwei LiuYu LiuXiang LiLiqian ChenShiming HeJiayin Lu
    • G06F5/06
    • G06F13/382
    • A variable-frequency bus adapter, a variable-frequency bus adapting method and a variable-frequency bus adapting system are provided. The method includes: generating a bus blocking indication according to a dynamic frequency scaling (DFS) request signal sent by a bus side; blocking a current bus transfer according to the bus blocking indication; and feeding back a DFS response signal to the bus side after blocking the current bus transfer, where the DFS response signal is adapted to enable the bus side to perform a DFS operation. In the method, the bus transfer is temporarily blocked during the DFS, so that undesired influence on peripheral components caused by unstable bus block during the bus DFS is reduced without increasing the number of clock domains of the system or modifying the peripheral components, thus reducing the complexity of the implementation of the system, and improving the applicability of dynamic voltage frequency scaling (DVFS).
    • 提供了可变频率总线适配器,可变频率总线适配方法和可变频率总线适配系统。 该方法包括:根据由总线端发送的动态频率缩放(DFS)请求信号产生总线阻塞指示; 根据总线阻塞指示阻止当前总线传输; 并且在阻止当前总线传输之后将DFS响应信号反馈给总线侧,其中DFS响应信号适于使总线端执行DFS操作。 在该方法中,在DFS期间暂时阻塞总线传输,从而在不增加系统的时钟域数量或修改外围组件的情况下减少总线DFS期间由不稳定总线块引起的对外围组件的不良影响,从而减少 实现系统的复杂性,并提高动态电压频率缩放(DVFS)的适用性。