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1. 发明授权

US08468286B2 Variable-frequency bus adapter, adapting method and system 有权
标题翻译：变频总线适配器，适配方式和系统
公开(公告)号：US08468286B2
公开(公告)日：2013-06-18
申请号：US13007332
申请日：2011-01-14
申请人： Cong Yao , Qiwei Liu , Yu Liu , Xiang Li , Liqian Chen , Shiming He , Jiayin Lu
发明人： Cong Yao , Qiwei Liu , Yu Liu , Xiang Li , Liqian Chen , Shiming He , Jiayin Lu
IPC分类号： G06F5/06
CPC分类号： G06F13/382
摘要： A variable-frequency bus adapter, a variable-frequency bus adapting method and a variable-frequency bus adapting system are provided. The method includes: generating a bus blocking indication according to a dynamic frequency scaling (DFS) request signal sent by a bus side; blocking a current bus transfer according to the bus blocking indication; and feeding back a DFS response signal to the bus side after blocking the current bus transfer, where the DFS response signal is adapted to enable the bus side to perform a DFS operation. In the method, the bus transfer is temporarily blocked during the DFS, so that undesired influence on peripheral components caused by unstable bus block during the bus DFS is reduced without increasing the number of clock domains of the system or modifying the peripheral components, thus reducing the complexity of the implementation of the system, and improving the applicability of dynamic voltage frequency scaling (DVFS).
摘要翻译：提供了可变频率总线适配器，可变频率总线适配方法和可变频率总线适配系统。该方法包括：根据由总线端发送的动态频率缩放（DFS）请求信号产生总线阻塞指示; 根据总线阻塞指示阻止当前总线传输; 并且在阻止当前总线传输之后将DFS响应信号反馈给总线侧，其中DFS响应信号适于使总线端执行DFS操作。在该方法中，在DFS期间暂时阻塞总线传输，从而在不增加系统的时钟域数量或修改外围组件的情况下减少总线DFS期间由不稳定总线块引起的对外围组件的不良影响，从而减少实现系统的复杂性，并提高动态电压频率缩放（DVFS）的适用性。

2. 发明申请

US20110179207A1 VARIABLE-FREQUENCY BUS ADAPTER, ADAPTING METHOD AND SYSTEM 有权
标题翻译：可变频率总线适配器，适配方法和系统
公开(公告)号：US20110179207A1
公开(公告)日：2011-07-21
申请号：US13007332
申请日：2011-01-14
申请人： Cong Yao , Qiwei Liu , Yu Liu , Xiang Li , Liqian Chen , Shiming He , Jiayin Lu
发明人： Cong Yao , Qiwei Liu , Yu Liu , Xiang Li , Liqian Chen , Shiming He , Jiayin Lu
IPC分类号： G06F13/14
CPC分类号： G06F13/382
摘要： A variable-frequency bus adapter, a variable-frequency bus adapting method and a variable-frequency bus adapting system are provided. The method includes: generating a bus blocking indication according to a dynamic frequency scaling (DFS) request signal sent by a bus side; blocking a current bus transfer according to the bus blocking indication; and feeding back a DFS response signal to the bus side after blocking the current bus transfer, where the DFS response signal is adapted to enable the bus side to perform a DFS operation. In the method, the bus transfer is temporarily blocked during the DFS, so that undesired influence on peripheral components caused by unstable bus block during the bus DFS is reduced without increasing the number of clock domains of the system or modifying the peripheral components, thus reducing the complexity of the implementation of the system, and improving the applicability of dynamic voltage frequency scaling (DVFS).
摘要翻译：提供了可变频率总线适配器，可变频率总线适配方法和可变频率总线适配系统。该方法包括：根据由总线端发送的动态频率缩放（DFS）请求信号产生总线阻塞指示; 根据总线阻塞指示阻止当前总线传输; 并且在阻止当前总线传输之后将DFS响应信号反馈给总线侧，其中DFS响应信号适于使总线端执行DFS操作。在该方法中，在DFS期间暂时阻塞总线传输，从而在不增加系统的时钟域数量或修改外围组件的情况下减少总线DFS期间由不稳定总线块引起的对外围组件的不良影响，从而减少实现系统的复杂性，并提高动态电压频率缩放（DVFS）的适用性。

3. 发明授权

US08570087B2 Circuitry for clock and method for providing clock signal 有权
标题翻译：时钟电路和提供时钟信号的方法
公开(公告)号：US08570087B2
公开(公告)日：2013-10-29
申请号：US13311069
申请日：2011-12-05
申请人： Shiming He , Liqian Chen , Cong Yao , Xiang Li , Yu Liu , Jiayin Lu
发明人： Shiming He , Liqian Chen , Cong Yao , Xiang Li , Yu Liu , Jiayin Lu
IPC分类号： H03K3/00
CPC分类号： H03L7/0997
摘要： The present invention provide a clock circuit and a method for providing a clock signal. The clock circuit includes: an adaptive clock generation circuit, configured to output an adaptive clock signal; and an adaptive clock driven circuit, configured to be driven by the adaptive clock signal to work. A maximum workable frequency of the adaptive clock driven circuit is higher than or equal to a frequency of the adaptive clock signal. When a working condition of the adaptive clock driven circuit is changed, the maximum workable frequency of the adaptive clock driven circuit is changed, the frequency of the adaptive clock signal which is output by the adaptive clock generation circuit is changed, and a changing direction of the frequency of an adaptive clock signal is consistent with that of the maximum workable frequency. The clock circuit and method may be used in design or manufacturing of a digital circuit.
摘要翻译：本发明提供一种提供时钟信号的时钟电路和方法。时钟电路包括：自适应时钟产生电路，被配置为输出自适应时钟信号; 以及自适应时钟驱动电路，被配置为由自适应时钟信号驱动工作。自适应时钟驱动电路的最大可工作频率高于或等于自适应时钟信号的频率。当自适应时钟驱动电路的工作状态改变时，自适应时钟驱动电路的最大可工作频率改变，由自适应时钟发生电路输出的自适应时钟信号的频率改变，并且改变方向自适应时钟信号的频率与最大可工作频率的频率一致。时钟电路和方法可用于数字电路的设计或制造。

4. 发明申请

US20120139596A1 CIRCUITRY FOR CLOCK AND METHOD FOR PROVIDING CLOCK SIGNAL 有权
标题翻译：用于提供时钟信号的时钟和方法的电路
公开(公告)号：US20120139596A1
公开(公告)日：2012-06-07
申请号：US13311069
申请日：2011-12-05
申请人： Shiming He , Liqian Chen , Cong Yao , Xiang Li , Yu Liu , Jiayin Lu
发明人： Shiming He , Liqian Chen , Cong Yao , Xiang Li , Yu Liu , Jiayin Lu
IPC分类号： H03L7/085
CPC分类号： H03L7/0997
摘要： The present invention provide a clock circuit and a method for providing a clock signal. The clock circuit includes: an adaptive clock generation circuit, configured to output an adaptive clock signal; and an adaptive clock driven circuit, configured to be driven by the adaptive clock signal to work. A maximum workable frequency of the adaptive clock driven circuit is higher than or equal to a frequency of the adaptive clock signal. When a working condition of the adaptive clock driven circuit is changed, the maximum workable frequency of the adaptive clock driven circuit is changed, the frequency of the adaptive clock signal which is output by the adaptive clock generation circuit is changed, and a changing direction of the frequency of an adaptive clock signal is consistent with that of the maximum workable frequency. The clock circuit and method may be used in design or manufacturing of a digital circuit.
摘要翻译：本发明提供一种提供时钟信号的时钟电路和方法。时钟电路包括：自适应时钟产生电路，被配置为输出自适应时钟信号; 以及自适应时钟驱动电路，被配置为由自适应时钟信号驱动工作。自适应时钟驱动电路的最大可工作频率高于或等于自适应时钟信号的频率。当自适应时钟驱动电路的工作状态改变时，自适应时钟驱动电路的最大可工作频率改变，由自适应时钟发生电路输出的自适应时钟信号的频率改变，并且改变方向自适应时钟信号的频率与最大可工作频率的频率一致。时钟电路和方法可用于数字电路的设计或制造。

5. 发明申请

US20100241885A1 Method, system and apparatus for controlling power consumption of embedded system 审中-公开
标题翻译：用于控制嵌入式系统功耗的方法，系统和设备
公开(公告)号：US20100241885A1
公开(公告)日：2010-09-23
申请号：US12725281
申请日：2010-03-16
申请人： Shiming He , Yu Liu , Cong Yao , Xiang Li , Liqian Chen , Jiayin Lu
发明人： Shiming He , Yu Liu , Cong Yao , Xiang Li , Liqian Chen , Jiayin Lu
IPC分类号： G06F1/30 , G06F13/24
CPC分类号： G06F1/3203 , G06F1/3215 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Embodiments of the present disclosure disclose a method for controlling power consumption of an embedded system. The method obtains a data transmission index that is between a bus module and a bus, compares the obtained data transmission index with a preset numeric value range, and adjusts an operation frequency or an operation voltage of the bus module when the data transmission index exceeds the preset numeric value range. Embodiments of the present disclosure further provide a system and a relevant apparatus for controlling power consumption of the embedded system. In comparison with the conventional art, embodiments of the present disclosure effectively monitor the load of the bus module, and adjust the operation parameters of the module according to the monitoring result to enable the module to operate under proper operation parameters and to thereby reduce unnecessary power consumption.
摘要翻译：本公开的实施例公开了一种用于控制嵌入式系统的功耗的方法。该方法获得总线模块和总线之间的数据传输索引，将获得的数据传输指数与预设数值范围进行比较，并且当数据传输指数超过总线模块时调整总线模块的工作频率或工作电压预设数值范围。本公开的实施例还提供了一种用于控制嵌入式系统的功耗的系统和相关装置。与传统技术相比，本公开的实施例有效地监视总线模块的负载，并且根据监视结果调整模块的操作参数，以使模块能够在适当的操作参数下操作，从而减少不必要的功率消费。

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