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1. 发明授权

US5699541A Memory system using schottky diodes to reduce load capacitance 失效
标题翻译：使用肖特基二极管降低负载电容的存储系统
公开(公告)号：US5699541A
公开(公告)日：1997-12-16
申请号：US406147
申请日：1995-03-20
申请人： Kenichi Kurosawa , Shin Kokura , Michio Morioka , Tetsuaki Nakamikawa , Sakou Ishikawa
发明人： Kenichi Kurosawa , Shin Kokura , Michio Morioka , Tetsuaki Nakamikawa , Sakou Ishikawa
IPC分类号： G11C11/417 , G06F13/16 , G11C7/10 , G11C11/409 , G06F12/00 , G06F9/26 , G06F9/32 , G06F12/02
CPC分类号： G11C7/1051 , G11C7/1078
摘要： A computer memory system is disclosed with an input/output circuitry capable of separating the load separating the load capacitance of an output circuit of a semiconductor memory connected to a memory bus from the memory bus. In order to separate the load capacitance of a semiconductor memory connected to a memory bus signal line, a Schottky diode is arranged between the semiconductor memory and the memory bus line, and a voltage control circuit is provided to control whether a reverse bias voltage is applied to the Schottky diode. The speed of signal transmission does not decrease even when a large number of semiconductor memories are connected to the memory bus since the load capacitance of the semiconductor memories is separated from the bus. Therefore, it is possible to construct a high speed and large capacity memory system.
摘要翻译：公开了具有输入/输出电路的计算机存储器系统，该输入/输出电路能够将连接到存储器总线的半导体存储器的输出电路的负载电容与存储器总线分开。为了分离连接到存储器总线信号线的半导体存储器的负载电容，在半导体存储器和存储器总线之间布置肖特基二极管，并且提供电压控制电路以控制是否施加反向偏置电压到肖特基二极管。即使当半导体存储器的负载电容与总线分离时，即使大量的半导体存储器连接到存储器总线，信号传输的速度也不会降低。因此，可以构建高速，大容量的存储系统。

2. 发明授权

US5841963A Dual information processing system having a plurality of data transfer channels 失效
标题翻译：双信息处理系统具有多个数据传输通道
公开(公告)号：US5841963A
公开(公告)日：1998-11-24
申请号：US861471
申请日：1997-05-21
申请人： Tetsuaki Nakamikawa , Shin Kokura , Kenichi Kurosawa , Shinichiro Yamaguchi , Yoshihiro Miyazaki , Hiroshi Ohguro
发明人： Tetsuaki Nakamikawa , Shin Kokura , Kenichi Kurosawa , Shinichiro Yamaguchi , Yoshihiro Miyazaki , Hiroshi Ohguro
IPC分类号： G06F11/16 , G06F15/17
CPC分类号： G06F11/1658
摘要： A dual computer system consisting of two computer systems connected by a plurality of data transfer units and a plurality of data transfer channels for a memory copy made to again synchronize both the computer systems at the time of recovery from a fault. When no fault occurs on the data transfer channels, the data transfer units share the load of data transfer in the memory copy operation, and when a fault occurs on any data transfer unit during the memory copy operation, the remaining normal data transfer units are used to again transfer data, whereby a memory copy is made at high speed for again synchronizing both the computer systems at the time of recovery from a fault, and system reliability at the time of recovery from a fault is improved.
摘要翻译：由由多个数据传送单元连接的两个计算机系统和用于存储器副本的多个数据传送通道组成的双计算机系统，使得在从故障恢复时再次同步计算机系统。当数据传输通道没有发生故障时，数据传输单元在存储器复制操作中共享数据传输的负载，并且当在存储器复制操作期间在任何数据传送单元发生故障时，使用剩余的正常数据传送单元再次传送数据，从而高速地进行存储器复制，以便在从故障恢复时再次同步计算机系统，并且提高从故障恢复时的系统可靠性。

3. 发明授权

US06453391B2 Multiplexed computer system 失效
标题翻译：多路复用计算机系统
公开(公告)号：US06453391B2
公开(公告)日：2002-09-17
申请号：US09882258
申请日：2001-06-18
申请人： Yuuichiro Morita , Tetsuaki Nakamikawa , Shinichiro Yamaguchi , Naoto Miyazaki , Shin Kokura , Yoshihiro Miyazaki
发明人： Yuuichiro Morita , Tetsuaki Nakamikawa , Shinichiro Yamaguchi , Naoto Miyazaki , Shin Kokura , Yoshihiro Miyazaki
IPC分类号： G06F1200
CPC分类号： G06F11/1658 , G06F11/2028 , G06F11/2035 , G06F11/2043 , G06F11/2097 , G06F12/0804
摘要： A multiplexed computer system allows memory accessing by a processor, a peripheral equipment or a like apparatus even during execution of memory copying to improve the processing performance during on-line maintenance. To this end, the multiplexed computer system includes a plurality of processing units which effect the same operation in synchronism with each other. Each of the processing units includes a copy processor register for designating a processor to read out contents of a memory unit, a memory copy control unit for transferring copies of the stored contents of the memory unit and data to be written into the memory unit in the same order as that of accesses to the memory unit of the other processing unit, a copy mode flag indicating that memory copy processing for making the stored contents of the memory unit of the self system and stored contents of the memory unit of the other processing unit coincide with each other is proceeding, and a copy task flag indicating that the processor is reading out, during memory copying processing, the stored contents of the memory unit.
摘要翻译：复用的计算机系统即使在执行存储器复制期间也允许由处理器，外围设备或类似设备进行的存储器访问，以提高在线维护期间的处理性能。为此，多路复用的计算机系统包括多个处理单元，其相互同步地进行相同的操作。每个处理单元包括用于指定处理器以读取存储器单元的内容的复制处理器寄存器，用于将存储器单元的存储内容的副本和要写入的存储器单元的副本传送到存储器单元的存储器复制控制单元与对其他处理单元的存储单元的访问相同的顺序，指示用于使自身系统的存储单元的存储内容和其他处理单元的存储单元的存储内容的存储器复制处理的复制模式标志并且在存储器复制处理期间指示处理器正在读出存储单元的存储内容的复制任务标志。

4. 发明授权

US6003116A Multiplexed computer system with the capability to copy data from one processor memory to another 失效
标题翻译：具有将数据从一个处理器存储器复制到另一个处理器的能力的多路复用计算机系统
公开(公告)号：US6003116A
公开(公告)日：1999-12-14
申请号：US739393
申请日：1996-10-29
申请人： Yuuichiro Morita , Tetsuaki Nakamikawa , Shinichiro Yamaguchi , Naoto Miyazaki , Shin Kokura , Yoshihiro Miyazaki
发明人： Yuuichiro Morita , Tetsuaki Nakamikawa , Shinichiro Yamaguchi , Naoto Miyazaki , Shin Kokura , Yoshihiro Miyazaki
IPC分类号： G06F11/18 , G06F11/20 , G06F12/08 , G06F15/16 , G06F15/177 , G06F12/00 , G06F13/00
CPC分类号： G06F11/1658 , G06F12/0804 , G06F11/2028 , G06F11/2035 , G06F11/2043 , G06F11/2097
摘要： A multiplexed computer system allows memory accessing by a processor, a peripheral equipment or a like apparatus even during execution of memory copying to improve the processing performance during on-line maintenance. To this end, the multiplexed computer system includes a plurality of processing units which carry out the same operation in synchronism with each other. Each of the processing units includes a copy processor register for designating a processor to read out contents of a memory unit, copying circuits which transfer copies of the stored contents of the memory unit and data to be written into the memory unit in the same order as that of accesses to the memory unit to a memory unit of another processing unit, a copy mode flag indicating that memory copying processing for making the stored contents of the memory unit of the self system and stored contents of the memory unit of the other processing unit coincide with each other is proceeding, and a copy task flag indicating that the processor is reading out, during memory copying processing, the stored contents of the memory unit.
摘要翻译：复用的计算机系统即使在执行存储器复制期间也允许由处理器，外围设备或类似设备进行的存储器访问，以提高在线维护期间的处理性能。为此，复用的计算机系统包括多个处理单元，它们彼此同步地执行相同的操作。每个处理单元包括一个复制处理器寄存器，用于指定一个处理器来读取存储器单元的内容，复制电路，将存储单元的存储内容的副本和要写入存储单元的数据按照与对存储器单元访问另一处理单元的存储器单元的复制模式标志，指示用于使自身系统的存储单元的存储内容存储的存储器复制处理和另一处理单元的存储单元的存储的复制模式标志并且在存储器复制处理期间指示处理器正在读出存储单元的存储内容的复制任务标志。

5. 发明授权

US07873871B2 Communication control system and communication control method 有权
标题翻译：通讯控制系统及通讯控制方法
公开(公告)号：US07873871B2
公开(公告)日：2011-01-18
申请号：US11768241
申请日：2007-06-26
申请人： Masakazu Ishikawa , Akira Bandou , Masahiro Shiraishi , Masamitsu Kobayashi , Yasuyuki Furuta , Akihiro Onozuka , Shin Kokura , Eiji Kobayashi , Satoru Funaki , Takashi Umehara , Naoya Mashiko , Yuusuke Seki , Tatsuyuki Ootani
发明人： Masakazu Ishikawa , Akira Bandou , Masahiro Shiraishi , Masamitsu Kobayashi , Yasuyuki Furuta , Akihiro Onozuka , Shin Kokura , Eiji Kobayashi , Satoru Funaki , Takashi Umehara , Naoya Mashiko , Yuusuke Seki , Tatsuyuki Ootani
IPC分类号： G06F11/00
CPC分类号： G05B23/0229 , G05B23/0262
摘要： A programmable electronic controller in which one central arithmetic processing unit and a plurality of input devices and output devices are connected by means of a parallel bus, the controller being basically configured to activate a self-diagnostic function and a diagnostic test of the input devices and the output devices with an instruction from a microprocessor of the central arithmetic processing unit; and to judge the result with the microprocessor of the central arithmetic processing unit, by using the microprocessor installed in the central arithmetic processing unit also as a processor for tests (diagnostic tests) of the self-diagnostic function of the input devices and output devices and conducting tests of the self-diagnostic function of the plurality of input devices and output devices with the central arithmetic processing unit.
摘要翻译：一种可编程电子控制器，其中一个中央算术处理单元和多个输入设备和输出设备通过并行总线连接，所述控制器基本上被配置为激活输入设备的自诊断功能和诊断测试，所述输出装置具有来自所述中央算术处理单元的微处理器的指令; 并且通过使用安装在中央算术处理单元中的微处理器作为输入设备和输出设备的自诊断功能的测试（诊断测试）的处理器来判断结果与中央算术处理单元的微处理器，以及利用中央算术处理单元对多个输入装置和输出装置进行自诊断功能的测试。

6. 发明授权

US07555627B2 Input-output control apparatus, input-output control method, process control apparatus and process control method 有权
标题翻译：输入输出控制装置，输入输出控制方法，过程控制装置和过程控制方法
公开(公告)号：US07555627B2
公开(公告)日：2009-06-30
申请号：US11477468
申请日：2006-06-30
申请人： Naoya Mashiko , Takashi Umehara , Masamitsu Kobayashi , Hiromichi Endoh , Akihiro Onozuka , Akira Bando , Shin Kokura , Hisao Nagayama , Masakazu Ishikawa , Satoru Funaki , Masahiro Shiraishi
发明人： Naoya Mashiko , Takashi Umehara , Masamitsu Kobayashi , Hiromichi Endoh , Akihiro Onozuka , Akira Bando , Shin Kokura , Hisao Nagayama , Masakazu Ishikawa , Satoru Funaki , Masahiro Shiraishi
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F13/122 , Y02P90/14
摘要： Input-output devices are prevented from conducting false output due to faulty operation by providing an input-output control apparatus configured to store input-output values to be used by a processor to conduct arithmetic operation in a mode having a relatively high safety requirement, in a first storage area, store input-output values to be used by the processor to conduct arithmetic operation in a mode having a relatively low safety requirement, in a second storage area, and restrict copying to the first storage area, copying from the first storage area, copying to the second storage area, or copying from the second storage area according to the mode concerning the safety requirement.
摘要翻译：通过提供输入输出控制装置，通过提供输入输出控制装置来防止输入输出装置由于处理器使用的输入输出值，以便以具有较高安全性要求的模式进行算术运算第一存储区域，存储由处理器在具有相对较低安全性要求的模式下进行算术运算的输入输出值，并将其限制在第一存储区域中，并将复制从第一存储区域区域，复制到第二存储区域，或者根据关于安全性要求的模式从第二存储区域进行复制。

7. 发明授权

US09208037B2 Duplexed operation processor control system, and duplexed operation processor control method 有权
公开(公告)号：US09208037B2
公开(公告)日：2015-12-08
申请号：US12457682
申请日：2009-06-18
申请人： Toshiki Shimizu , Akira Bando , Yusaku Otsuka , Yasuhiro Kiyofuji , Eiji Kobayashi , Akihiro Onozuka , Satoru Funaki , Masakazu Ishikawa , Hideaki Masuko , Yusuke Seki , Wataru Sasaki , Naoya Mashiko , Akihiro Nakano , Shin Kokura , Shoichi Ozawa , Yu Iwasaki
发明人： Toshiki Shimizu , Akira Bando , Yusaku Otsuka , Yasuhiro Kiyofuji , Eiji Kobayashi , Akihiro Onozuka , Satoru Funaki , Masakazu Ishikawa , Hideaki Masuko , Yusuke Seki , Wataru Sasaki , Naoya Mashiko , Akihiro Nakano , Shin Kokura , Shoichi Ozawa , Yu Iwasaki
IPC分类号： G06F11/20 , G06F11/16 , G06F9/445
CPC分类号： G06F11/2033 , G06F8/656 , G06F11/1658 , G06F11/2028 , G06F11/2038 , G06F11/2097
摘要： The present invention provides a duplexed operation processor control system that includes operation processors, an I/O device, and at least one communication path that couples the operation processors to the I/O device, and at least one communication path that couples the operation processors with each other. The duplexed operation processor control system switches over either of the operation processors to be a primary operation processor that executes a control operation for a control target, and the other to be a secondary operation processor that is in a stand-by state, and the secondary operation processor snoops control data synchronously when the primary operation processor acquires the control data from the control target.

8. 发明授权

US08493927B2 Control apparatus, control method and control program 有权
标题翻译：控制装置，控制方法及控制程序
公开(公告)号：US08493927B2
公开(公告)日：2013-07-23
申请号：US11769862
申请日：2007-06-28
申请人： Akira Bandou , Masamitsu Kobayashi , Masahiro Shiraishi , Akihiro Onozuka , Takashi Umehara , Shin Kokura , Eiji Kobayashi , Masakazu Ishikawa , Yasuyuki Furuta , Naoya Mashiko , Satoru Funaki , Yuusuke Seki , Tatsuyuki Ootani , Wataru Sasaki , Yusaku Otsuka , Akihiro Nakano , Shoichi Ozawa , Takenori Kasahara , Yu Iwasaki
发明人： Akira Bandou , Masamitsu Kobayashi , Masahiro Shiraishi , Akihiro Onozuka , Takashi Umehara , Shin Kokura , Eiji Kobayashi , Masakazu Ishikawa , Yasuyuki Furuta , Naoya Mashiko , Satoru Funaki , Yuusuke Seki , Tatsuyuki Ootani , Wataru Sasaki , Yusaku Otsuka , Akihiro Nakano , Shoichi Ozawa , Takenori Kasahara , Yu Iwasaki
IPC分类号： H04B7/212
CPC分类号： G05B9/02
摘要： In a control apparatus which transmits/receives data from a central processing unit via a serial transfer channel to a communication control unit, and groups/distributes data of input/output units from the communication control unit via a parallel transfer channel, the control apparatus initiates a diagnosing unit of the parallel transfer channel in response to an instruction issued from the central processing unit, and diagnosis the input/output units subsequent to the diagnosis of the transmission channel. Data input/output timing of the input/output unit is also instructed from the central processing unit, so that the central processing unit can suppress lowering of response speeds caused by the diagnoses, and can maintain the periodicity of the data input/output.
摘要翻译：在通过串行传送信道向通信控制单元从中央处理单元发送/接收数据的控制装置中，通过并行传送信道对来自通信控制单元的输入/输出单元的数据进行分组/分配时，控制装置启动响应于从中央处理单元发出的指令，并行传输信道的诊断单元，并且诊断传输信道诊断之后的输入/输出单元。还从中央处理单元指示输入/输出单元的数据输入/输出定时，使得中央处理单元可以抑制由诊断引起的响应速度的降低，并且可以保持数据输入/输出的周期性。

9. 发明授权

US08255769B2 Control apparatus and control method 有权
标题翻译：控制装置及控制方法
公开(公告)号：US08255769B2
公开(公告)日：2012-08-28
申请号：US12652773
申请日：2010-01-06
申请人： Satoru Funaki , Yasuhiro Kiyofuji , Masashi Suenaga , Shin Kokura , Eiji Kobayashi , Akihiro Onozuka , Yusuke Seki , Toshiki Shimizu , Yukiko Tahara , Yuta Sugimoto
发明人： Satoru Funaki , Yasuhiro Kiyofuji , Masashi Suenaga , Shin Kokura , Eiji Kobayashi , Akihiro Onozuka , Yusuke Seki , Toshiki Shimizu , Yukiko Tahara , Yuta Sugimoto
IPC分类号： G11C29/00
CPC分类号： G06F11/1008 , H03M13/09
摘要： A failure is detected immediately and certainly, and continuation of processing in an unstable state is prevented. A first error detection code is generated from first information which is output as a result of execution of a predetermined program conducted by a first processor. A second error detection code is generated from second information which is output as a result of execution of the program conducted by a second processor which is configured so as to output the same computation result as that of the first processor. It is detected whether the first information is the same as the second information, and it is detected whether the first error detection code is the same as the second error detection code. Writing the first information or the second information into a main memory is controlled on the basis of a result of the detection.
摘要翻译：立即且肯定地检测到故障，并且防止处于不稳定状态的处理的继续。作为执行由第一处理器执行的预定程序的结果而输出的第一信息产生第一错误检测码。从作为由第二处理器执行的程序的执行结果输出的第二信息生成第二错误检测码，该第二处理器被配置为输出与第一处理器相同的计算结果。检测第一信息是否与第二信息相同，并且检测第一错误检测码是否与第二错误检测码相同。基于检测结果来控制将第一信息或第二信息写入主存储器。

10. 发明申请

US20070006025A1 Sending device, receiving device, communication control device, communication system, and communication control method 审中-公开
标题翻译：发送装置，接收装置，通信控制装置，通信系统和通信控制方法
公开(公告)号：US20070006025A1
公开(公告)日：2007-01-04
申请号：US11477440
申请日：2006-06-30
申请人： Akihiro Onozuka , Masakazu Ishikawa , Masamitsu Kobayashi , Takashi Umehara , Shin Kokura , Hiromichi Endoh , Satoru Funaki , Hisao Nagayama , Masahiro Shiraishi , Akira Bando , Eiji Kobayashi , Yasuyuki Furuta , Naoya Mashiko
发明人： Akihiro Onozuka , Masakazu Ishikawa , Masamitsu Kobayashi , Takashi Umehara , Shin Kokura , Hiromichi Endoh , Satoru Funaki , Hisao Nagayama , Masahiro Shiraishi , Akira Bando , Eiji Kobayashi , Yasuyuki Furuta , Naoya Mashiko
IPC分类号： G06F11/00
CPC分类号： H04L1/0046
摘要： The system has, provided in a sending device, a generator generating transmission data including data, a data error detection code generated from the data and a safety flag indicating a degree of reliability, and transmission data; has, provided in a receiving device, a plurality of components of extracting transmission data, a safety flag, and a data error detection code from a received frame, and detecting a data error, a comparator comparing the matching of a plurality of received frames, and a selector selecting one received frame, from the frame error detection result, the safety flag, the data error detection result, and the matching comparison result; and determines the validity of transmitted data by the detection corresponding to the degree of reliability set with the safety flag.
摘要翻译：该系统在发送装置中具有生成包括数据的发送数据的发生器，从数据生成的数据错误检测码和表示可靠度的安全标志，以及发送数据; 在接收装置中具有从接收到的帧中提取发送数据，安全标志和数据错误检测码的多个组件，并且检测数据错误，比较多个接收帧的匹配的比较器，以及从帧错误检测结果，安全标志，数据错误检测结果和匹配比较结果中选择一个接收帧的选择器; 并通过与利用安全标志设定的可靠度相对应的检测来确定发送数据的有效性。

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