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1. 发明授权

US06623804B1 Melting and impregnating apparatus method of manufacturing linear composite material and linear composite material 有权
标题翻译：熔融浸渍设备制造线性复合材料和线性复合材料的方法
公开(公告)号：US06623804B1
公开(公告)日：2003-09-23
申请号：US09667305
申请日：2000-09-25
申请人： Kenichi Kawaguchi , Hitoshi Ushijima , Takeshi Kamata
发明人： Kenichi Kawaguchi , Hitoshi Ushijima , Takeshi Kamata
IPC分类号： B05D118
CPC分类号： D01D11/06 , C23C2/006
摘要： A melting and impregnating apparatus includes an impregnating tank having an inlet sealing portion in the bottom portion thereof, an outlet sealing portion in the upper portion thereof and a drawing portion disposed between the sealing portions; a raw-material heating tank allowed to communicate with the impregnating tank through a heating passage; and pressurizing means for maintaining pressurized states of the inside portions of the impregnating tank and the pressurizing means.
摘要翻译：熔融浸渍装置包括：浸渍槽，其底部具有入口密封部分，其上部具有出口密封部分和设置在密封部分之间的拉伸部分; 允许原料加热槽通过加热通道与浸渍槽连通; 以及用于保持浸渍罐和加压装置的内部的加压状态的加压装置。

2. 发明授权

US07823142B2 Processor for executing instructions in units that are unrelated to the units in which instructions are read, and a compiler, an optimization apparatus, an assembler, a linker, a debugger and a disassembler for such processor 有权
标题翻译：用于以与读取指令的单位无关的单元执行指令的处理器，以及用于这种处理器的编译器，优化装置，汇编器，链接器，调试器和反汇编器
公开(公告)号：US07823142B2
公开(公告)日：2010-10-26
申请号：US11245357
申请日：2005-10-07
申请人： Shuichi Takayama , Hajime Ogawa , Kenichi Kawaguchi , Nobuo Higaki , Kensuke Odani , Tetsuya Tanaka , Shinya Miyaji , Taketo Heishi
发明人： Shuichi Takayama , Hajime Ogawa , Kenichi Kawaguchi , Nobuo Higaki , Kensuke Odani , Tetsuya Tanaka , Shinya Miyaji , Taketo Heishi
IPC分类号： G06F9/45
CPC分类号： G06F9/3802 , G06F9/30149 , G06F9/30152 , G06F9/30167 , G06F9/321 , G06F9/322 , G06F9/324 , G06F9/3822 , G06F9/3853
摘要： When a branch instruction is decoded by the instruction decoders 409a˜409c, the upper 29 bits of the PC relative value included in the branch instruction are sent to the upper PC calculator 411 and the lower 3 bits are sent to the lower PC calculator 405. The lower PC calculator 405 adds the lower 3 bits of the PC relative value and the lower 3 bits of the present lower PC 404 and sends the result to the lower PC 404 as the updated lower PC. The upper PC calculator 411 adds the upper 29 bits of the PC relative value, the upper 29 bits of the present upper PC 403, and a carry that may be received from the lower PC calculator 405, and sends the result to the upper PC 403 as the updated upper PC.
摘要翻译：当指令解码器409a至409c解码分支指令时，分支指令中包括的PC相对值的高29位被发送到上位PC计算器411，低3位被发送到下PC计算器405。下PC计算器405将PC相对值的低3位和当前下PC404的低3位相加，并将结果作为更新的下级PC发送到下PC404。上PC计算器411将PC相对值的上29位，当前上位机403的上位29加上可从下PC计算器405接收的进位，并将结果发送到上PC403 作为更新的上位机。

3. 发明申请

US20100090196A1 Optical semiconductor device and manufacturing method of the same 有权
标题翻译：光半导体器件及其制造方法
公开(公告)号：US20100090196A1
公开(公告)日：2010-04-15
申请号：US12654016
申请日：2009-12-08
申请人： Nami Yasuoka , Kenichi Kawaguchi
发明人： Nami Yasuoka , Kenichi Kawaguchi
IPC分类号： H01L29/66
CPC分类号： H01L31/18 , B82Y20/00 , H01L31/0352 , H01L31/035236
摘要： A side barrier is provided between columnar dots each constituted by directly stacking respective quantum dots in seven or more layers. Out of respective side barrier layers composing the side barrier, each of the lower side barrier layers (four layers of the undermost layer to the fourth layer from the bottom) is formed as a first side barrier layer into which a tensile strain is introduced, and each of the upper side barrier layers (three layers of the fifth Layer to the uppermost layer from the bottom) is formed as a second side barrier layer which has no strain.
摘要翻译：在通过以7层或更多层直接层叠各量子点构成的柱状点之间设置有侧壁。在构成侧壁的各个侧壁阻挡层中，形成作为施加拉伸应变的第一侧阻挡层，下侧阻挡层（从底部的最下层到第四层的四层）每个上侧阻挡层（从第五层到底层的最上层三层）被形成为没有应变的第二侧阻挡层。

4. 发明授权

US07685353B2 Data transfer apparatus with control of buses to optimize different size data transfers 有权
标题翻译：数据传输设备，可控制总线，优化不同大小的数据传输
公开(公告)号：US07685353B2
公开(公告)日：2010-03-23
申请号：US12390198
申请日：2009-02-20
申请人： Kenichi Kawaguchi
发明人： Kenichi Kawaguchi
IPC分类号： G06F13/36
CPC分类号： G06F13/4027 , G06F13/4031 , G06F13/4059 , G06F13/423 , G06F2213/0024
摘要： A bus bridge is connected to a primary bus and a secondary bus, and relays data between a master and a target which are each connected to a different one of the primary and secondary buses. The bus bridge includes a primary bus interface, a secondary bus interface, a data FIFO, and a register block. The register block, which can be written by the master, includes two registers corresponding to the primary and secondary buses. Relay information showing the number of entries of data to be relayed from the target to the master is registered in a register corresponding to a bus to which the target is connected. In a read transaction, the primary bus interface or the secondary bus interface reads data from the target until data of the amount shown by the registered relay information is stored in the data FIFO.
摘要翻译：总线桥连接到主总线和辅助总线，并且中继主机和目标之间的数据，每个主站和目标站之间连接到主总线和次总线之间的不同的总线。总线桥包括主总线接口，辅助总线接口，数据FIFO和寄存器块。可由主器件写入的寄存器块包括与主母线和辅助母线相对应的两个寄存器。显示要从目标到主机中继的数据的条目数的中继信息被登记在对应于目标连接到的总线的寄存器中。在读取事务中，主总线接口或辅助总线接口从目标读取数据，直到被注册的中继信息所示量的数据被存储在数据FIFO中。

5. 发明授权

US07313642B2 Bus bridge arbitration method 有权
标题翻译：总线桥仲裁方法
公开(公告)号：US07313642B2
公开(公告)日：2007-12-25
申请号：US10391167
申请日：2003-03-18
申请人： Kenichi Kawaguchi
发明人： Kenichi Kawaguchi
IPC分类号： G06F13/36
CPC分类号： G06F13/4031
摘要： A bus bridge is connected to a first bus and a second bus. In the bus bridge, an arbiter grants ownership of the first bus to one of a plurality of devices connected to the first bus. A detecting unit detects a read cycle initiated by the device on the first bus to read data from a memory which is also accessible by another device connected to the second bus. A first signaling unit sends a first signal to the arbiter, when the data is not yet transferable to the device when the read cycle is detected. A second signaling unit sends a second signal to the arbiter, when the data becomes transferable to the device. The arbiter deprives the device of the ownership of the first bus upon receipt of the first signal, and withholds from granting the ownership to the device until receipt of the second signal.
摘要翻译：总线桥连接到第一总线和第二总线。在总线桥中，仲裁者将第一总线的所有权授予连接到第一总线的多个设备之一。检测单元检测由第一总线上的设备发起的读周期，以从存储器读取数据，该存储器也可由连接到第二总线的另一设备访问。当检测到读取周期时，当数据不能传输到设备时，第一信令单元向仲裁器发送第一信号。当数据可转移到设备时，第二信令单元向仲裁器发送第二信号。仲裁者在收到第一个信号后，剥夺了第一个公共汽车的所有权，并将所有权授予设备，直到收到第二个信号。

6. 发明授权

US07297698B2 N-phenyl-(2R,5S) dimethylpiperazine derivative 有权
标题翻译： N-苯基 - （2R，5S）二甲基哌嗪衍生物
公开(公告)号：US07297698B2
公开(公告)日：2007-11-20
申请号：US10521119
申请日：2003-07-11
申请人： Nobuaki Taniguchi , Masakazu Imamura , Masahiko Hayakawa , Kenichi Kawaguchi , Takenori Kimura , Isao Kinoyama , Hiroyuki Kaizawa , Minoru Okada , Takashi Furutani
发明人： Nobuaki Taniguchi , Masakazu Imamura , Masahiko Hayakawa , Kenichi Kawaguchi , Takenori Kimura , Isao Kinoyama , Hiroyuki Kaizawa , Minoru Okada , Takashi Furutani
IPC分类号： A61K31/4965 , C07D403/00
CPC分类号： C07D213/75 , C07D213/84 , C07D239/42 , C07D295/215
摘要： The present invention relates to a novel N-phenyl-(2R,5S)dimethylpiperazine derivatives useful as antiandrogenic agent which exhibits a sufficient prostate gland reducing effect as compared with conventional compounds and are excellent in oral activity. The compound of the present application is useful in preventing or treating prostate cancer, benign prostatic hyperplasia, and the like. The present invention also provides a novel intermediate useful in producing the compound of the present invention.
摘要翻译：本发明涉及用作抗雄激素剂的新型N-苯基 - （2R，5S）二甲基哌嗪衍生物，其与常规化合物相比表现出足够的前列腺减少效果，口服活性优异。本申请的化合物可用于预防或治疗前列腺癌，良性前列腺增生等。本发明还提供了可用于制备本发明化合物的新型中间体。

7. 发明授权

US07185137B2 Bus bridge with stored controlling relay information 有权
标题翻译：具有存储控制继电器信息的总线桥
公开(公告)号：US07185137B2
公开(公告)日：2007-02-27
申请号：US11209511
申请日：2005-08-23
申请人： Kenichi Kawaguchi
发明人： Kenichi Kawaguchi
IPC分类号： G06F13/36
CPC分类号： G06F13/4027 , G06F13/4031 , G06F13/4059 , G06F13/423 , G06F2213/0024
摘要： A bus bridge is connected to a primary bus and a secondary bus, and relays data between a master and a target which are each connected to a different one of the primary and secondary buses. The bus bridge includes a primary bus interface, a secondary bus interface, a data FIFO, and a register block. The register block, which can be written by the master, includes two registers corresponding to the primary and secondary buses. Relay information showing the number of entries of data to be relayed from the target to the master is registered in a register corresponding to a bus to which the target is connected. In a read transaction, the primary bus interface or the secondary bus interface reads data from the target until data of the amount shown by the registered relay information is stored in the data FIFO.
摘要翻译：总线桥连接到主总线和辅助总线，并且中继主机和目标之间的数据，每个主站和目标站之间连接到主总线和次总线之间的不同的总线。总线桥包括主总线接口，辅助总线接口，数据FIFO和寄存器块。可由主器件写入的寄存器块包括与主母线和辅助母线相对应的两个寄存器。显示要从目标到主机中继的数据的条目数的中继信息被登记在对应于目标连接到的总线的寄存器中。在读取事务中，主总线接口或辅助总线接口从目标读取数据，直到被注册的中继信息所示量的数据被存储在数据FIFO中。

8. 发明申请

US20060047882A1 Bus bridge 有权
公开(公告)号：US20060047882A1
公开(公告)日：2006-03-02
申请号：US11209511
申请日：2005-08-23
申请人： Kenichi Kawaguchi
发明人： Kenichi Kawaguchi
IPC分类号： G06F13/36
CPC分类号： G06F13/4027 , G06F13/4031 , G06F13/4059 , G06F13/423 , G06F2213/0024
摘要： A bus bridge is connected to a primary bus and a secondary bus, and relays data between a master and a target which are each connected to a different one of the primary and secondary buses. The bus bridge includes a primary bus interface, a secondary bus interface, a data FIFO, and a register block. The register block, which can be written by the master, includes two registers corresponding to the primary and secondary buses. Relay information showing the number of entries of data to be relayed from the target to the master is registered in a register corresponding to a bus to which the target is connected. In a read transaction, the primary bus interface or the secondary bus interface reads data from the target until data of the amount shown by the registered relay information is stored in the data FIFO.

9. 发明申请

US20050261303A1 N-phenyl-(2r,5s) dimethylpiperadine derivative 有权
标题翻译： N-苯基 - （2r，5s）二甲基哌啶衍生物
公开(公告)号：US20050261303A1
公开(公告)日：2005-11-24
申请号：US10521119
申请日：2003-07-11
申请人： Nobuaki Taniguchi , Masakazu Imamura , Masahiko Hayakawa , Kenichi Kawaguchi , Takenori Kimura , Isao Kinoyama , Hiroyuki Kaizawa , Minoru Okada , Takashi Furutani
发明人： Nobuaki Taniguchi , Masakazu Imamura , Masahiko Hayakawa , Kenichi Kawaguchi , Takenori Kimura , Isao Kinoyama , Hiroyuki Kaizawa , Minoru Okada , Takashi Furutani
IPC分类号： A61P5/28 , A61P13/08 , A61P17/08 , A61P17/14 , A61P35/00 , C07D213/75 , C07D213/84 , C07D239/42 , C07D295/215 , A61K31/496 , A61K31/506 , C07D43/02
CPC分类号： C07D213/75 , C07D213/84 , C07D239/42 , C07D295/215
摘要： The present invention relates to a novel N-phenyl-(2R,5S)dimethylpiperazine derivatives useful as antiandrogenic agent which exhibits a sufficient prostate gland reducing effect as compared with conventional compounds and are excellent in oral activity. The compound of the present application is useful in preventing or treating prostate cancer, benign prostatic hyperplasia, and the like. The present invention also provides a novel intermediate useful in producing the compound of the present invention.
摘要翻译：本发明涉及用作抗雄激素剂的新型N-苯基 - （2R，5S）二甲基哌嗪衍生物，其与常规化合物相比表现出足够的前列腺减少效果，口服活性优异。本申请的化合物可用于预防或治疗前列腺癌，良性前列腺增生等。本发明还提供了可用于制备本发明化合物的新型中间体。

10. 发明申请

US20050223195A1 Processor for making more efficient use of idling components and program conversion apparatus for the same 审中-公开
公开(公告)号：US20050223195A1
公开(公告)日：2005-10-06
申请号：US11144132
申请日：2005-06-03
申请人： Kenichi Kawaguchi
发明人： Kenichi Kawaguchi
IPC分类号： G06F9/30 , G06F9/302 , G06F9/318 , G06F9/38
CPC分类号： G06F9/3001 , G06F9/3017 , G06F9/3822 , G06F9/3853 , G06F9/3885
摘要： A processor that has a plurality of instruction slots each of which stores an instruction to be executed in parallel. One of the plurality of instruction slots is a first instruction slot and another a second instruction slot. A special instruction stored in the first instruction slot is executed by a first functional unit that executes instructions stored in the first instruction slot, and a second functional unit that executes instructions stored in the second instruction slot. An instruction stored in the second instruction slot is executed in parallel by a third functional unit that executes instructions stored in the second instruction slot.

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