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1. 发明授权

US08219340B2 Monitoring method for through-silicon vias of three-dimensional intergrated circuit (3D IC) and apparatus using the same 有权
标题翻译：三维集成电路（3D IC）的硅通孔监视方法及使用该通孔的设备
公开(公告)号：US08219340B2
公开(公告)日：2012-07-10
申请号：US12435311
申请日：2009-05-04
申请人： Keng-Li Su , Chih Sheng Lin , Chih-Wen Hsiao
发明人： Keng-Li Su , Chih Sheng Lin , Chih-Wen Hsiao
IPC分类号： G01R13/00 , G01R29/26
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A monitoring method for Through-Silicon Vias (TSVs) of a three-dimensional integrated circuit (3D IC) is provided, wherein the 3D IC includes a plurality of TSVs, and the method includes: providing a plurality of inverters; connecting the inverters with the TSVs as a circuit; enabling the circuit to oscillate; measuring an output signal on an output end of one of the inverters; and determining the characteristic of TSVs of the 3D IC based on the output signal.
摘要翻译：提供了一种三维集成电路（3D IC）的通硅通孔（TSV）的监视方法，其中3D IC包括多个TSV，并且该方法包括：提供多个逆变器; 将变频器与TSV连接作为电路; 使电路振荡; 测量其中一个逆变器的输出端的输出信号; 以及基于输出信号确定3D IC的TSV的特性。

2. 发明授权

US09064837B2 Monitoring method for three-dimensional intergrated circuit (3D IC) and apparatus using the same 有权
标题翻译：三维集成电路（3D IC）及其使用的装置的监控方法
公开(公告)号：US09064837B2
公开(公告)日：2015-06-23
申请号：US13493976
申请日：2012-06-11
申请人： Keng-Li Su , Chih Sheng Lin , Chih-Wen Hsiao
发明人： Keng-Li Su , Chih Sheng Lin , Chih-Wen Hsiao
IPC分类号： G01R31/28 , G01R13/00 , H01L23/48 , H01L21/66
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A monitoring method of a three-dimensional integrated circuit (3D IC) is provided, wherein the method includes: providing a plurality of TSVs, providing a plurality of inverters; connecting the inverters with the plurality of TSVs as a circuit loop; enabling the circuit loop to oscillate; measuring an output signal on an output end of one of the plurality of inverters; and determining the manufacturing state of the plurality of TSVs of the 3D IC based on the output signal and apparatus using the same.
摘要翻译：提供了三维集成电路（3D IC）的监视方法，其中所述方法包括：提供多个TSV，提供多个逆变器; 将所述反相器与所述多个TSV连接作为电路回路; 使电路回路振荡; 测量所述多个逆变器之一的输出端上的输出信号; 以及基于输出信号和使用其的装置来确定3D IC的多个TSV的制造状态。

3. 发明申请

US20120249178A1 MONITORING METHOD FOR THREE-DIMENSIONAL INTERGRATED CIRCUIT (3D IC) AND APPARATUS USING THE SAME 审中-公开
标题翻译：三维集成电路（3D IC）的监视方法及其使用的装置
公开(公告)号：US20120249178A1
公开(公告)日：2012-10-04
申请号：US13493976
申请日：2012-06-11
申请人： Keng-Li Su , Chih Sheng Lin , Chih-Wen Hsiao
发明人： Keng-Li Su , Chih Sheng Lin , Chih-Wen Hsiao
IPC分类号： G01R31/26
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A monitoring method of a three-dimensional integrated circuit (3D IC) is provided, wherein the method includes: providing a plurality of TSVs, providing a plurality of inverters; connecting the inverters with the plurality of TSVs as a circuit loop; enabling the circuit loop to oscillate; measuring an output signal on an output end of one of the plurality of inverters; and determining the manufacturing state of the plurality of TSVs of the 3D IC based on the output signal and apparatus using the same.
摘要翻译：提供了三维集成电路（3D IC）的监视方法，其中该方法包括：提供多个TSV，提供多个逆变器; 将所述反相器与所述多个TSV连接作为电路回路; 使电路回路振荡; 测量所述多个逆变器之一的输出端上的输出信号; 以及基于输出信号和使用其的装置来确定3D IC的多个TSV的制造状态。

4. 发明授权

US08164113B2 Electrostatic discharge structure for 3-dimensional integrated circuit through-silicon via device 有权
标题翻译：三维集成电路通硅片通过器件的静电放电结构
公开(公告)号：US08164113B2
公开(公告)日：2012-04-24
申请号：US12564051
申请日：2009-09-22
申请人： Chih-Sheng Lin , Chih-Wen Hsiao , Keng-Li Su
发明人： Chih-Sheng Lin , Chih-Wen Hsiao , Keng-Li Su
IPC分类号： H01L23/60 , H01L29/74 , H01L31/111 , H01L23/62 , H01L23/48 , H02H9/00
CPC分类号： H01L23/60 , H01L23/481 , H01L24/05 , H01L24/16 , H01L25/0657 , H01L27/0251 , H01L2224/0401 , H01L2224/05009 , H01L2224/13025 , H01L2224/13099 , H01L2224/14181 , H01L2224/16145 , H01L2225/06513 , H01L2225/06541 , H01L2924/12036 , H01L2924/13091 , H01L2924/14 , H01L2924/30105 , H01L2924/30107 , H01L2924/00
摘要： An electrostatic discharge (ESD) structure for a 3-dimensional (3D) integrated circuit (IC) through-silicon via (TSV) device is provided. The ESD structure includes a substrate, a TSV device which is formed through the substrate and is equivalent to a resistance-inductance-capacitance (RLC) device, and at least one ESD device which is disposed in the substrate and electrically connected to one end of the TSV device. The ESD structure can protect the 3D IC TSV device.
摘要翻译：提供了一种三维（3D）集成电路（IC）穿硅通孔（TSV）器件的静电放电（ESD）结构。 ESD结构包括衬底，通过衬底形成并等效于电阻 - 电感 - 电容（RLC）器件的TSV器件，以及至少一个ESD器件，其被布置在衬底中并电连接到 TSV设备。 ESD结构可以保护3D IC TSV器件。

5. 发明授权

US07894274B2 Memories with improved write current 有权
标题翻译：具有改善写入电流的存储器
公开(公告)号：US07894274B2
公开(公告)日：2011-02-22
申请号：US12479612
申请日：2009-06-05
申请人： Chih Sheng Lin , Min-Chuan Wang , Chih-Wen Hsiao , Keng-Li Su
发明人： Chih Sheng Lin , Min-Chuan Wang , Chih-Wen Hsiao , Keng-Li Su
IPC分类号： G11C7/00
CPC分类号： G11C8/08 , G11C7/12 , G11C11/1655 , G11C11/1675 , G11C13/0004 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/0038 , G11C13/0069 , G11C2013/0071 , G11C2013/009
摘要： A memory with improved write current is provided, including a bit line, a write switch and a control circuit. The write switch is coupled between a voltage source and the bit line, and has a control terminal. Based on a bit line select signal, the control circuit controls the electric conductance of the write switch and discharges/charges the parasitic capacitors of the write switch. The voltage source is turned on after the control terminal of the write switch reaches a pre-determined voltage level.
摘要翻译：提供具有改善的写入电流的存储器，包括位线，写入开关和控制电路。写开关耦合在电压源和位线之间，并且具有控制端子。基于位线选择信号，控制电路控制写入开关的电导，并对写入开关的寄生电容器进行放电/充电。在写开关的控制端达到预定电压电平之后，电压源接通。

6. 发明申请

US20100237386A1 ELECTROSTATIC DISCHARGE STRUCTURE FOR 3-DIMENSIONAL INTEGRATED CIRCUIT THROUGH-SILICON VIA DEVICE 有权
标题翻译：静电放电结构通过器件通过硅三维集成电路
公开(公告)号：US20100237386A1
公开(公告)日：2010-09-23
申请号：US12564051
申请日：2009-09-22
申请人： Chih-Sheng Lin , Chih-Wen Hsiao , Keng-Li Su
发明人： Chih-Sheng Lin , Chih-Wen Hsiao , Keng-Li Su
IPC分类号： H01L23/60 , H01L23/48
CPC分类号： H01L23/60 , H01L23/481 , H01L24/05 , H01L24/16 , H01L25/0657 , H01L27/0251 , H01L2224/0401 , H01L2224/05009 , H01L2224/13025 , H01L2224/13099 , H01L2224/14181 , H01L2224/16145 , H01L2225/06513 , H01L2225/06541 , H01L2924/12036 , H01L2924/13091 , H01L2924/14 , H01L2924/30105 , H01L2924/30107 , H01L2924/00
摘要： An electrostatic discharge (ESD) structure for a 3-dimensional (3D) integrated circuit (IC) through-silicon via (TSV) device is provided. The ESD structure includes a substrate, a TSV device which is formed through the substrate and is equivalent to a resistance-inductance-capacitance (RLC) device, and at least one ESD device which is disposed in the substrate and electrically connected to one end of the TSV device. The ESD structure can protect the 3D IC TSV device.
摘要翻译：提供了一种三维（3D）集成电路（IC）穿硅通孔（TSV）器件的静电放电（ESD）结构。 ESD结构包括衬底，通过衬底形成并等效于电阻 - 电感 - 电容（RLC）器件的TSV器件，以及至少一个ESD器件，其被布置在衬底中并电连接到 TSV设备。 ESD结构可以保护3D IC TSV器件。

7. 发明申请

US20100118617A1 MEMORIES WITH IMPROVED WRITE CURRENT 有权
标题翻译：具有改进的写入电流的记忆
公开(公告)号：US20100118617A1
公开(公告)日：2010-05-13
申请号：US12479612
申请日：2009-06-05
申请人： Chih Sheng Lin , Min-Chuan Wang , Chih-Wen Hsiao , Keng-Li Su
发明人： Chih Sheng Lin , Min-Chuan Wang , Chih-Wen Hsiao , Keng-Li Su
IPC分类号： G11C7/10 , G11C5/14
CPC分类号： G11C8/08 , G11C7/12 , G11C11/1655 , G11C11/1675 , G11C13/0004 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/0038 , G11C13/0069 , G11C2013/0071 , G11C2013/009
摘要： A memory with improved write current is provided, including a bit line, a write switch and a control circuit. The write switch is coupled between a voltage source and the bit line, and has a control terminal. Based on a bit line select signal, the control circuit controls the electric conductance of the write switch and discharges/charges the parasitic capacitors of the write switch. The voltage source is turned on after the control terminal of the write switch reaches a pre-determined voltage level.
摘要翻译：提供具有改善的写入电流的存储器，包括位线，写入开关和控制电路。写开关耦合在电压源和位线之间，并且具有控制端子。基于位线选择信号，控制电路控制写入开关的电导，并对写入开关的寄生电容器进行放电/充电。在写开关的控制端达到预定电压电平之后，电压源接通。

8. 发明申请

US20120139092A1 MULTI-CHIP STACK STRUCTURE 有权
标题翻译：多芯片堆叠结构
公开(公告)号：US20120139092A1
公开(公告)日：2012-06-07
申请号：US12968285
申请日：2010-12-15
申请人： Keng-Li Su , Hsin-Chi Lai , Chih-Sheng Lin , Zhe-Hui Lin
发明人： Keng-Li Su , Hsin-Chi Lai , Chih-Sheng Lin , Zhe-Hui Lin
IPC分类号： H01L23/552
CPC分类号： H01L25/0657 , H01L23/642 , H01L2224/16145 , H01L2225/06513 , H01L2225/06517 , H01L2225/06537 , H01L2225/06541
摘要： A multi-chip stack structure including a first chip, a second chip, a shielding layer, and a plurality of conductive bumps is provided. The second chip is stacked on the first chip. The second chip has a plurality of through silicon via (TSV) structures to conduct a reference voltage. The shielding layer and the plurality of conductive bumps are disposed between the first chip and the second chip, and are electrically connected to the plurality of TSV structures. The shielding layer can isolate noises and improve signal coupling between two adjacent chips.
摘要翻译：提供了包括第一芯片，第二芯片，屏蔽层和多个导电凸块的多芯片堆叠结构。第二芯片堆叠在第一芯片上。第二芯片具有多个贯穿硅通孔（TSV）结构以导通参考电压。屏蔽层和多个导电凸块设置在第一芯片和第二芯片之间，并且电连接到多个TSV结构。屏蔽层可以隔离噪声并改善两个相邻芯片之间的信号耦合。

9. 发明授权

US07486546B2 Multi-state sense amplifier 有权
标题翻译：多状态读出放大器
公开(公告)号：US07486546B2
公开(公告)日：2009-02-03
申请号：US11806636
申请日：2007-06-01
申请人： Min-Chuan Wang , Chih-Sheng Lin , Chia-Pao Chang , Keng-Li Su
发明人： Min-Chuan Wang , Chih-Sheng Lin , Chia-Pao Chang , Keng-Li Su
IPC分类号： G11C11/00
CPC分类号： G11C7/062 , G11C7/06 , G11C11/1673 , G11C11/5607 , G11C2207/063 , G11C2211/5634 , G11C2211/5645
摘要： The invention provides a multi-state sense amplifier, coupled to at least one memory cell with changeable resistance and a plurality of reference cells. The first current mirror circuit, coupled to the output terminal of the memory cell, generates a second memory cell current at a first node according to a first memory cell current through the memory cell. The second current mirror circuit, coupled to the output terminal of the reference cells, generates a plurality of second reference currents at a plurality of second nodes according to a plurality of first reference currents through the reference cells. The load circuit, coupled to the first node, the second nodes, and a ground, provides equal loads for the second memory cell current and the second reference currents to respectively generate a memory cell voltage at the first node and a plurality of reference voltages at the second nodes.
摘要翻译：本发明提供一种多状态读出放大器，耦合到具有可变电阻的至少一个存储单元和多个参考单元。耦合到存储器单元的输出端的第一电流镜电路根据通过存储单元的第一存储单元电流在第一节点产生第二存储单元电流。耦合到参考单元的输出端的第二电流镜电路根据通过参考单元的多个第一参考电流在多个第二节点处产生多个第二参考电流。耦合到第一节点，第二节点和地的负载电路为第二存储器单元电流和第二参考电流提供相等的负载，以分别在第一节点处产生存储单元电压和多个参考电压第二个节点。

10. 发明申请

US20080007992A1 Multi-state sense amplifier 有权
标题翻译：多状态读出放大器
公开(公告)号：US20080007992A1
公开(公告)日：2008-01-10
申请号：US11806636
申请日：2007-06-01
申请人： Min-Chuan Wang , Chih-Sheng Lin , Chia-Pao Chang , Keng-Li Su
发明人： Min-Chuan Wang , Chih-Sheng Lin , Chia-Pao Chang , Keng-Li Su
IPC分类号： G11C11/02 , G11C7/06
CPC分类号： G11C7/062 , G11C7/06 , G11C11/1673 , G11C11/5607 , G11C2207/063 , G11C2211/5634 , G11C2211/5645
摘要： The invention provides a multi-state sense amplifier, coupled to at least one memory cell with changeable resistance and a plurality of reference cells. The first current mirror circuit, coupled to the output terminal of the memory cell, generates a second memory cell current at a first node according to a first memory cell current through the memory cell. The second current mirror circuit, coupled to the output terminal of the reference cells, generates a plurality of second reference currents at a plurality of second nodes according to a plurality of first reference currents through the reference cells. The load circuit, coupled to the first node, the second nodes, and a ground, provides equal loads for the second memory cell current and the second reference currents to respectively generate a memory cell voltage at the first node and a plurality of reference voltages at the second nodes.
摘要翻译：本发明提供一种多状态读出放大器，耦合到具有可变电阻的至少一个存储单元和多个参考单元。耦合到存储器单元的输出端的第一电流镜电路根据通过存储单元的第一存储单元电流在第一节点产生第二存储单元电流。耦合到参考单元的输出端的第二电流镜电路根据通过参考单元的多个第一参考电流在多个第二节点处产生多个第二参考电流。耦合到第一节点，第二节点和接地的负载电路为第二存储器单元电流和第二参考电流提供相等的负载，以分别在第一节点处产生存储器单元电压和多个参考电压第二个节点。

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