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1. 发明授权

US08219340B2 Monitoring method for through-silicon vias of three-dimensional intergrated circuit (3D IC) and apparatus using the same 有权
标题翻译：三维集成电路（3D IC）的硅通孔监视方法及使用该通孔的设备
公开(公告)号：US08219340B2
公开(公告)日：2012-07-10
申请号：US12435311
申请日：2009-05-04
申请人： Keng-Li Su , Chih Sheng Lin , Chih-Wen Hsiao
发明人： Keng-Li Su , Chih Sheng Lin , Chih-Wen Hsiao
IPC分类号： G01R13/00 , G01R29/26
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A monitoring method for Through-Silicon Vias (TSVs) of a three-dimensional integrated circuit (3D IC) is provided, wherein the 3D IC includes a plurality of TSVs, and the method includes: providing a plurality of inverters; connecting the inverters with the TSVs as a circuit; enabling the circuit to oscillate; measuring an output signal on an output end of one of the inverters; and determining the characteristic of TSVs of the 3D IC based on the output signal.
摘要翻译：提供了一种三维集成电路（3D IC）的通硅通孔（TSV）的监视方法，其中3D IC包括多个TSV，并且该方法包括：提供多个逆变器; 将变频器与TSV连接作为电路; 使电路振荡; 测量其中一个逆变器的输出端的输出信号; 以及基于输出信号确定3D IC的TSV的特性。

2. 发明申请

US20100153043A1 MONITORING METHOD FOR THROUGH-SILICON VIAS OF THREE-DIMENSIONAL INTERGRATED CIRCUIT (3D IC) AND APPARATUS USING THE SAME 有权
标题翻译：三维集成电路（3D IC）的通孔硅的监视方法及其使用的装置
公开(公告)号：US20100153043A1
公开(公告)日：2010-06-17
申请号：US12435311
申请日：2009-05-04
申请人： Keng-Li SU , Chih Sheng LIN , Chih-Wen HSIAO
发明人： Keng-Li SU , Chih Sheng LIN , Chih-Wen HSIAO
IPC分类号： G06F19/00 , G01R13/00
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A monitoring method for Through-Silicon Vias (TSVs) of a three-dimensional integrated circuit (3D IC) is provided, wherein the 3D IC includes a plurality of TSVs, and the method includes: providing a plurality of inverters; connecting the inverters with the TSVs as a circuit; enabling the circuit to oscillate; measuring an output signal on an output end of one of the inverters; and determining the characteristic of TSVs of the 3D IC based on the output signal.
摘要翻译：提供了一种三维集成电路（3D IC）的通硅通孔（TSV）的监视方法，其中3D IC包括多个TSV，并且该方法包括：提供多个逆变器; 将变频器与TSV连接作为电路; 使电路振荡; 测量其中一个逆变器的输出端的输出信号; 以及基于输出信号确定3D IC的TSV的特性。

3. 发明申请

US20080157826A1 VOLTAGE DRIVING CIRCUIT 审中-公开
标题翻译：电压驱动电路
公开(公告)号：US20080157826A1
公开(公告)日：2008-07-03
申请号：US11739114
申请日：2007-04-24
申请人： Ming-Daw Chen , Shyh-Shyuan Sheu , Wei-Chun Chang , Keng-Li Su
发明人： Ming-Daw Chen , Shyh-Shyuan Sheu , Wei-Chun Chang , Keng-Li Su
IPC分类号： H03K3/00
CPC分类号： G09G3/3648 , G09G2300/0465 , G09G2300/0809 , G09G2300/0823 , G09G2300/0857
摘要： A voltage driving circuit, suitable for being used in a pixel driving circuit, includes a storage unit for receiving a single-end data input signal and outputting a first voltage signal and a second voltage signal according to a content of the data input signal. The first voltage signal and the second voltage signal have different voltage levels, and the voltage levels are a high voltage level and a low voltage level, which have been adjusted to a driving-voltage requirement satisfying subsequent operations. A switch control unit receives the first voltage signal and the second voltage signal and outputs an output-voltage signal at an output terminal based on a determination from at least one control signal. The output-voltage signal is the high voltage level or the low voltage level.
摘要翻译：适用于像素驱动电路的电压驱动电路包括：存储单元，用于接收单端数据输入信号，并根据数据输入信号的内容输出第一电压信号和第二电压信号。第一电压信号和第二电压信号具有不同的电压电平，并且电压电平是已经被调整到满足后续操作的驱动电压要求的高电压电平和低电压电平。开关控制单元接收第一电压信号和第二电压信号，并且基于来自至少一个控制信号的确定在输出端输出输出电压信号。输出电压信号为高电平或低电平。

4. 发明授权

US06980780B2 Power controller 有权
标题翻译：电源控制器
公开(公告)号：US06980780B2
公开(公告)日：2005-12-27
申请号：US09855511
申请日：2001-05-16
申请人： Chieh-Sheng Chen , Keng-Li Su
发明人： Chieh-Sheng Chen , Keng-Li Su
IPC分类号： H03F3/19 , H03G3/30 , H04B1/04
CPC分类号： H03G3/3042 , H03F3/19 , H04B2001/0416
摘要： An apparatus for power controlling in a transmitter for detecting the output power without using a power coupler includes a plurality of stage amplifiers, a plurality of matching circuits, at least one power detector, and a bias control circuit. The stage amplifiers receive an emission signal and amplify the power thereof. The matching circuits are connected between the stage amplifiers for matching with the stage amplifiers, respectively. The power detector detects the power of the stage amplifiers and generates detection signals, respectively. The bias control circuit receives the detection signals of the power detector, thereby generating a bias of each of the stage amplifiers in order to optimize the efficiency of each of the stage amplifiers according to the magnitude of the power of each of the stage amplifiers.
摘要翻译：一种用于在不使用功率耦合器的情况下检测输出功率的发射机中的功率控制的装置包括多个级放大器，多个匹配电路，至少一个功率检测器和偏置控制电路。舞台放大器接收发射信号并放大其功率。匹配电路分别连接在级放大器之间，以与舞台放大器匹配。功率检测器检测级放大器的功率，分别产生检测信号。偏置控制电路接收功率检测器的检测信号，从而产生每个级放大器的偏置，以便根据每个级放大器的功率的大小优化每个级放大器的效率。

5. 发明申请

US20120139092A1 MULTI-CHIP STACK STRUCTURE 有权
标题翻译：多芯片堆叠结构
公开(公告)号：US20120139092A1
公开(公告)日：2012-06-07
申请号：US12968285
申请日：2010-12-15
申请人： Keng-Li Su , Hsin-Chi Lai , Chih-Sheng Lin , Zhe-Hui Lin
发明人： Keng-Li Su , Hsin-Chi Lai , Chih-Sheng Lin , Zhe-Hui Lin
IPC分类号： H01L23/552
CPC分类号： H01L25/0657 , H01L23/642 , H01L2224/16145 , H01L2225/06513 , H01L2225/06517 , H01L2225/06537 , H01L2225/06541
摘要： A multi-chip stack structure including a first chip, a second chip, a shielding layer, and a plurality of conductive bumps is provided. The second chip is stacked on the first chip. The second chip has a plurality of through silicon via (TSV) structures to conduct a reference voltage. The shielding layer and the plurality of conductive bumps are disposed between the first chip and the second chip, and are electrically connected to the plurality of TSV structures. The shielding layer can isolate noises and improve signal coupling between two adjacent chips.
摘要翻译：提供了包括第一芯片，第二芯片，屏蔽层和多个导电凸块的多芯片堆叠结构。第二芯片堆叠在第一芯片上。第二芯片具有多个贯穿硅通孔（TSV）结构以导通参考电压。屏蔽层和多个导电凸块设置在第一芯片和第二芯片之间，并且电连接到多个TSV结构。屏蔽层可以隔离噪声并改善两个相邻芯片之间的信号耦合。

6. 发明申请

US20120018723A1 STRUCTURE AND METHOD FOR TESTING THROUGH-SILICON VIA (TSV) 审中-公开
标题翻译：用于测试通过硅（TSV）的结构和方法
公开(公告)号：US20120018723A1
公开(公告)日：2012-01-26
申请号：US12967932
申请日：2010-12-14
申请人： Keng-Li SU , Chih-Sheng Lin , Wen-Pin Lin , John H. Lau
发明人： Keng-Li SU , Chih-Sheng Lin , Wen-Pin Lin , John H. Lau
IPC分类号： H01L23/58 , H01L21/66
CPC分类号： H01L22/34
摘要： A test structure including at least one ground pad, an input pad, at least one first through-silicon via (TSV), at least one second TSV and an output pad is disclosed. The ground pad receives a ground signal during a test mode. The input pad receives a test signal during the test mode. The first TSV is coupled to the input pad. The output pad is coupled to the second TSV. No connection line occurs between the first and the second TSVs. During the test mode, a test result is obtained according to the signal of at least one of the first and the second TSVs, and structural characteristics can be obtained according to the test result.
摘要翻译：公开了包括至少一个接地焊盘，输入焊盘，至少一个第一穿透硅通孔（TSV），至少一个第二TSV和输出焊盘的测试结构。接地焊盘在测试模式下接收接地信号。在测试模式期间，输入焊盘接收测试信号。第一TSV耦合到输入板。输出焊盘耦合到第二TSV。在第一和第二TSV之间不发生连接线。在测试模式期间，根据第一和第二TSV中的至少一个的信号获得测试结果，并且可以根据测试结果获得结构特征。

7. 发明申请

US20090141574A1 Memory accessing circuit and method 有权
标题翻译：存储器访问电路和方法
公开(公告)号：US20090141574A1
公开(公告)日：2009-06-04
申请号：US12155787
申请日：2008-06-10
申请人： Min Chuan Wang , Chih Sheng Lin , Keng Li Su , Wei Chun Chang
发明人： Min Chuan Wang , Chih Sheng Lin , Keng Li Su , Wei Chun Chang
IPC分类号： G11C7/02
CPC分类号： G11C11/5607 , G11C11/16 , G11C29/08 , G11C2211/5634
摘要： The present invention relates to a memory accessing circuit, which is for accessing a memory circuit with 2N impedance states. The memory accessing circuit comprises a testing signal generating circuit, for generating a testing signal by detecting the impedance state of the memory circuit; a reference signal generating circuit, for generating 2N−1 reference signals by detecting the impedance states of a reference circuit having 2N−1 impedance paths; a median signal generating circuit, for generating (2N−1)−1, median signals by receiving the 2N−1 reference signals; and a comparing circuit, for comparing the testing signal and the (2N−1) median signals. The present invention further provides a memory accessing method thereof.
摘要翻译：本发明涉及一种用于访问具有2N个阻抗状态的存储器电路的存储器存取电路。存储器访问电路包括测试信号发生电路，用于通过检测存储器电路的阻抗状态来产生测试信号; 参考信号发生电路，用于通过检测具有2N-1个阻抗路径的参考电路的阻抗状态来产生2N-1个参考信号; 中间信号发生电路，用于通过接收2N-1个参考信号来产生（2N-1）-1个中间信号; 以及用于比较测试信号和（2N-1）个中值信号的比较电路。本发明还提供一种其存储器访问方法。

8. 发明授权

US07369424B2 Programmable memory cell and operation method 失效
标题翻译：可编程存储单元和操作方法
公开(公告)号：US07369424B2
公开(公告)日：2008-05-06
申请号：US11271550
申请日：2005-11-09
申请人： Keng-Li Su , Shyh-Shyuan Sheu , Jan-Ruel Lin , Wei-Jen Chang , Chen-Pang Kung
发明人： Keng-Li Su , Shyh-Shyuan Sheu , Jan-Ruel Lin , Wei-Jen Chang , Chen-Pang Kung
IPC分类号： G11C11/00 , G11C11/14
CPC分类号： G11C13/00 , B82Y10/00 , G11C13/0014 , G11C2213/79
摘要： A memory array including a plurality of programmable memory cells, a plurality of column lines and a plurality of row lines is introduced. Each of the programmable memory cells is coupled to corresponding one of the column lines and corresponding one of the row lines. Each of the programmable memory cells includes an organic memory cell and an active switching element. The active switching element is controlled by the column line and interposed between the row line and the organic memory cell. Under controlling of the column line, the active switching element is turned on to coupling the row line and the organic memory cell to connect to each other.
摘要翻译：引入包括多个可编程存储器单元，多个列线和多个行线的存储器阵列。每个可编程存储器单元耦合到对应的列线和对应的一行行。每个可编程存储器单元包括有机存储单元和有源开关元件。有源开关元件由列线控制并插入在行线和有机存储单元之间。在列线的控制下，有源开关元件被接通以将行线和有机存储器单元耦合以彼此连接。

9. 发明授权

US08164113B2 Electrostatic discharge structure for 3-dimensional integrated circuit through-silicon via device 有权
标题翻译：三维集成电路通硅片通过器件的静电放电结构
公开(公告)号：US08164113B2
公开(公告)日：2012-04-24
申请号：US12564051
申请日：2009-09-22
申请人： Chih-Sheng Lin , Chih-Wen Hsiao , Keng-Li Su
发明人： Chih-Sheng Lin , Chih-Wen Hsiao , Keng-Li Su
IPC分类号： H01L23/60 , H01L29/74 , H01L31/111 , H01L23/62 , H01L23/48 , H02H9/00
CPC分类号： H01L23/60 , H01L23/481 , H01L24/05 , H01L24/16 , H01L25/0657 , H01L27/0251 , H01L2224/0401 , H01L2224/05009 , H01L2224/13025 , H01L2224/13099 , H01L2224/14181 , H01L2224/16145 , H01L2225/06513 , H01L2225/06541 , H01L2924/12036 , H01L2924/13091 , H01L2924/14 , H01L2924/30105 , H01L2924/30107 , H01L2924/00
摘要： An electrostatic discharge (ESD) structure for a 3-dimensional (3D) integrated circuit (IC) through-silicon via (TSV) device is provided. The ESD structure includes a substrate, a TSV device which is formed through the substrate and is equivalent to a resistance-inductance-capacitance (RLC) device, and at least one ESD device which is disposed in the substrate and electrically connected to one end of the TSV device. The ESD structure can protect the 3D IC TSV device.
摘要翻译：提供了一种三维（3D）集成电路（IC）穿硅通孔（TSV）器件的静电放电（ESD）结构。 ESD结构包括衬底，通过衬底形成并等效于电阻 - 电感 - 电容（RLC）器件的TSV器件，以及至少一个ESD器件，其被布置在衬底中并电连接到 TSV设备。 ESD结构可以保护3D IC TSV器件。

10. 发明授权

US07894274B2 Memories with improved write current 有权
标题翻译：具有改善写入电流的存储器
公开(公告)号：US07894274B2
公开(公告)日：2011-02-22
申请号：US12479612
申请日：2009-06-05
申请人： Chih Sheng Lin , Min-Chuan Wang , Chih-Wen Hsiao , Keng-Li Su
发明人： Chih Sheng Lin , Min-Chuan Wang , Chih-Wen Hsiao , Keng-Li Su
IPC分类号： G11C7/00
CPC分类号： G11C8/08 , G11C7/12 , G11C11/1655 , G11C11/1675 , G11C13/0004 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/0038 , G11C13/0069 , G11C2013/0071 , G11C2013/009
摘要： A memory with improved write current is provided, including a bit line, a write switch and a control circuit. The write switch is coupled between a voltage source and the bit line, and has a control terminal. Based on a bit line select signal, the control circuit controls the electric conductance of the write switch and discharges/charges the parasitic capacitors of the write switch. The voltage source is turned on after the control terminal of the write switch reaches a pre-determined voltage level.
摘要翻译：提供具有改善的写入电流的存储器，包括位线，写入开关和控制电路。写开关耦合在电压源和位线之间，并且具有控制端子。基于位线选择信号，控制电路控制写入开关的电导，并对写入开关的寄生电容器进行放电/充电。在写开关的控制端达到预定电压电平之后，电压源接通。

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