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1. 发明申请

US20050158999A1 Multi-step plasma treatment method to improve CU interconnect electrical performance 有权
标题翻译：多级等离子处理方法提高CU互连电气性能
公开(公告)号：US20050158999A1
公开(公告)日：2005-07-21
申请号：US10762186
申请日：2004-01-20
申请人： Keng-Chu Lin , Hui-Lin Chang , I-I Chen , Yung-Chen Lu , Syug-Ming Jang
发明人： Keng-Chu Lin , Hui-Lin Chang , I-I Chen , Yung-Chen Lu , Syug-Ming Jang
IPC分类号： H01L21/321 , H01L21/768 , H01L21/04 , H01L21/469 , H01L21/4763
CPC分类号： H01L21/76888 , H01L21/321 , H01L21/76826 , H01L21/76829 , H01L21/76838 , H01L21/7684
摘要： A method for plasma treating an exposed copper surface and dielectric insulating layer in a semiconductor device manufacturing process including providing a semiconductor wafer having a process surface including an exposed copper portion and an exposed dielectric insulating layer portion; plasma treating in a first plasma treatment process, the process surface with a first plasma including ammonia (NH3) and nitrogen (N2) plasma to form a copper nitride layer overlying the exposed copper portion; and, plasma treating in a second plasma treatment process the process surface with a second plasma including oxygen (O2).
摘要翻译：一种在半导体器件制造工艺中等离子体处理暴露的铜表面和介电绝缘层的方法，包括提供具有包括暴露的铜部分和暴露的介电绝缘层部分的工艺表面的半导体晶片; 在第一等离子体处理过程中进行等离子体处理，所述工艺表面具有包含氨（NH 3）3和氮（N 2 O 3）等离子体的第一等离子体，以形成覆盖的氮化铜层暴露的铜部分; 以及在第二等离子体处理过程中进行等离子体处理，所述工艺表面具有包含氧（O 2 O 2）的第二等离子体。

2. 发明授权

US07094705B2 Multi-step plasma treatment method to improve CU interconnect electrical performance 有权
标题翻译：多级等离子处理方法提高CU互连电气性能
公开(公告)号：US07094705B2
公开(公告)日：2006-08-22
申请号：US10762186
申请日：2004-01-20
申请人： Keng-Chu Lin , Hui-Lin Chang , I-I Chen , Yung-Chen Lu , Syun-Ming Jeng
发明人： Keng-Chu Lin , Hui-Lin Chang , I-I Chen , Yung-Chen Lu , Syun-Ming Jeng
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/76888 , H01L21/321 , H01L21/76826 , H01L21/76829 , H01L21/76838 , H01L21/7684
摘要： A method for plasma treating an exposed copper surface and dielectric insulating layer in a semiconductor device manufacturing process including providing a semiconductor wafer having a process surface including an exposed copper portion and an exposed dielectric insulating layer portion; plasma treating in a first plasma treatment process, the process surface with a first plasma including ammonia (NH3) and nitrogen (N2) plasma to form a copper nitride layer overlying the exposed copper portion; and, plasma treating in a second plasma treatment process the process surface with a second plasma including oxygen (O2).
摘要翻译：一种在半导体器件制造工艺中等离子体处理暴露的铜表面和介电绝缘层的方法，包括提供具有包括暴露的铜部分和暴露的介电绝缘层部分的工艺表面的半导体晶片; 在第一等离子体处理过程中进行等离子体处理，所述工艺表面具有包含氨（NH 3）3和氮（N 2 O 3）等离子体的第一等离子体，以形成覆盖的氮化铜层暴露的铜部分; 以及在第二等离子体处理过程中进行等离子体处理，所述工艺表面具有包含氧（O 2 O 2）的第二等离子体。

3. 发明授权

US09024601B2 Voltage converting apparatus with low power consumption 有权
标题翻译：具有低功耗的电压转换装置
公开(公告)号：US09024601B2
公开(公告)日：2015-05-05
申请号：US13615674
申请日：2012-09-14
申请人： Yung-Chen Lu
发明人： Yung-Chen Lu
IPC分类号： G05F1/00 , G05F1/565 , H02M7/5387 , H02M3/156 , H05B33/08 , H02M1/00
CPC分类号： H02M3/156 , H02M2001/0006 , H02M2001/0025 , H02M2001/0048 , H05B33/0818 , Y02B20/346 , Y02B70/1491
摘要： A voltage converting apparatus is disclosed. The voltage converting apparatus includes a pulse width modulation (PWM) signal generating circuit, a power transistor, a first inductor, a second inductor and a feedback rectifier. The PWM signal generating circuit receives a feedback power to be an operating power and generates a PWM signal. A first terminal of the power transistor receives an input voltage, and a control terminal of the power transistor receives the PWM signal. The second inductor couples with a voltage on the first inductor and generates a coupling voltage. The feedback rectifier rectifies the coupling voltage to generate a feedback power.
摘要翻译：公开了电压转换装置。电压转换装置包括脉冲宽度调制（PWM）信号发生电路，功率晶体管，第一电感器，第二电感器和反馈整流器。 PWM信号发生电路接收作为工作电源的反馈功率并产生PWM信号。功率晶体管的第一端接收输入电压，功率晶体管的控制端接收PWM信号。第二电感器与第一电感器上的电压耦合并产生耦合电压。反馈整流器整流耦合电压以产生反馈功率。

4. 发明申请

US20060024954A1 Copper damascene barrier and capping layer 审中-公开
标题翻译：铜镶嵌屏障和封盖层
公开(公告)号：US20060024954A1
公开(公告)日：2006-02-02
申请号：US10910007
申请日：2004-08-02
申请人： Zhen-Cheng Wu , Lain-Jong Li , Yung-Chen Lu , Syun-Ming Jang
发明人： Zhen-Cheng Wu , Lain-Jong Li , Yung-Chen Lu , Syun-Ming Jang
IPC分类号： H01L21/4763
CPC分类号： H01L21/76829 , H01L21/76831 , H01L21/7684 , H01L21/76846
摘要： A method for forming a damascene with improved electrical properties and resulting structure thereof including providing at least one dielectric insulating layer overlying a first etch stop layer; forming an anti-reflectance coating (ARC) layer prior to a photolithographic patterning process; forming at least one opening extending through a thickness portion of the at least one dielectric insulating layer and first etch stop layer according to said photolithographic patterning and an etching process; blanket depositing a barrier layer including material selected from the group consisting of silicon carbide and silicon oxycarbide to line the at least one opening; blanket depositing a refractory metal liner over the barrier layer; blanket depositing at least one metal layer to fill the at least one opening; and, removing at least the at least one metal layer overlying the at least one opening level according to a chemical mechanical polish (CMP) process.
摘要翻译：一种用于形成具有改善的电性能及其结构的镶嵌体的方法，包括提供覆盖在第一蚀刻停止层上的至少一个介电绝缘层; 在光刻图案化工艺之前形成抗反射涂层（ARC）层; 根据所述光刻图案和蚀刻工艺形成至少一个延伸穿过所述至少一个介电绝缘层的厚度部分的开口和第一蚀刻停止层; 覆盖沉积包括选自碳化硅和碳氧化硅的材料的阻挡层，以使所述至少一个开口线对准; 在阻挡层上铺设难熔金属衬垫; 毯子沉积至少一个金属层以填充所述至少一个开口; 以及根据化学机械抛光（CMP）工艺，至少去除覆盖所述至少一个开口水平面的所述至少一个金属层。

5. 发明授权

US06753269B1 Method for low k dielectric deposition 失效
标题翻译：低k电介质沉积方法
公开(公告)号：US06753269B1
公开(公告)日：2004-06-22
申请号：US10434029
申请日：2003-05-08
申请人： Lih-Ping Li , Yung-Chen Lu , Syun-Ming Jang
发明人： Lih-Ping Li , Yung-Chen Lu , Syun-Ming Jang
IPC分类号： H01L2131
CPC分类号： H01L21/76835 , H01L21/3105 , H01L21/76801 , H01L21/76807 , H01L21/76826 , H01L21/76831
摘要： The present disclosure provides a method for forming an intermediate trench layer through low k dielectric material deposition in a damascene process for manufacturing semiconductor devices. After depositing a low k dielectric material block, a curing process is applied to the low k dielectric material block for a predetermined curing time period, wherein after the curing time period, the low k dielectric material block forms a first and second low k dielectric layers so as to make the first low k dielectric layer an intermediate trench layer, thereby eliminating the need of an etch stop layer.
摘要翻译：本公开提供了一种在用于制造半导体器件的镶嵌工艺中通过低k电介质材料沉积形成中间沟槽层的方法。在沉积低k介电材料块之后，将固化过程施加到低k电介质材料块上预定的固化时间段，其中在固化时间段之后，低k电介质材料块形成第一和第二低k电介质层以便使第一低k电介质层成为中间沟槽层，由此不需要蚀刻停止层。

6. 发明授权

US08704451B2 Driving circuit of light emitting diode 有权
标题翻译：发光二极管的驱动电路
公开(公告)号：US08704451B2
公开(公告)日：2014-04-22
申请号：US13267914
申请日：2011-10-07
申请人： Yung-Chen Lu
发明人： Yung-Chen Lu
IPC分类号： H05B37/02
CPC分类号： H05B33/0809 , H05B33/0824
摘要： A driving circuit of a light emitting diode (LED) including an AC power, a rectifier, a power converter, a waveform sampler, and a control circuit is provided. The AC power provides an AC signal. The rectifier is coupled to the AC power and outputs a driving signal. The power converter is coupled to the rectifier. The power converter includes an LED and outputs a first signal positive correlated with a current passing through the LED. The waveform sampler is coupled between the AC power and the rectifier, and outputs a second signal directly proportional to the AC signal. The control circuit is coupled between the waveform sampler and the power converter, and outputs a control signal to the power converter according to a comparison result between the first signal and the second signal.
摘要翻译：提供了包括交流电源，整流器，功率转换器，波形采样器和控制电路的发光二极管（LED）的驱动电路。交流电源提供交流信号。整流器耦合到AC电源并输出驱动信号。功率转换器耦合到整流器。功率转换器包括LED并输出与通过LED的电流正相关的第一信号。波形采样器耦合在交流电源和整流器之间，并输出与AC信号成正比的第二信号。控制电路耦合在波形采样器和功率转换器之间，并根据第一信号和第二信号之间的比较结果向控制信号输出功率转换器。

7. 发明授权

US08598810B2 Constant current driving circuit of light emitting diode and lighting apparatus 有权
标题翻译：发光二极管恒流驱动电路及照明装置
公开(公告)号：US08598810B2
公开(公告)日：2013-12-03
申请号：US13101154
申请日：2011-05-05
申请人： Yung-Chen Lu
发明人： Yung-Chen Lu
IPC分类号： H05B37/02
CPC分类号： H05B33/0815 , H05B33/0851
摘要： A constant current driving circuit of a light emitting diode (LED) including a control unit, a buck converter, and a compensation unit is provided. The control unit has an input terminal and an output terminal, and outputs a control signal through the output terminal. The buck converter is coupled to an input power, and is coupled between the output terminal of the control unit and an LED string. The compensation unit is coupled between the LED string and the input terminal of the control unit. The control unit receives a compensation signal of the compensation unit through the input terminal. Besides, a lighting apparatus is also provided.
摘要翻译：提供了包括控制单元，降压转换器和补偿单元的发光二极管（LED）的恒流驱动电路。控制单元具有输入端子和输出端子，并通过输出端子输出控制信号。降压转换器耦合到输入功率，并且耦合在控制单元的输出端子和LED串之间。补偿单元耦合在LED串和控制单元的输入端之间。控制单元通过输入端接收补偿单元的补偿信号。此外，还提供了一种照明装置。

8. 发明授权

US07151315B2 Method of a non-metal barrier copper damascene integration 有权
标题翻译：非金属阻挡铜大马士革一体化方法
公开(公告)号：US07151315B2
公开(公告)日：2006-12-19
申请号：US10459222
申请日：2003-06-11
申请人： Zhen-Cheng Wu , Yung-Chen Lu , Syun-Ming Jang
发明人： Zhen-Cheng Wu , Yung-Chen Lu , Syun-Ming Jang
IPC分类号： H01L23/50
CPC分类号： H01L21/76802 , H01L21/76831 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure provides a method, integrated circuit, and interconnect structure utilizing non-metal barrier copper damascene integration. The method is provided for fabricating an interconnect for connecting to one or more front end of line (FEOL) devices. The method includes forming a layer of doped oxide on the one or more FEOL devices and forming a first barrier layer on the layer of doped oxide, the first barrier layer comprising such material as silicon oxycarbide (SiOC) or silicon carbonitride (SiCN). The method further includes forming a plurality of refractory metal plugs in the first barrier layer and the doped oxide layer, forming a low dielectric constant film over the first barrier layer and the plurality of refractory metal plugs, and performing a first etch to create trenches through the low dielectric constant film. The plurality of refractory metal plugs and the first barrier layer perform as an etch-stop.
摘要翻译：本公开提供了利用非金属阻挡铜镶嵌一体化的方法，集成电路和互连结构。该方法用于制造用于连接到一个或多个前端（FEOL）装置的互连件。该方法包括在一个或多个FEOL器件上形成掺杂氧化物层，并在掺杂氧化物层上形成第一势垒层，第一势垒层包含碳氧化硅（SiOC）或碳氮化硅（SiCN）等材料。该方法还包括在第一阻挡层和掺杂氧化物层中形成多个难熔金属塞，在第一阻挡层和多个耐火金属插塞上形成低介电常数膜，并进行第一蚀刻以产生沟槽低介电常数膜。多个难熔金属插塞和第一阻挡层执行蚀刻停止。

9. 发明授权

US06878621B2 Method of fabricating barrierless and embedded copper damascene interconnects 失效
标题翻译：制造无障碍和嵌入铜大马士革互连的方法
公开(公告)号：US06878621B2
公开(公告)日：2005-04-12
申请号：US10346382
申请日：2003-01-17
申请人： Zhen-Cheng Wu , Lain-Jong Li , Yung-Chen Lu , Syun-Ming Jang
发明人： Zhen-Cheng Wu , Lain-Jong Li , Yung-Chen Lu , Syun-Ming Jang
IPC分类号： H01L21/768 , H01L21/44 , H01L21/4763
CPC分类号： H01L21/76834 , H01L21/76832 , H01L21/76835 , H01L21/76885
摘要： A method for forming at least one barrierless, embedded metal structure comprising the following steps. A structure having a patterned dielectric layer formed thereover with at least one opening exposing at least one respective portion of the structure. Respective metal structures are formed within each respective opening. The first dielectric layer is removed to expose the top and at least a portion of the side walls of the respective at least one metal structure. A dielectric barrier layer is formed over the structure and the exposed top of the respective metal structure. A second, conformal dielectric layer is formed over the dielectric barrier layer to complete the respective barrierless at least one metal structure embedded within the second, conformal dielectric layer. The dielectric barrier layer preventing diffusion of the metal comprising the respective at least one metal structure into the second, conformal dielectric layer.
摘要翻译：一种形成至少一个无障碍嵌入金属结构的方法，包括以下步骤。具有形成在其上的图案化电介质层的结构，其中至少一个开口暴露出结构的至少一个相应部分。在每个相应的开口内形成相应的金属结构。去除第一电介质层以暴露相应的至少一个金属结构的顶部和至少一部分侧壁。介电阻挡层形成在相应的金属结构的结构和暴露的顶部上。在电介质阻挡层上方形成第二个保形介电层，以完成嵌入在第二保形电介质层内的相应无障碍的至少一个金属结构。电介质阻挡层防止包含相应的至少一种金属结构的金属扩散到第二保形电介质层中。

10. 发明申请

US20130088161A1 DRIVING CIRCUIT OF LIGHT EMITTING DIODE 有权
标题翻译：发光二极管的驱动电路
公开(公告)号：US20130088161A1
公开(公告)日：2013-04-11
申请号：US13267914
申请日：2011-10-07
申请人： Yung-Chen Lu
发明人： Yung-Chen Lu
IPC分类号： H05B37/02
CPC分类号： H05B33/0809 , H05B33/0824
摘要： A driving circuit of a light emitting diode (LED) including an AC power, a rectifier, a power converter, a waveform sampler, and a control circuit is provided. The AC power provides an AC signal. The rectifier is coupled to the AC power and outputs a driving signal. The power converter is coupled to the rectifier. The power converter includes an LED and outputs a first signal positive correlated with a current passing through the LED. The waveform sampler is coupled between the AC power and the rectifier, and outputs a second signal directly proportional to the AC signal. The control circuit is coupled between the waveform sampler and the power converter, and outputs a control signal to the power converter according to a comparison result between the first signal and the second signal.
摘要翻译：提供了包括交流电源，整流器，功率转换器，波形采样器和控制电路的发光二极管（LED）的驱动电路。交流电源提供交流信号。整流器耦合到AC电源并输出驱动信号。功率转换器耦合到整流器。功率转换器包括LED并输出与通过LED的电流正相关的第一信号。波形采样器耦合在交流电源和整流器之间，并输出与AC信号成正比的第二信号。控制电路耦合在波形采样器和功率转换器之间，并根据第一信号和第二信号之间的比较结果向控制信号输出功率转换器。

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