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    • 3. 发明授权
    • Clock reproduction circuit
    • 时钟再现电路
    • US06862332B2
    • 2005-03-01
    • US10467747
    • 2002-02-25
    • Ken'ichi Ejima
    • Ken'ichi Ejima
    • H04L7/033H03K21/00
    • H04L7/0331
    • A master clock signal source (10) generates a master clock signal having a frequency equal to N times the bit rate of received data, where N is a positive integer. A modulo-N counter (12) counts the master clock signal. An edge detecting circuit (4) detects a transition of the received data from a H level to a L level. A counter (8) counts the master clock signal and resets the modulo-N counter (12) if the count counted during a time period in which three edge representative signals occur is 2N. In accordance with the count in the modulo-N counter 12, a clock generating unit 14 generates a clock signal.
    • 主时钟信号源(10)产生具有等于接收数据的比特率的N倍的频率的主时钟信号,其中N是正整数。 模N计数器(12)对主时钟信号进行计数。 边缘检测电路(4)检测从H电平到L电平的接收数据的转变。 如果在发生三个边缘代表信号的时间段内计数的计数器为2N,则计数器(8)对主时钟信号进行计数并复位模N计数器(12)。 根据模N计数器12中的计数,时钟产生单元14产生时钟信号。