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1. 发明授权

US06356217B1 Enhanced DC offset correction through bandwidth and clock speed selection 有权
标题翻译：通过带宽和时钟速度选择增强直流偏移校正
公开(公告)号：US06356217B1
公开(公告)日：2002-03-12
申请号：US09515843
申请日：2000-02-29
申请人： Keith A. Tilley , Raul Salvi , Enrique Ferrer
发明人： Keith A. Tilley , Raul Salvi , Enrique Ferrer
IPC分类号： H03M110
CPC分类号： H03F1/304
摘要： A DC offset correction method and apparatus. In a DC offset correction loop (100), a DC offset is corrected using a binary search routine or any other digital or analog DC offset correction technique. In this binary search routine, the sign of the offset (138) is used to control a direction in which a digital to analog converter (DAC) (166) is stepped until the least significant bit of the DAC is set. The process is enhanced by opening up the bandwidth of the baseband filters (130) to permit the binary search to be clocked (180) at a higher clock rate. After the correction is established, the filters (130) are reset to normal operating conditions.
摘要翻译： DC偏移校正方法和装置。在DC偏移校正回路（100）中，使用二分搜索程序或任何其他数字或模拟DC偏移校正技术校正DC偏移。在该二进制搜索例程中，偏移量（138）的符号用于控制数模转换器（DAC）（166）的步进直到DAC的最低有效位被置位的方向。通过打开基带滤波器（130）的带宽来增强该过程，以允许二进制搜索以更高的时钟速率被计时（180）。在建立校正之后，将过滤器（130）复位到正常的操作条件。

2. 发明授权

US06317064B1 DC offset correction adaptable to multiple requirements 有权
标题翻译： DC偏移校正适应多种要求
公开(公告)号：US06317064B1
公开(公告)日：2001-11-13
申请号：US09515834
申请日：2000-02-29
申请人： Enrique Ferrer , James C. Goatley , Keith A. Tilley , Raul Salvi
发明人： Enrique Ferrer , James C. Goatley , Keith A. Tilley , Raul Salvi
IPC分类号： H03M110
CPC分类号： H03M1/004 , H03F1/304 , H03F3/45973 , H03M1/0607
摘要： A DC offset correction method and apparatus. Several DC offset correction schemes including a digital binary search scheme (100), a digital slow averaging scheme (200) and an analog integration (50) scheme are provided. A controller (160) selects one or more of the correction schemes in accordance with the desired characteristics provided by each scheme.
摘要翻译： DC偏移校正方法和装置。提供了包括数字二进制搜索方案（100），数字慢平均方案（200）和模拟积分（50）方案的多个DC偏移校正方案。控制器（160）根据每个方案提供的期望特性选择一个或多个校正方案。

3. 发明授权

US06225848B1 Method and apparatus for settling and maintaining a DC offset 有权
标题翻译：用于稳定和维持DC偏移的方法和装置
公开(公告)号：US06225848B1
公开(公告)日：2001-05-01
申请号：US09515286
申请日：2000-02-29
申请人： Keith A. Tilley , Raul Salvi , Enrique Ferrer , Atif A. Meraj , David J. Graham
发明人： Keith A. Tilley , Raul Salvi , Enrique Ferrer , Atif A. Meraj , David J. Graham
IPC分类号： H03K508
CPC分类号： H03F1/304 , H03F2200/372
摘要： A DC offset correction loop (200) utilizes a sign bit generator (204), binary search stage (206), and a digital-to-analog converter (208) in its feedback path to correct for DC offsets at the input of a gain stage (202). When a correction value is obtained, it is applied and held (524) to compensate for the DC offset. When a programming event occurs (534), such as detecting an increase in DC offset beyond a threshold, detecting a significant temperature change, or passage of time, a new DC offset correction cycle is initiated.
摘要翻译：直流偏移校正回路（200）利用符号位产生器（204），二进制搜索级（206）和数模转换器（208）在其反馈路径中校正增益输入端的直流偏移阶段（202）。当获得校正值时，施加和保持（524）以补偿DC偏移。当发生编程事件（534）时，例如检测DC偏移的增加超过阈值，检测明显的温度变化或时间的流逝，则开始新的DC偏移校正周期。

4. 发明授权

US6114980A Method and apparatus for settling a DC offset 有权
标题翻译：沉降直流偏移的方法和装置
公开(公告)号：US6114980A
公开(公告)日：2000-09-05
申请号：US290564
申请日：1999-04-13
申请人： Keith A. Tilley , Raul Salvi , Enrique Ferrer
发明人： Keith A. Tilley , Raul Salvi , Enrique Ferrer
IPC分类号： H03F1/30 , H03M1/10
CPC分类号： H03F1/304 , H03F2200/372
摘要： A DC offset correction loop (200) utilizes a sign bit generator (204), binary search stage (206), and a digital-to-analog converter (208) in its feedback path to correct for DC offsets at the input of a gain stage (202).
摘要翻译：直流偏移校正回路（200）利用符号位产生器（204），二进制搜索级（206）和数模转换器（208）在其反馈路径中校正增益输入端的直流偏移阶段（202）。

5. 发明授权

US07720448B2 Signal generation power management control system for portable communications device and method of using same 有权
标题翻译：用于便携式通信设备的信号发生电力管理控制系统及其使用方法
公开(公告)号：US07720448B2
公开(公告)日：2010-05-18
申请号：US10748735
申请日：2003-12-30
申请人： Raul Salvi , Cesar Carralero , Steven P. Hoggarth
发明人： Raul Salvi , Cesar Carralero , Steven P. Hoggarth
IPC分类号： H04B1/04
CPC分类号： H03G3/30 , G11B20/10
摘要： A signal generation power management control system (100) for use in a portable communications device includes a digital signal processor (DSP) (101) for processing a digital source input and providing a digital processed bit stream A digital-to-analog converter (DAC) (103) is used for converting the digital processed bit stream to provide an analog signal. A power management controller (115) within the DSP (101) is then used for interpreting control parameters of signal processing components used within the portable communications device and dynamically adjusting the bias current of these components based on minimal signal requirements of the analog signal.
摘要翻译：一种用于便携式通信设备的信号发生功率管理控制系统（100）包括用于处理数字源输入并提供数字处理比特流A的数字信号处理器（DSP）（101）数模转换器）（103）用于转换数字处理比特流以提供模拟信号。然后，DSP（101）内的电源管理控制器（115）用于解释在便携式通信设备内使用的信号处理组件的控制参数，并且基于模拟信号的最小信号要求来动态调整这些组件的偏置电流。

6. 发明申请

US20080298495A1 METHOD AND APPARATUS FOR GENERATING CORRECTED QUADRATURE PHASE SIGNAL PAIRS IN A COMMUNICATION DEVICE 有权
标题翻译：用于在通信设备中产生校正的相位信号对的方法和装置
公开(公告)号：US20080298495A1
公开(公告)日：2008-12-04
申请号：US11755540
申请日：2007-05-30
申请人： Raul Salvi , Pedro J. Landin
发明人： Raul Salvi , Pedro J. Landin
IPC分类号： H04L27/00
CPC分类号： H04L27/364
摘要： A method and an apparatus (300) for generating corrected quadrature phase signal pairs in a communication device are provided. The apparatus (300) includes a quadrature phase generator (310), programmable delay elements (320, 330) and a control circuit (360). The programmable delay elements (320, 330) receive a quadrature phase signal pair (signals I 312 and Q 314) from the quadrature phase generator (310). The control circuit (360) generates a control signal (362) based on outputs (325, 335) of the programmable delay elements (320, 330). The control signal (362) configures the programmable delay elements (320, 330). The programmable delay elements (320, 330) are configured to adjust delay between the signals I (312) and Q (314). The programmable delay elements (320, 330) are also used to adjust duty cycle for the quadrature phase signal pair to provide the corrected quadrature phase signal pair.
摘要翻译：提供一种用于在通信设备中产生校正的正交相位信号对的方法和装置（300）。装置（300）包括正交相位发生器（310），可编程延迟元件（320,330）和控制电路（360）。可编程延迟元件（320,330）从正交相位发生器（310）接收正交相位信号对（信号I 312和Q 314）。控制电路（360）基于可编程延迟元件（320,330）的输出（325,335）产生控制信号（362）。控制信号（362）配置可编程延迟元件（320,330）。可编程延迟元件（320,330）被配置为调整信号I（312）和Q（314）之间的延迟。可编程延迟元件（320,330）也用于调整正交相位信号对的占空比以提供校正的正交相位信号对。

7. 发明授权

US5697068A System and method for providing a non-invasively tunable transceiver synthesizer 失效
标题翻译：用于提供非侵入式可调谐收发器合成器的系统和方法
公开(公告)号：US5697068A
公开(公告)日：1997-12-09
申请号：US490876
申请日：1995-06-15
申请人： Raul Salvi , John Wetters , Wayne Phang
发明人： Raul Salvi , John Wetters , Wayne Phang
IPC分类号： H03B1/00 , H03C3/09 , H03L7/18 , H04B1/40
CPC分类号： H03C3/0983 , H03C3/0941 , H03C3/0958 , H03C3/0966 , H03L7/18 , H04B1/40 , H03B2201/0208
摘要： A transceiver synthesizer includes components that enable it to be tuned non-invasively by software. The transceiver synthesizer includes a non-volatile memory (30) that can be non-invasively programmed with a digital value for each of a number of tuning variables. The digital values are converted by digital to analog converters (37, 38, 39) into tuning voltages. The tuning voltages are applied to voltage variable devices (60, 80, 95) that respond to changes in the applied tuning voltage to vary an operating characteristic thereof. The operating characteristics of the voltage variable devices (60, 80, 95) are non-invasively adjustable to tune the transceiver synthesizer for high and low port modulation deviation, reference oscillator make tolerance, automatic frequency control, reference oscillator temperature compensation etc.
摘要翻译：收发器合成器包括能够通过软件非侵入性地调整的组件。收发器合成器包括非易失性存储器（30），其可以用多个调谐变量中的每一个的数字值进行非侵入式编程。数字值由数模转换器（37,38,39）转换成调谐电压。调谐电压被施加到对施加的调谐电压的变化作出响应以改变其工作特性的电压可变器件（60,80,95）。电压可变器件（60,80,95）的工作特性是非侵入式可调的，以调谐收发器合成器的高低端调制偏差，参考振荡器允差，自动频率控制，参考振荡器温度补偿等。

8. 发明授权

US5557244A Dual port phase and magnitude balanced synthesizer modulator and method for a transceiver 失效
标题翻译：双端口相位和幅度平衡合成器调制器和收发器的方法
公开(公告)号：US5557244A
公开(公告)日：1996-09-17
申请号：US427677
申请日：1995-04-24
申请人： Raul Salvi
发明人： Raul Salvi
IPC分类号： H03C3/09 , H03L3/00 , H03D3/00 , H03L7/06 , H03L7/099
CPC分类号： H03C3/0966 , H03C3/0941 , H03C3/0958
摘要： A transceiver (10) includes a dual port phase and magnitude balanced synthesizer modulator (60). The modulator (60) couples a modulation input to a voltage controlled oscillator (40) and to a reference oscillator (42) that are coupled together in a phase locked loop (44). The modulator 60 includes a magnitude balancing circuit (64) that divides a modulation input representing data or the like into a first modulation input signal applied to the reference oscillator (42) and a second modulation input signal for the voltage controlled oscillator (40). A phase balancing circuit (68) induces a negative phase shift in the second modulation input signal that is coupled to the voltage controlled oscillator (40) in order to compensate for the phase lag of the reference oscillator loop (44).
摘要翻译：收发器（10）包括双端口相位和幅度平衡合成器调制器（60）。调制器（60）将调制输入耦合到压控振荡器（40）和耦合到锁相环（44）中的基准振荡器（42）。调制器60包括：幅度平衡电路（64），其将表示数据等的调制输入划分为施加到参考振荡器（42）的第一调制输入信号和用于压控振荡器（40）的第二调制输入信号。相位平衡电路（68）在耦合到压控振荡器（40）的第二调制输入信号中引起负相移，以便补偿参考振荡器回路（44）的相位滞后。

9. 发明授权

US08554267B2 Broadband input frequency adaptive technique for filter tuning and quadrature generation 有权
标题翻译：用于滤波器调谐和正交生成的宽带输入频率自适应技术
公开(公告)号：US08554267B2
公开(公告)日：2013-10-08
申请号：US12647476
申请日：2009-12-26
申请人： Raul Salvi
发明人： Raul Salvi
IPC分类号： H04B1/10 , H04B1/18 , H04B1/16
CPC分类号： H03H11/16
摘要： A method for tuning a filter is provided. The amplitude of a first signal (I1) is compared with the amplitude of a comparison signal. The first signal is generated with a first filter, which receives a first input signal, and there is a phase difference between the first signal (I1) and the comparison signal. A tuning signal is then generated based on differences between the amplitudes of the first signal (I1) and the comparison signal. The tuning signal compensates for any phase and/or amplitude offset in the first signal (I1).
摘要翻译：提供了一种用于调整过滤器的方法。将第一信号（I1）的幅度与比较信号的振幅进行比较。第一信号由接收第一输入信号的第一滤波器产生，并且在第一信号（I1）和比较信号之间存在相位差。然后基于第一信号（I1）和比较信号的振幅之间的差异产生调谐信号。调谐信号补偿第一信号（I1）中的任何相位和/或幅度偏移。

10. 发明申请

US20120074996A1 METHOD AND APPARATUS FOR CORRECTING PHASE OFFSET ERRORS IN A COMMUNICATION DEVICE 有权
标题翻译：用于校正通信设备中的相位偏移误差的方法和装置
公开(公告)号：US20120074996A1
公开(公告)日：2012-03-29
申请号：US12893266
申请日：2010-09-29
申请人： Geetha B. Nagaraj , Thomas R. Harrington , Raul Salvi
发明人： Geetha B. Nagaraj , Thomas R. Harrington , Raul Salvi
IPC分类号： H03L7/06
CPC分类号： H03L7/083 , H03L7/0891 , H03L7/101
摘要： A frequency synthesizer that utilizes locked loop circuitry, for example delay locked loop and/or phase locked loop circuits is provided with a means for minimizing static phase/delay errors. An auto-tuning circuit and technique provide a measurement of static phase error by integrating the static phase error in the DLL/PLL circuit. A correction value is determined and applied as a current at the charge pump or as a time/phase offset at the phase detector to minimize static phase error. During normal operation the DLL/PLL is operated with the correction value resulting in substantially reduced spur levels and/or improved settling time.
摘要翻译：使用锁相环电路（例如延迟锁定环路和/或锁相环路电路）的频率合成器具有用于最小化静态相位/延迟误差的装置。自动调谐电路和技术通过在DLL / PLL电路中积分静态相位误差来提供静态相位误差的测量。校正值被确定并应用于电荷泵处的电流或作为相位检测器处的时间/相位偏移，以使静态相位误差最小化。在正常操作期间，使用校正值来操作DLL / PLL，从而导致显着降低的刺激水平和/或改善的建立时间。

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