专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08310248B2 Capacitive sensor device 有权
标题翻译：电容传感器装置
公开(公告)号：US08310248B2
公开(公告)日：2012-11-13
申请号：US12656542
申请日：2010-02-02
申请人： Keisuke Gotoh , Kentaro Mizuno , Norikazu Ohta
发明人： Keisuke Gotoh , Kentaro Mizuno , Norikazu Ohta
IPC分类号： G01R27/26
CPC分类号： G01L9/12 , G01D1/00 , G01D15/00 , G01D21/00 , G01H11/06 , G01P15/125
摘要： A capacitive sensor device includes first and second sensor capacitors coupled in series, a clock signal generating part, an operational amplifier, a feedback capacitor, a compensating capacitor, and a compensating signal generating part. The clock signal generating part generates a first clock signal and the second clock signal applied to the first and second sensor capacitors, respectively. The compensating signal generating part generates a compensating signal applied to the compensating capacitor. The first clock signal and the second clock signal have the same frequency and the same amplitude and have phases being opposite each other. The compensating signal has a frequency same as the first clock signal and the second clock signal, has a phase same as one of the first clock signal and the second clock signal, and has an amplitude that is adjustable.
摘要翻译：电容传感器装置包括串联耦合的第一传感器电容器和第二传感器电容器，时钟信号产生部件，运算放大器，反馈电容器，补偿电容器和补偿信号产生部件。时钟信号产生部分分别产生施加到第一和第二传感器电容器的第一时钟信号和第二时钟信号。补偿信号生成部生成施加到补偿电容器的补偿信号。第一时钟信号和第二时钟信号具有相同的频率和相同的幅度并且具有彼此相反的相位。补偿信号具有与第一时钟信号和第二时钟信号相同的频率，具有与第一时钟信号和第二时钟信号中的一个相同的相位，并且具有可调整的幅度。

2. 发明申请

US20100219848A1 Capacitive sensor device 有权
标题翻译：电容传感器装置
公开(公告)号：US20100219848A1
公开(公告)日：2010-09-02
申请号：US12656542
申请日：2010-02-02
申请人： Keisuke Gotoh , Kentaro Mizuno , Norikazu Ohta
发明人： Keisuke Gotoh , Kentaro Mizuno , Norikazu Ohta
IPC分类号： G01R27/26
CPC分类号： G01L9/12 , G01D1/00 , G01D15/00 , G01D21/00 , G01H11/06 , G01P15/125
摘要： A capacitive sensor device includes first and second sensor capacitors coupled in series, a clock signal generating part, an operational amplifier, a feedback capacitor, a compensating capacitor, and a compensating signal generating part. The clock signal generating part generates a first clock signal and the second clock signal applied to the first and second sensor capacitors, respectively. The compensating signal generating part generates a compensating signal applied to the compensating capacitor. The first clock signal and the second clock signal have the same frequency and the same amplitude and have phases being opposite each other. The compensating signal has a frequency same as the first clock signal and the second clock signal, has a phase same as one of the first clock signal and the second clock signal, and has an amplitude that is adjustable.
摘要翻译：电容传感器装置包括串联耦合的第一传感器电容器和第二传感器电容器，时钟信号产生部件，运算放大器，反馈电容器，补偿电容器和补偿信号产生部件。时钟信号产生部分分别产生施加到第一和第二传感器电容器的第一时钟信号和第二时钟信号。补偿信号生成部生成施加到补偿电容器的补偿信号。第一时钟信号和第二时钟信号具有相同的频率和相同的幅度并且具有彼此相对的相位。补偿信号具有与第一时钟信号和第二时钟信号相同的频率，具有与第一时钟信号和第二时钟信号中的一个相同的相位，并且具有可调整的幅度。

3. 发明授权

US08008948B2 Peak voltage detector circuit and binarizing circuit including the same circuit 有权
标题翻译：峰值电压检测电路和二值化电路包括相同电路
公开(公告)号：US08008948B2
公开(公告)日：2011-08-30
申请号：US12000304
申请日：2007-12-11
申请人： Yasuaki Makino , Hiroshi Okada , Reiji Iwamoto , Nobukazu Oba , Shinji Nakatani , Norikazu Ohta , Hideki Hosokawa
发明人： Yasuaki Makino , Hiroshi Okada , Reiji Iwamoto , Nobukazu Oba , Shinji Nakatani , Norikazu Ohta , Hideki Hosokawa
IPC分类号： G01R19/00 , G06M1/10
CPC分类号： G01R19/04
摘要： A peak voltage detector circuit detects a peak voltage of an input voltage. The input voltage is input into a first input terminal of a comparator. A counter circuit counts up a counter value in synchronization with a first clock signal, when a signal output from the comparator is in a first state. The counter circuit counts down the counter value in synchronization with a second clock signal. A digital-analog conversion circuit outputs an output voltage corresponding to the counter value, and the output voltage is input into a second input terminal of the comparator. The first clock signal has a wave period shorter than that of the second clock signal.
摘要翻译：峰值电压检测电路检测输入电压的峰值电压。输入电压被输入到比较器的第一输入端。当从比较器输出的信号处于第一状态时，计数器电路与第一时钟信号同步地计数计数器值。计数器电路与第二个时钟信号同步地计数计数器值。数字模拟转换电路输出对应于计数器值的输出电压，输出电压被输入到比较器的第二输入端。第一时钟信号具有比第二时钟信号短的波周期。

4. 发明申请

US20090002033A1 Noise removal circuit and comparator circuit including same 审中-公开
标题翻译：除噪电路和比较电路包括相同
公开(公告)号：US20090002033A1
公开(公告)日：2009-01-01
申请号：US12213893
申请日：2008-06-26
申请人： Shinji Nakatani , Nobukazu Oba , Norikazu Ohta , Hideki Hosokawa
发明人： Shinji Nakatani , Nobukazu Oba , Norikazu Ohta , Hideki Hosokawa
IPC分类号： H03K5/22
CPC分类号： H03K5/1252 , H03K5/086
摘要： The present invention reliably removes a signal change associated with a noise component from a comparison signal of a comparator. A comparator circuit includes a comparator and a timer circuit. After a reversal of the comparison signal, if the level of the comparator is sustained at least from a first time to a second time, an output signal is reversed and output. The timer circuit includes a memory unit that is shifted to a memory state in which the reversal of the comparison signal is stored at the first time if the reversal is verified. If the comparison signal is reversed during the interval between the first time and second time, the memory state is cleared.
摘要翻译：本发明可以从比较器的比较信号可靠地去除与噪声分量相关联的信号变化。比较器电路包括比较器和定时器电路。在比较信号反转之后，如果比较器的电平至少从第一时间持续到第二时间，则输出信号被反转并输出。定时器电路包括一个存储器单元，该存储器单元被转移到如果反转被验证则在第一时间存储比较信号的反转的存储器状态。如果在第一次和第二次之间的间隔期间比较信号反转，则存储器状态被清除。

5. 发明申请

US20080048641A1 Peak voltage detector circuit and binarizing circuit including the same circuit 审中-公开
标题翻译：峰值电压检测电路和二值化电路包括相同电路
公开(公告)号：US20080048641A1
公开(公告)日：2008-02-28
申请号：US11822291
申请日：2007-07-03
申请人： Yasuaki Makino , Hiroshi Okada , Reiji Iwamoto , Norikazu Ohta , Hideki Hosokawa
发明人： Yasuaki Makino , Hiroshi Okada , Reiji Iwamoto , Norikazu Ohta , Hideki Hosokawa
IPC分类号： G01R19/04
CPC分类号： G01R19/04
摘要： A peak voltage detector circuit detects a peak voltage of an input voltage. The input voltage is input into a first input terminal of a comparator. A counter circuit counts up a counter value in synchronization with a first clock signal, when a signal output from the comparator is in a first state. The counter circuit counts down the counter value in synchronization with a second clock signal. A digital-analog conversion circuit outputs an output voltage corresponding to the counter value, and the output voltage is input into a second input terminal of the comparator. The first clock signal has a wave period shorter than that of the second clock signal.
摘要翻译：峰值电压检测电路检测输入电压的峰值电压。输入电压被输入到比较器的第一输入端。当从比较器输出的信号处于第一状态时，计数器电路与第一时钟信号同步地计数计数器值。计数器电路与第二个时钟信号同步地计数计数器值。数字模拟转换电路输出对应于计数器值的输出电压，输出电压被输入到比较器的第二输入端。第一时钟信号具有比第二时钟信号短的波周期。

6. 发明申请

US20070146072A1 Clock signal output circuit 有权
标题翻译：时钟信号输出电路
公开(公告)号：US20070146072A1
公开(公告)日：2007-06-28
申请号：US11604198
申请日：2006-11-27
申请人： Norikazu Ohta , Yoshie Ohira , Yasuaki Makino , Hiromi Ariyoshi
发明人： Norikazu Ohta , Yoshie Ohira , Yasuaki Makino , Hiromi Ariyoshi
IPC分类号： H03F3/45
CPC分类号： H03K3/354 , H03K3/0315 , H03K2005/0013 , H03K2005/00143 , H03K2005/00169
摘要： 1st to nth pairs of transistors (n=an odd number) are connected in parallel, and each pair of transistors has an upper transistor and a lower transistor connected in series. A point between the upper transistor and the lower transistor of a preceding pair of transistors is connected to a gate of the lower transistor of a subsequent transistor, and the point between the upper transistor and the lower transistor of nth pair of transistors is connected to the gate of the first lower transistor. A capacitor is inserted between the lower transistor and a direct power source. A current regulating circuit connected to gates of the upper transistors, wherein the current regulating circuit supplies a gate voltage to each gate of the each upper transistor. The magnitude of the gate voltage is adjusted such that a magnitude of current that flows between the source and drain of the upper transistor due to the gate voltage is proportional to a voltage between the source and gate of the corresponding lower transistor when the lower transistor is turned on.
摘要翻译：并联连接第n个第n个（n =奇数）对的第一个第一和第二个晶体管，每对晶体管具有串联连接的上部晶体管和下部晶体管。先前一对晶体管的上部晶体管和下部晶体管之间的点连接到后续晶体管的下部晶体管的栅极，并且上部晶体管和下部晶体管之间的点位于第n / >一对晶体管连接到第一下晶体管的栅极。电容器插在下晶体管和直接电源之间。连接到上部晶体管的栅极的电流调节电路，其中电流调节电路向每个上部晶体管的每个栅极提供栅极电压。调整栅极电压的大小，使得由于栅极电压而在上部晶体管的源极和漏极之间流动的电流的大小与当下部晶体管为相应的下部晶体管的源极和栅极之间的电压成比例时打开。

7. 发明授权

US07233136B2 Circuit for outputting stable reference voltage against variation of background temperature or variation of voltage of power source 有权
标题翻译：用于输出稳定的参考电压的电路，以抵抗背景温度的变化或电源电压的变化
公开(公告)号：US07233136B2
公开(公告)日：2007-06-19
申请号：US11311182
申请日：2005-12-20
申请人： Yasuaki Makino , Norikazu Ohta , Yoshie Ohira , Hirofumi Funabashi
发明人： Yasuaki Makino , Norikazu Ohta , Yoshie Ohira , Hirofumi Funabashi
IPC分类号： G05F3/16 , G05F3/20
CPC分类号： G05F3/30
摘要： A reference voltage circuit includes an operational amplifier, a first fixed resistance resistor, a second fixed resistance resistor, a third fixed resistance resistor, a first diode and a second diode. The reference voltage circuit further includes a fourth fixed resistance resistor having an end connected to a non-inverting input terminal of the operational amplifier and the other end connected to the first diode. The reference voltage circuit is characterized by a value of the resistance of the fourth resistor being less than the resistance of the first resistor and a temperature coefficient of the fourth resistor being greater than any of the temperature coefficients of the first, second and third resistors.
摘要翻译：参考电压电路包括运算放大器，第一固定电阻电阻，第二固定电阻电阻，第三固定电阻电阻，第一二极管和第二二极管。参考电压电路还包括第四固定电阻电阻器，其端部连接到运算放大器的非反相输入端子，另一端连接到第一二极管。参考电压电路的特征在于第四电阻器的电阻小于第一电阻器的电阻值，第四电阻器的温度系数大于第一，第二和第三电阻器的任何温度系数。

8. 发明授权

US06744258B2 Capacitive sensor apparatus 有权
标题翻译：电容传感器装置
公开(公告)号：US06744258B2
公开(公告)日：2004-06-01
申请号：US10189565
申请日：2002-07-08
申请人： Seiichiro Ishio , Yasutoshi Suzuki , Hajime Ito , Yasuaki Makino , Norikazu Ohta , Keiichi Shimaoka , Hirofumi Funabashi
发明人： Seiichiro Ishio , Yasutoshi Suzuki , Hajime Ito , Yasuaki Makino , Norikazu Ohta , Keiichi Shimaoka , Hirofumi Funabashi
IPC分类号： G01R3112
CPC分类号： G01D3/08
摘要： In a capacitive sensor apparatus, a capacitive sensor includes a plurality of physical-quantity-detection capacitors each having a movable electrode and a fixed electrode. A conversion device operates for converting an output signal of the capacitive sensor into an apparatus output signal. Each of the physical-quantity-detection capacitors is selectively connected and disconnected to and from the conversion device. A determination is made as to whether or not each of the physical-quantity-detection capacitors fails in response to the sensor output signal. When it is determined that a first one of the physical-quantity-detection capacitors fails, the first one is disconnected from the conversion device and a second one of the physical-quantity-detection capacitors is connected to the conversion device.
摘要翻译：在电容传感器装置中，电容式传感器包括多个物理量检测电容器，每个物理量检测电容器具有可动电极和固定电极。转换装置用于将电容式传感器的输出信号转换成装置输出信号。每个物理量检测电容器被选择性地连接到转换装置和从转换装置断开。确定每个物理量检测电容器是否响应于传感器输出信号而失败。当确定物理量检测电容器中的第一个电容器发生故障时，第一个物理量检测电容器与转换装置断开连接，并且第二个物理量检测电容器连接到转换装置。

9. 发明授权

US5245346A Interrogator/transponder system and mobile transponder device 失效
标题翻译： INTERROGATOR / TRANSPONDER系统和移动传输器设备
公开(公告)号：US5245346A
公开(公告)日：1993-09-14
申请号：US743340
申请日：1991-08-28
申请人： Yoshihiro Nishimura , Kazuhiro Kozuka , Hidehiro Tomioka , Shin Yamamoto , Norikazu Ohta , Yoshihisa Harata , Souichi Isikawa , Takehiko Okuda
发明人： Yoshihiro Nishimura , Kazuhiro Kozuka , Hidehiro Tomioka , Shin Yamamoto , Norikazu Ohta , Yoshihisa Harata , Souichi Isikawa , Takehiko Okuda
IPC分类号： G01S13/82 , G07B15/06
CPC分类号： G07B15/063 , G01S13/825
摘要： An interrogation responder system composed of a transmitter stationarily mounted in a certain fixed place and a receiver mounted on a mobile object. The receiver on the mobile side starts the operation when a power is supplied to the entire circuit in accordance with a wake-up signal from the transmitter on the fixed side so as to modulate the electromagnetic signal emitted from the transmitter on the fixed side in accordance with a predetermined code and reflect a response. This enables continuing bilateral communication of a command, data and so forth. By starting communication between the transmitter and the receiver by a direct wave of a carrier signal in a microwave band after sensing that the receiver on the mobile side has entered a good communication zone, secure communication is enabled at a sufficient electric field strength.
摘要翻译： PCT No.PCT / JP90 / 01249 Sec。 371日期1991年8月28日 102（e）日期1991年8月28日PCT提交1990年9月28日PCT公布。出版物WO91 / 10290 日期1991年7月11日。一个询问响应者系统由固定安装在某个固定位置的发射器和安装在移动物体上的接收器组成。根据来自固定侧的发射机的唤醒信号向整个电路提供电力，移动侧的接收机开始操作，以便根据固定侧调制从固定侧的发射机发射的电磁信号具有预定的代码并反映出响应。这使得能够持续双向地通信命令，数据等。通过在感测到移动侧的接收机已经进入良好的通信区域之后，通过微波频带中的载波信号的直接波开始发射机和接收机之间的通信，在足够的电场强度下实现安全通信。

10. 发明申请

US20080211544A1 Peak voltage detector circuit and binarizing circuit including the same circuit 有权
公开(公告)号：US20080211544A1
公开(公告)日：2008-09-04
申请号：US12000304
申请日：2007-12-11
申请人： Yasuaki Makino , Hiroshi Okada , Reiji Iwamoto , Nobukazu Oba , Shinji Nakatani , Norikazu Ohta , Hideki Hosokawa
发明人： Yasuaki Makino , Hiroshi Okada , Reiji Iwamoto , Nobukazu Oba , Shinji Nakatani , Norikazu Ohta , Hideki Hosokawa
IPC分类号： H03K5/1532
CPC分类号： G01R19/04
摘要： A peak voltage detector circuit detects a peak voltage of an input voltage. The input voltage is input into a first input terminal of a comparator. A counter circuit counts up a counter value in synchronization with a first clock signal, when a signal output from the comparator is in a first state. The counter circuit counts down the counter value in synchronization with a second clock signal. A digital-analog conversion circuit outputs an output voltage corresponding to the counter value, and the output voltage is input into a second input terminal of the comparator. The first clock signal has a wave period shorter than that of the second clock signal.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式