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    • 1. 发明授权
    • Latch circuit for amplifying an analog signal and converting an analog
signal into a digital signal
    • 用于放大模拟信号并将模拟信号转换为数字信号的锁存电路
    • US5719513A
    • 1998-02-17
    • US699808
    • 1996-08-20
    • Keiichi KusumotoKenji MurataAkira Matsuzawa
    • Keiichi KusumotoKenji MurataAkira Matsuzawa
    • H03K3/012H03K3/037
    • H03K3/037H03K3/012
    • The present invention discloses an improved latch circuit. In the latch circuit, a composite gate takes in a basic clock signal and a delayed clock signal which is delayed by a delay circuit for a specific amount with respect to the basic clock signal, and puts out to a second drive circuit a first signal identical in waveform with the basic block signal, and further puts out to a first drive circuit a second signal that is delayed in the rising timing with respect to the first signal. As a result of such arrangement, when a transition is made from a feedback period during which an input switch has an off state while a feedback switch has an on state to a sampling period during which the input switch has an on state while the feedback switch has an off state, neither the input switch nor the feedback switch has an on state.
    • 本发明公开了一种改进的锁存电路。 在锁存电路中,复合栅极接收基本时钟信号和相对于基本时钟信号延迟特定量的延迟电路的延迟时钟信号,并向第二驱动电路输出相同的第一信号 具有基本块信号的波形,并且进一步向第一驱动电路输出相对于第一信号在上升定时中延迟的第二信号。 作为这种布置的结果,当反馈开关具有断开状态的反馈周期转变到反馈开关具有接通状态到输入开关处于导通状态的采样周期,而反馈开关 具有断开状态,输入开关和反馈开关都不具有导通状态。
    • 3. 发明授权
    • Analog memory circuit and method for recording analog signal
    • 模拟记忆电路和记录模拟信号的方法
    • US5717624A
    • 1998-02-10
    • US739867
    • 1996-10-31
    • Keiichi KusumotoKenji MurataYutaka TeradaAkira Matsuzawa
    • Keiichi KusumotoKenji MurataYutaka TeradaAkira Matsuzawa
    • G11C27/02G11C27/00
    • G11C27/026
    • An analog memory circuit of the present invention includes: a recording circuit for recording and holding an input analog signal as a charge and for reading out the analog signal after deterioration of the analog signal caused by leakage of the charge in a holding operation is eliminated; a selecting circuit for controlling an operation of the recording circuit; and a driving circuit for supplying a predetermined constant voltage to the recording circuit, wherein the recording circuit includes: an input/output terminal for inputting and outputting the analog signal; a first capacitor having a first electrode and a second electrode, for recording and holding the analog signal as the charge; and a second capacitor connected between the second electrode of the first capacitor and a reference potential, for holding a charge leaked from the first capacitor, and wherein an amount of charge corresponding to an amount of leaked charge held in the second capacitor is restored to the first capacitor with predetermined timing.
    • 本发明的模拟存储器电路包括:记录电路,用于记录和保持作为电荷的输入模拟信号,并且用于在由保持操作中的电荷泄漏引起的模拟信号劣化后读出模拟信号; 用于控制记录电路的操作的选择电路; 以及用于向所述记录电路提供预定的恒定电压的驱动电路,其中所述记录电路包括:用于输入和输出所述模拟信号的输入/输出端子; 具有第一电极和第二电极的第一电容器,用于记录和保持模拟信号作为电荷; 以及连接在第一电容器的第二电极和参考电位之间的第二电容器,用于保持从第一电容器泄漏的电荷,并且其中对应于保持在第二电容器中的泄漏电荷量的电荷量恢复到 具有预定定时的第一电容器。
    • 5. 发明授权
    • Robot
    • 机器人
    • US06917856B2
    • 2005-07-12
    • US10343913
    • 2002-04-12
    • Kenji Murata
    • Kenji Murata
    • B25J9/16B25J9/18B25J19/00G05B19/04G05B19/18
    • B25J9/1674G05B2219/40218
    • It is constructed so as to detect a joint movement position of a robot arm by a position detector and a joint movement speed is calculated from change amounts of the joint movement position and elapsed time and is compared with an allowable movement speed and unlocking and locking of a brake are controlled so that the joint movement speed of an arm at the time of brake unlocking becomes within a constant value even when a shape, an attitude and a load condition of the robot arm vary. Therefore, movement work of the arm by the brake unlocking can be performed alone and a robot with high safety can be obtained.
    • 其结构是通过位置检测器检测机器人手臂的关节运动位置,并且根据关节运动位置和经过时间的变化量计算关节运动速度,并将其与允许的运动速度进行比较并解锁和锁定 控制制动器,使得即使当机器人手臂的形状,姿态和负载条件变化时,制动器解锁时的臂的关节移动速度也变为恒定值。 因此,可以单独执行通过制动器解锁的臂的移动工作,并且可以获得具有高安全性的机器人。
    • 6. 发明授权
    • Sub woofer system
    • 次低音扬声器系统
    • US06771784B2
    • 2004-08-03
    • US09926319
    • 2002-01-09
    • Kenji Murata
    • Kenji Murata
    • H03G500
    • H04R1/26H04R3/04H04R3/14
    • A sub woofer system is constituted of a real time digital signal processing part 5 that includes an A/D converter 5a, a low pass filter block 5b, a delay block 5c, and a D/A converter block 5d, an analog power amplifier 6 and a speaker 7. The length of delay time of the delay block 5c is set so that the length of group delay time of the digital signal processing part 5 may equal an integral multiple of the length of time corresponding to one wavelength of the crossover point frequency between the digital signal processing part 5 and a main speaker 4. The signal processing is performed under the conditions that have been set as such. In this case, a construction is made up wherein the length of a group delay time produced in the digital type real time digital signal processing part can be set to a given value. By this construction, it is possible to provide a sub woofer system which can improve the phase interference between the main speaker and the sub woofer system at the crossover point between the two.
    • 低音扬声器系统由包括A / D转换器5a,低通滤波器块5b,延迟块5c和D / A转换器块5d的实时数字信号处理部分5构成,模拟功率放大器6 和扬声器7.延迟块5c的延迟时间的长度被设置为使得数字信号处理部分5的组延迟时间的长度可以等于与交叉点的一个波长相对应的时间长度的整数倍 在数字信号处理部分5和主扬声器4之间的频率。信号处理在已被设置为这样的条件下执行。 在这种情况下,构成了数字型实时数字信号处理部中产生的群延迟时间的长度可以设定为给定值的结构。 通过这种结构,可以提供一种可以在两者之间的交叉点改善主扬声器和次低音扬声器系统之间的相位干扰的次低音扬声器系统。