会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 2. 发明授权
    • Microwave plasma film deposition system
    • 微波等离子体膜沉积系统
    • US5125358A
    • 1992-06-30
    • US384699
    • 1989-07-25
    • Tetsuya UedaNaoki SuzukiKohsaku Yano
    • Tetsuya UedaNaoki SuzukiKohsaku Yano
    • C23C16/511H01J37/32
    • H01J37/32211C23C16/511H01J37/32192H01J37/32678
    • A microwave plasma film deposition system comprises a waveguide for feeding microwaves through a microwave feeding window provided at one end of the waveguide, and a plasma cavity in communication with the other end of the waveguide and having a discharge gas inlet which is not in communication with the waveguide. The system further includes a specimen chamber which is in communication with the plasma cavity and which has a substrate setting rest therein and a material gas inlet, and a magnetic field applying device provided near the plasma cavity. Stable film deposition occurs because the plasma cavity is at the end of the waveguide which is remote from the microwave feeding window, whereby deposition on the microwave feeding window is prevented. Deposition on the microwave feeding window is further prevented by a ferromagnetic material which is placed around the waveguide and which reduces the strength of the magnetic field in the waveguide.
    • 微波等离子体膜沉积系统包括用于通过设置在波导的一端处的微波馈电窗口馈送微波的波导和与波导的另一端连通的等离子体腔,并且具有不与 波导。 该系统还包括与等离子体空腔连通并且具有衬底固定在其中的试样室和材料气体入口,以及设置在等离子体腔附近的磁场施加装置。 发生稳定的膜沉积,因为等离子体空腔位于远离微波馈电窗口的波导的末端,从而防止微波馈电窗口上的沉积。 通过放置在波导周围的铁磁材料进一步防止微波馈电窗上的沉积,并降低波导中的磁场的强度。
    • 3. 发明授权
    • Solid state imager
    • 固态成像仪
    • US4661830A
    • 1987-04-28
    • US626730
    • 1984-07-02
    • Yoshio OhtaTakao ChikamuraYutaka MiyataKohsaku YanoShinji Fujiwara
    • Yoshio OhtaTakao ChikamuraYutaka MiyataKohsaku YanoShinji Fujiwara
    • H01L27/146H01L27/14H01L29/78H01L31/00
    • H01L27/14672
    • This invention discloses a high efficiency solid state imager combining a semiconductor substrate having a charge transfer function and a photoelectric conversion film, wherein a high frequency transfer pulse having a frequency higher than that of a vertical transfer pulse is applied for a prescribed time during the vertical blanking period; voltages with different values are applied to a transparent electrode provided on the above-mentioned photoelectric conversion film in the first and second period of the period with the presence of the above-mentioned high frequency transfer pulse; and a voltage differing with each field is applied to the above-mentioned transparent electrode during the vertical blanking period, whereby blooming, highlight lag and flicker due to an intense light are considerably suppressed.
    • 本发明公开了一种组合具有电荷传递函数的半导体衬底和光电转换膜的高效率固态成像器,其中具有高于垂直传输脉冲的频率的高频传输脉冲在垂直方向施加规定时间 消隐期 在上述第一和第二周期中存在上述高频传输脉冲,将不同值的电压施加到设置在上述光电转换膜上的透明电极; 并且在垂直消隐期间,对上述透明电极施加与各场不同的电压,从而显着地抑制了由于强光引起的闪光,高光滞后和闪烁。
    • 4. 发明授权
    • Semiconductor device having a double-layer interconnection structure
    • 具有双层互连结构的半导体器件
    • US5327012A
    • 1994-07-05
    • US993885
    • 1992-12-23
    • Kohsaku YanoTetsuya UedaTeruhito OhnishiHiroshi Nishimura
    • Kohsaku YanoTetsuya UedaTeruhito OhnishiHiroshi Nishimura
    • H01L23/522H01L23/532H01L23/48
    • H01L23/5329H01L23/5226H01L2924/0002
    • A semiconductor device having a double-layer interconnection with contact portions between first and second metal films, each having a multi-layered structure, covered with at least a silicon nitride film is provided wherein an electromigration characteristic at the contact portions is improved. The improvement is achieved by defining a value obtained by multiplying a thickness of the silicon nitride film by a stress of the nitride film formed at the contact portions is not larger than 2/5 of a value obtained by multiplying a thickness of the silicon nitride film by a stress of the nitride film formed at non-contact portions. By this, the stress exerted on the second metal film is reduced to improve the electromigration life at the contact portions by about one order of magnitude. The first and second metal films, respectively, have a multi-layered structure including a sub-layer made of Al or Al alloys.
    • 提供一种具有与第一和第二金属膜之间的接触部分的双层互连的半导体器件,每个具有多层结构的接触部分被至少覆盖有氮化硅膜,其中提高了接触部分的电迁移特性。 通过将通过在接触部分形成的氮化物膜的应力乘以氮化硅膜的厚度而获得的值不超过通过将氮化硅膜的厚度乘以所获得的值的2/5来获得的改进 通过在非接触部分形成的氮化物膜的应力。 由此,施加在第二金属膜上的应力减小,从而将接触部分的电迁移寿命提高大约一个数量级。 第一和第二金属膜分别具有包括由Al或Al合金制成的子层的多层结构。
    • 7. 发明授权
    • Semiconductor memory device
    • 半导体存储器件
    • US5132748A
    • 1992-07-21
    • US682109
    • 1991-04-08
    • Kohsaku Yano
    • Kohsaku Yano
    • H01L21/8229H01L27/102H01L27/108
    • H01L27/108H01L27/1023
    • A semiconductor device includes a first semiconductor region connected to a bit line for controlling signal charges; a second semiconductor region connected to the first semiconductor region and to a word line for controlling signal charges, wherein the second semiconductor region has a type of electrical conductivity which is different from that of the first semiconductor region; and a third semiconductor region connected to the second semiconductor region and to a data line for reading the signal charges, wherein the third semiconductor region has a type of electrical conductivity which is the same as that of the first semiconductor region, and wherein the third semiconductor region has a barrier at the interface with the data line, the barrier being able to be controlled by the bit line and the word line to store signal charges in the third semiconductor regions. The barrier may be a Schottky barrier or a thin insulating film which can be controlled by the bit and word lines for writing, holding and reading of information charges in the third semiconductor region. A fourth semiconductor region may be arranged between the first and the third semiconductor regions in parallel to the second region as in a junction field effect transistor.
    • 半导体器件包括连接到用于控制信号电荷的位线的第一半导体区域; 连接到第一半导体区域的第二半导体区域和用于控制信号电荷的字线,其中第二半导体区域具有不同于第一半导体区域的导电类型; 以及连接到第二半导体区域的第三半导体区域和用于读取信号电荷的数据线,其中第三半导体区域具有与第一半导体区域相同的导电类型,并且其中第三半导体区域 区域在与数据线的界面处具有阻挡层,所述势垒能够由位线和字线控制,以将信号电荷存储在第三半导体区域中。 势垒可以是肖特基势垒或薄的绝缘膜,其可以由位和字线控制,用于在第三半导体区域中写入,保持和读取信息电荷。 第四半导体区域可以如在结型场效应晶体管中那样平行于第二区域布置在第一和第三半导体区域之间。
    • 8. 发明授权
    • Apparatus for dry etching
    • 干蚀刻设备
    • US5076877A
    • 1991-12-31
    • US523422
    • 1990-05-15
    • Tetsuya UedaKohsaku Yano
    • Tetsuya UedaKohsaku Yano
    • H01L21/302H01L21/00
    • H01L21/67069
    • An apparatus for dry etching, which comprises a stage for supporting a substrate, a rotor having a center shaft, the stage and an arm connecting the stage to the center shaft, and a driving means for turning the rotor at the center shaft as a turning center in the direction tangential to the circumference of a circle established by turning of the surface of the substrate at the center shaft as a turning center, the rotor being housed in a chamber, can make uniform perpendicular submicron etching with radicals or a reactive gas without using ions and without damages on the substrate.
    • 一种用于干蚀刻的装置,包括用于支撑基板的台,具有中心轴的转子,所述台和将所述台与所述中心轴连接的臂,以及用于在所述中心轴处转动所述转子作为转动的驱动装置 中心在与通过在作为转动中心的中心轴处的基板的表面的转动而形成的圆的圆周方向上,转子被容纳在室中,可以进行具有自由基或反应气体的均匀的垂直亚微米蚀刻而没有 在基板上使用离子而不损坏。