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1. 发明授权

US5327012A Semiconductor device having a double-layer interconnection structure 失效
标题翻译：具有双层互连结构的半导体器件
公开(公告)号：US5327012A
公开(公告)日：1994-07-05
申请号：US993885
申请日：1992-12-23
申请人： Kohsaku Yano , Tetsuya Ueda , Teruhito Ohnishi , Hiroshi Nishimura
发明人： Kohsaku Yano , Tetsuya Ueda , Teruhito Ohnishi , Hiroshi Nishimura
IPC分类号： H01L23/522 , H01L23/532 , H01L23/48
CPC分类号： H01L23/5329 , H01L23/5226 , H01L2924/0002
摘要： A semiconductor device having a double-layer interconnection with contact portions between first and second metal films, each having a multi-layered structure, covered with at least a silicon nitride film is provided wherein an electromigration characteristic at the contact portions is improved. The improvement is achieved by defining a value obtained by multiplying a thickness of the silicon nitride film by a stress of the nitride film formed at the contact portions is not larger than 2/5 of a value obtained by multiplying a thickness of the silicon nitride film by a stress of the nitride film formed at non-contact portions. By this, the stress exerted on the second metal film is reduced to improve the electromigration life at the contact portions by about one order of magnitude. The first and second metal films, respectively, have a multi-layered structure including a sub-layer made of Al or Al alloys.
摘要翻译：提供一种具有与第一和第二金属膜之间的接触部分的双层互连的半导体器件，每个具有多层结构的接触部分被至少覆盖有氮化硅膜，其中提高了接触部分的电迁移特性。通过将通过在接触部分形成的氮化物膜的应力乘以氮化硅膜的厚度而获得的值不超过通过将氮化硅膜的厚度乘以所获得的值的2/5来获得的改进通过在非接触部分形成的氮化物膜的应力。由此，施加在第二金属膜上的应力减小，从而将接触部分的电迁移寿命提高大约一个数量级。第一和第二金属膜分别具有包括由Al或Al合金制成的子层的多层结构。

2. 发明授权

US5198884A Semiconductor devices having a double-layer interconnection structure 失效
标题翻译：具有双层互连结构的半导体器件
公开(公告)号：US5198884A
公开(公告)日：1993-03-30
申请号：US675833
申请日：1991-03-27
申请人： Kohsaku Yano , Tetsuya Ueda , Teruhito Ohnishi , Hiroshi Nishimura
发明人： Kohsaku Yano , Tetsuya Ueda , Teruhito Ohnishi , Hiroshi Nishimura
IPC分类号： H01L23/522 , H01L23/532
CPC分类号： H01L23/5226 , H01L23/5329 , H01L2924/0002
摘要： A semiconductor device having a double-layer interconnection with contact portions between first and second metal films covered with at least a silicon nitride film is provided wherein an electromigration characteristic at the contact portions is improved. The improvement is achieved by defining a value obtained by multiplying a thickness of the silicon nitride film by a stress of the nitride film formed at the contact portions is not larger than 2/5 of a value obtained by multiplying a thickness of the silicon nitride film by a stress of the nitride film formed at non-contact portions. By this, the stress exerted on the second metal film is reduced to improve the electromigration life at the contact portions by about one order of magnitude. The first and second metal films are made of Al or Al-based alloys.
摘要翻译：提供了具有与至少覆盖有氮化硅膜的第一和第二金属膜之间的接触部分的双层互连的半导体器件，其中改善了接触部分处的电迁移特性。通过将通过在接触部分形成的氮化物膜的应力乘以氮化硅膜的厚度而获得的值不超过通过将氮化硅膜的厚度乘以所获得的值的2/5来获得的改进通过在非接触部分形成的氮化物膜的应力。由此，施加在第二金属膜上的应力减小，从而将接触部分的电迁移寿命提高大约一个数量级。第一和第二金属膜由Al或Al基合金制成。

3. 发明授权

US07091099B2 Bipolar transistor and method for fabricating the same 有权
标题翻译：双极晶体管及其制造方法
公开(公告)号：US07091099B2
公开(公告)日：2006-08-15
申请号：US10807307
申请日：2004-03-24
申请人： Teruhito Ohnishi , Koichiro Yuki , Tsuneichiro Sano , Tohru Saitoh , Ken Idota , Takahiro Kawashima , Shigeki Sawada
发明人： Teruhito Ohnishi , Koichiro Yuki , Tsuneichiro Sano , Tohru Saitoh , Ken Idota , Takahiro Kawashima , Shigeki Sawada
IPC分类号： H01L21/331
CPC分类号： H01L29/66242 , H01L29/7378
摘要： A bipolar transistor includes a Si single crystalline layer serving as a collector, a single crystalline Si/SiGeC layer and a polycrystalline Si/SiGeC layer which are formed on the Si single crystalline layer, an oxide film having an emitter opening portion, an emitter electrode, and an emitter layer. An intrinsic base layer is formed on the single crystalline Si/SiGeC layer, part of the single crystalline Si/SiGeC layer, the polycrystalline Si/SiGeC layer and the Co silicide layer together form an external base layer. The thickness of the emitter electrode is set so that boron ions implanted into the emitter electrode and diffused therein do not reach an emitter-base junction portion.
摘要翻译：双极晶体管包括形成在Si单晶层上的Si单结晶层，单晶Si / SiGeC层和多晶Si / SiGeC层，具有发射极开口部分的氧化膜，发射极，和发射极层。在单晶Si / SiGeC层上形成本征基层，单晶Si / SiGeC层的一部分，多晶Si / SiGeC层和Co硅化物层一起形成外部基极层。发射电极的厚度被设定为使得注入发射电极并在其中扩散的硼离子不会到达发射极 - 基极接合部分。

4. 发明申请

US20050092230A1 Method for fabricating a semiconductor crystal 失效
标题翻译：半导体晶体的制造方法
公开(公告)号：US20050092230A1
公开(公告)日：2005-05-05
申请号：US11009020
申请日：2004-12-13
申请人： Yoshihiko Kanzawa , Teruhito Ohnishi , Ken Idota , Tohru Saitoh , Akira Asai
发明人： Yoshihiko Kanzawa , Teruhito Ohnishi , Ken Idota , Tohru Saitoh , Akira Asai
IPC分类号： C30B1/00 , C30B23/02 , C30B25/02 , C30B29/52 , H01L21/205 , H01L21/31 , H01L21/322 , H01L21/324
CPC分类号： H01L21/324 , C30B23/02 , C30B25/02 , C30B29/52 , H01L21/02381 , H01L21/02529 , H01L21/02532 , H01L21/0262 , H01L21/02661 , H01L21/02664 , H01L21/322 , Y10S438/933
摘要： A method for fabricating a semiconductor crystal that has a first step for forming a semiconductor crystal layer (202) that contains carbon atoms and at least one kind of Group IV element other than carbon on a substrate (201), a second step for adding an impurity that is capable of reacting with oxygen to the semiconductor crystal layer (202), and a third step for removing the carbon atoms contained in the semiconductor crystal layer (202) by reacting the carbon with the impurity. This method makes it possible to fabricate a semiconductor crystal substrate in which the concentration of interstitial carbon atoms is satisfactorily reduced, thus resulting in excellent electrical properties when the substrate is applied to a semiconductor device.
摘要翻译：一种制造半导体晶体的方法，其具有在基板（201）上形成含有碳原子的半导体晶体层（202）和除了碳以外的至少一种第IV族元素的第一工序，第二工序用于添加能够与氧反应的半导体晶体层（202）的杂质，以及通过使碳与杂质反应来除去半导体结晶层（202）中所含的碳原子的第三工序。该方法可以制造其中间隙碳原子的浓度令人满意地降低的半导体晶体衬底，从而当将衬底应用于半导体器件时获得优异的电性能。

5. 发明授权

US06674149B2 Bipolar transistor device having phosphorous 失效
标题翻译：具有磷的双极晶体管器件
公开(公告)号：US06674149B2
公开(公告)日：2004-01-06
申请号：US10009201
申请日：2001-12-10
申请人： Teruhito Ohnishi , Akira Asai
发明人： Teruhito Ohnishi , Akira Asai
IPC分类号： H01L27082
CPC分类号： H01L29/66242 , H01L29/7378
摘要： A Si1-xGex layer 111b functioning as the base composed of an i-Si1-xGex layer and a p+ Si1-xGex layer is formed on a collector layer 102, and a Si cap layer 111a as the emitter is formed on the p+ Si1-xGex layer. An emitter lead electrode 129, which is composed of an n− polysilicon layer 129b containing phosphorus in a concentration equal to or lower than the solid-solubility limit for single-crystal silicon and a n+ polysilicon layer 129a containing phosphorus in a high concentration, is formed on the Si cap layer 111a in a base opening 118. The impurity concentration distribution in the base layer is properly maintained by suppressing the Si cap layer 111a from being doped with phosphorus (P) in an excessively high concentration. The upper portion of the Si cap layer 111a may contain a p-type impurity. The p-type impurity concentration distribution in the base layer of an NPN bipolar transistor is thus properly maintained.
摘要翻译：在集电极层102上形成用作由i-Si1-xGex层和ap + Si1-xGex层构成的基底的Si1-xGex层111b，在p上形成作为发射极的Si覆盖层111a Si1-xGex层。发射极引线电极129，其由含有等于或低于单晶硅的固溶度极限的磷的n +多晶硅层129b和含有磷的多晶硅层129a组成在基底开口118中的Si覆盖层111a上形成高浓度。通过抑制Si覆盖层111a以过高的浓度掺杂磷（P）来适当地保持基底层中的杂质浓度分布。 Si覆盖层111a的上部可以含有p型杂质。因此，适当地维持NPN双极晶体管的基极层中的p型杂质浓度分布。

6. 发明授权

US06642607B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06642607B2
公开(公告)日：2003-11-04
申请号：US10061365
申请日：2002-02-04
申请人： Teruhito Ohnishi , Takeshi Takagi , Akira Asai , Taizo Fujii , Mitsuo Sugiura , Yoshihisa Minami
发明人： Teruhito Ohnishi , Takeshi Takagi , Akira Asai , Taizo Fujii , Mitsuo Sugiura , Yoshihisa Minami
IPC分类号： H01L2993
CPC分类号： H01L29/93 , H01L27/0664 , H01L27/0808
摘要： A variable capacitor includes an N+ layer including a variable capacitance region, a P+ layer epitaxially grown on the N+ layer and formed from a SiGe film and a Si film, and a P-type electrode. An NPN-HBT (Hetero-junction Bipolar Transistor) includes a collector diffusion layer formed simultaneously with the N+ layer of the variable capacitor, a collector layer, and a Si/SiGe layer epitaxially grown simultaneously with the P+ layer of the variable capacitor. Since a depletion layer formed in a PN junction of the variable capacitor can extend entirely across the N+ layer, reduction in variation range of the capacitance can be suppressed.
摘要翻译：可变电容器包括N +层，包括可变电容区，在N +层上外延生长并由SiGe膜和Si膜形成的P +层和P型电极。 NPN-HBT（异质结双极晶体管）包括与可变电容器的N +层同时形成的集电极扩散层，集电极层和与P +层同时外延生长的Si / SiGe层的可变电容器。由于形成在可变电容器的PN结中的耗尽层可以完全延伸穿过N +层，所以可以抑制电容的变化范围的减小。

7. 发明授权

US07719031B2 Heterojunction biploar transistor and method for manufacturing same 失效
标题翻译：异质结双极晶体管及其制造方法
公开(公告)号：US07719031B2
公开(公告)日：2010-05-18
申请号：US10564085
申请日：2004-07-06
申请人： Tohru Saitoh , Takahiro Kawashima , Ken Idota , Yoshihiko Kanzawa , Teruhito Ohnishi
发明人： Tohru Saitoh , Takahiro Kawashima , Ken Idota , Yoshihiko Kanzawa , Teruhito Ohnishi
IPC分类号： H01L29/74
CPC分类号： H01L29/66242 , H01L29/7378
摘要： A bipolar transistor 120 comprises a substrate 1, a intrinsic base region 11 and an extrinsic base region 12. The intrinsic base region 11 comprises a silicon buffer layer 109 comprised of silicon which is formed on the substrate 1, and a composition-ratio graded base layer 111 which is formed on the silicon buffer layer and comprises silicon and at least germanium and where a composition ratio of the germanium to the silicon varies in a thickness direction of the composition-ratio graded base layer 111. The extrinsic base region 12 comprises an extrinsic base formation layer 113 comprised of silicon which is formed on the substrate and adjacent to the silicon buffer layer. And the thickness of the extrinsic base formation layer 113 is not less than 40 nm.
摘要翻译：双极晶体管120包括衬底1，本征基极区域11和非本征基极区域12.本征基极区域11包括由衬底1上形成的硅构成的硅缓冲层109和组成比分级基底层111，其形成在硅缓冲层上并且包含硅并且至少为锗，并且其中锗与硅的组成比在组成比梯度基底层111的厚度方向上变化。外部基极区12包括外部基底形成层113由硅构成，其形成在衬底上并与硅缓冲层相邻。外部基底形成层113的厚度不小于40nm。

8. 发明授权

US07145168B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07145168B2
公开(公告)日：2006-12-05
申请号：US10997127
申请日：2004-11-24
申请人： Yoshihiro Hara , Akira Asai , Gaku Sugahara , Haruyuki Sorada , Teruhito Ohnishi
发明人： Yoshihiro Hara , Akira Asai , Gaku Sugahara , Haruyuki Sorada , Teruhito Ohnishi
IPC分类号： H01L29/06 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L29/1054 , H01L21/76224 , H01L21/823481 , Y10S438/933
摘要： On an Si substrate 1, a buffer layer 2, a SiGe layer 3, and an Si cap layer 4 are formed. A mask is formed on the substrate, and then the substrate is patterned. In this manner, a trench 7a is formed so as to reach the Si substrate 1 and have the side faces of the SiGe layer 3 exposed. Then, the surface of the trench 7a is subjected to heat treatment for one hour at 750° C. so that Ge contained in a surface portion of the SiGe layer 3 is evaporated. Thus, a Ge evaporated portion 8 having a lower Ge content than that of other part of the SiGe layer 3 is formed in part of the SiGe layer 3 exposed at part of the trench 7a. Thereafter, the walls of the trench 7a are oxidized.
摘要翻译：在Si衬底1上形成缓冲层2，SiGe层3和Si覆盖层4。在基板上形成掩模，然后对基板进行图案化。以这种方式，形成沟槽7a以到达Si衬底1并且暴露SiGe层3的侧面。然后，将沟槽7a的表面在750℃下进行1小时的热处理，使得包含在SiGe层3的表面部分中的Ge蒸发。因此，在沟槽7a的一部分暴露的SiGe层3的一部分，形成Ge含量低于SiGe层3的Ge含量低的Ge蒸发部分8。此后，沟槽7a的壁被氧化。

9. 发明申请

US20060225642A1 Method of forming semiconductor crystal 审中-公开
标题翻译：形成半导体晶体的方法
公开(公告)号：US20060225642A1
公开(公告)日：2006-10-12
申请号：US10402239
申请日：2003-03-31
申请人： Yoshihiko Kanzawa , Tohru Saitoh , Akira Asai , Teruhito Ohnishi
发明人： Yoshihiko Kanzawa , Tohru Saitoh , Akira Asai , Teruhito Ohnishi
IPC分类号： C30B23/00 , C30B25/00 , C30B28/12 , C30B28/14
CPC分类号： C30B25/04 , C30B25/18 , C30B29/52 , H01L21/02381 , H01L21/02447 , H01L21/0245 , H01L21/02529 , H01L21/02532 , H01L21/0262 , H01L21/02658 , H01L21/02661 , H01L29/1054
摘要： A method of forming semiconductor crystal of the present invention comprises the steps of heating a Si substrate to clean a surface of the Si substrate, epitaxially growing Si crystal on the Si substrate inside a crystal growth chamber at a growth temperature lower than a substrate temperature of the Si substrate in the cleaning step and higher than a growth temperature at which SiGe crystal is epitaxially grown later, and epitaxially growing the SiGe crystal on the Si crystal.
摘要翻译：本发明的半导体晶体的形成方法包括以下步骤：加热Si衬底以清洁Si衬底的表面，在晶体生长室内的Si衬底上外延生长Si晶体，生长温度低于衬底温度 Si衬底在高于SiGe晶体后来生长的生长温度以及在Si晶体上外延生长SiGe晶体。

10. 发明授权

US07109095B2 Method for fabricating semiconductor device 有权
公开(公告)号：US07109095B2
公开(公告)日：2006-09-19
申请号：US10396505
申请日：2003-03-26
申请人： Hidenori Notake , Teruhito Ohnishi , Akira Asai , Shigetaka Aoki
发明人： Hidenori Notake , Teruhito Ohnishi , Akira Asai , Shigetaka Aoki
IPC分类号： H01L21/20
CPC分类号： H01L21/0209 , H01L21/02052 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/02639 , H01L21/32134 , H01L29/66242
摘要： Immediately after a Si/SiGe film containing a contaminant is formed over all surfaces of a substrate by epitaxial growth, a portion of the Si/SiGe film formed to the back surface side of the substrate is removed by wet etching. In addition, the Si/SiGe film is subjected to processing with heating in a container, after which a dummy run is carried out in the container. These processings prevent secondary wafer contamination through a stage, a robot arm or a vacuum wand for handling a wafer and the contamination of the container also used in the fabrication process of a semiconductor device free from any group IV element but Si.

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