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1. 发明申请

US20060008962A1 Manufacturing method of semiconductor integrated circuit device 审中-公开
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US20060008962A1
公开(公告)日：2006-01-12
申请号：US11175049
申请日：2005-07-06
申请人： Kazuyuki Ozeki , Yuji Tsukada
发明人： Kazuyuki Ozeki , Yuji Tsukada
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L21/823481 , H01L21/823462
摘要： The invention is directed to a semiconductor integrated circuit device having a plurality of gate insulation films of different thicknesses where reliability of the gate insulation films and characteristics of MOS transistors are improved. A photoresist layer is selectively formed on a SiO2 film in first and third regions, and a SiO2 film in a second region is removed by etching. After the photoresist layer is removed, a silicon substrate is thermally oxidized to form a SiO2 film having a smaller thickness than a first gate insulation film in the second region. Then, the SiO2 film in the third region is removed by etching. After a photoresist layer is removed, the silicon substrate is thermally oxidized to form a SiO2 film having a smaller thickness than a second gate insulation film in the third region.
摘要翻译：本发明涉及一种半导体集成电路器件，其具有多个不同厚度的栅极绝缘膜，其中栅极绝缘膜的可靠性和MOS晶体管的特性得到改善。在第一和第三区域中的SiO 2膜上选择性地形成光致抗蚀剂层，并且通过蚀刻去除第二区域中的SiO 2膜。在除去光致抗蚀剂层之后，硅衬底被热氧化以形成在第二区域中具有比第一栅极绝缘膜更薄的厚度的SiO 2膜。然后，通过蚀刻除去第三区域中的SiO 2膜。在去除光致抗蚀剂层之后，硅衬底被热氧化以形成具有比第三区域中的第二栅极绝缘膜更薄的厚度的SiO 2膜。

2. 发明授权

US06551867B1 Non-volatile semiconductor memory device and method for manufacturing the same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US06551867B1
公开(公告)日：2003-04-22
申请号：US09488917
申请日：2000-01-19
申请人： Kazuyuki Ozeki , Yukihiro Oya , Kazutoshi Kitazume , Hideo Azegami
发明人： Kazuyuki Ozeki , Yukihiro Oya , Kazutoshi Kitazume , Hideo Azegami
IPC分类号： H01L2100
CPC分类号： H01L27/11521 , H01L27/115
摘要： A non-volatile semiconductor memory device includes an interlayer dielectric film 9, 19 flattened by etching back an SOG film. In the non-volatile semiconductor memory device, a barrier film of a silicon nitride film 9D and 19D is formed to cover at least a memory cell composed of a floating gate 4, a control gate 6, etc. Because of such a structure, even if H or OH contained in the SOG is diffused, it will not be trapped by a tunneling film 3. This improves a “trap-up rate”. The barrier film may be formed in only an area covering the memory cell. This reduces its contact area with a tungsten silicide film, thereby suppressing film peeling-off. Thus, the operation life of the memory cell in the non-volatile semiconductor memory device can be improved.
摘要翻译：非挥发性半导体存储器件包括通过蚀刻SOG膜而平坦化的层间电介质膜9,19。在非易失性半导体存储器件中，形成氮化硅膜9D和19D的阻挡膜以至少覆盖由浮动栅极4，控制栅极6等组成的存储单元。由于这样的结构，即使如果包含在SOG中的H或OH扩散，则不会被隧道膜3捕获。这提高了“捕获率”。阻挡膜可以仅形成在覆盖存储单元的区域中。这就减少了与硅化钨膜的接触面积，从而抑制了膜的剥离。因此，可以提高非易失性半导体存储器件中的存储单元的使用寿命。

3. 发明授权

US07211486B2 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07211486B2
公开(公告)日：2007-05-01
申请号：US11175050
申请日：2005-07-06
申请人： Kazuyuki Ozeki , Yuji Goto
发明人： Kazuyuki Ozeki , Yuji Goto
IPC分类号： H01L21/336
CPC分类号： H01L27/11534 , H01L21/28273 , H01L27/0629 , H01L27/105 , H01L27/11521 , H01L27/11526 , H01L27/11531 , H01L27/11539 , H01L29/66825 , H01L29/7881
摘要： When memory cells of EEPROM and a capacitor element are formed on a same semiconductor substrate, the number of processes is prevented from increasing and a manufacturing cost is reduced. Furthermore, reliability of the capacitor element is improved, and characteristics of the memory cells, a MOS transistor, and so on are prevented from changing. A pair of left and right memory cells is formed in a memory cell formation region of a P-type silicon substrate, being symmetrical to each other with respect to a source region, and a capacitor element formed of a lower electrode, a capacitor insulation film, and an upper electrode is formed in a capacitor element formation region of the same P-type silicon substrate. The lower electrode of the capacitor element is formed by patterning a polysilicon film provided for forming control gates of the pair of memory cells.
摘要翻译：当EEPROM和电容器元件的存储单元形成在相同的半导体衬底上时，防止了工艺数量的增加并且降低了制造成本。此外，电容器元件的可靠性得到改善，并且防止存储单元，MOS晶体管等的特性改变。一对左右存储单元形成在P型硅衬底的存储单元形成区域中，相对于源极区域彼此对称，并且电容器元件由下电极，电容器绝缘膜并且在相同P型硅衬底的电容器元件形成区域中形成上电极。电容器元件的下电极通过图案化用于形成该对存储单元的控制栅极的多晶硅膜而形成。

4. 发明申请

US20060008986A1 Method of manufacturing a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20060008986A1
公开(公告)日：2006-01-12
申请号：US11175050
申请日：2005-07-06
申请人： Kazuyuki Ozeki , Yuji Goto
发明人： Kazuyuki Ozeki , Yuji Goto
IPC分类号： H01L21/336
CPC分类号： H01L27/11534 , H01L21/28273 , H01L27/0629 , H01L27/105 , H01L27/11521 , H01L27/11526 , H01L27/11531 , H01L27/11539 , H01L29/66825 , H01L29/7881
摘要： When memory cells of EEPROM and a capacitor element are formed on a same semiconductor substrate, the number of processes is prevented from increasing and a manufacturing cost is reduced. Furthermore, reliability of the capacitor element is improved, and characteristics of the memory cells, a MOS transistor, and so on are prevented from changing. A pair of left and right memory cells is formed in a memory cell formation region of a P-type silicon substrate, being symmetrical to each other with respect to a source region, and a capacitor element formed of a lower electrode, a capacitor insulation film, and an upper electrode is formed in a capacitor element formation region of the same P-type silicon substrate. The lower electrode of the capacitor element is formed by patterning a polysilicon film provided for forming control gates of the pair of memory cells.
摘要翻译：当EEPROM和电容器元件的存储单元形成在相同的半导体衬底上时，防止了工艺数量的增加并且降低了制造成本。此外，电容器元件的可靠性得到改善，并且防止存储单元，MOS晶体管等的特性改变。一对左右存储单元形成在P型硅衬底的存储单元形成区域中，相对于源极区域彼此对称，并且电容器元件由下电极，电容器绝缘膜并且在相同P型硅衬底的电容器元件形成区域中形成上电极。电容器元件的下电极通过图案化用于形成该对存储单元的控制栅极的多晶硅膜而形成。

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