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1. 发明授权

US08707057B2 Data processing apparatus and data processing method 有权
标题翻译：数据处理装置及数据处理方法
公开(公告)号：US08707057B2
公开(公告)日：2014-04-22
申请号：US13237317
申请日：2011-09-20
申请人： Kazuyoshi Furukawa , Takeshi Shimoyama , Masahiko Takenaka
发明人： Kazuyoshi Furukawa , Takeshi Shimoyama , Masahiko Takenaka
IPC分类号： G06F11/30 , G06F12/14
CPC分类号： H04L9/002 , H04L9/06 , H04L2209/12
摘要： A data processing apparatus includes an address bus, a scramble unit, and a data bus. The address bus outputs address data to be given to a memory apparatus. The scramble unit scrambles write-in data into a storage position in the memory apparatus identified by the address data to obtain confidential data. The data bus outputs the confidential data. The scramble unit includes a first scrambler, a first converter and a second scrambler. The first scrambler XORs first mask data corresponding to the address data and the write-in data for each bit and makes it first scrambled data. The first converter performs one-to-one substitution conversion of the first scrambled data. The second scrambler XORs second mask data corresponding to the address data and data after the conversion of the first scrambled data by the first converter and outputs obtained second scrambled data as the confidential data.
摘要翻译：数据处理装置包括地址总线，加扰单元和数据总线。地址总线输出要提供给存储装置的地址数据。加扰单元将写入数据加密到由地址数据识别的存储装置中的存储位置，以获得机密数据。数据总线输出机密数据。加扰单元包括第一加扰器，第一转换器和第二加扰器。第一加扰器将对应于地址数据的第一掩码数据和每个位的写入数据进行异或，并使其成为第一个加扰数据。第一转换器执行第一加扰数据的一对一替换转换。第二加扰器将对应于地址数据的第二掩码数据和由第一转换器转换第一加扰数据之后的数据进行异或，并将获得的第二加密数据作为机密数据输出。

2. 发明申请

US20120008782A1 DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD 有权
标题翻译：数据处理设备和数据处理方法
公开(公告)号：US20120008782A1
公开(公告)日：2012-01-12
申请号：US13237317
申请日：2011-09-20
申请人： Kazuyoshi FURUKAWA , Takeshi Shimoyama , Masahiko Takenaka
发明人： Kazuyoshi FURUKAWA , Takeshi Shimoyama , Masahiko Takenaka
IPC分类号： H04L9/20
CPC分类号： H04L9/002 , H04L9/06 , H04L2209/12
摘要： A data processing apparatus includes an address bus, a scramble unit, and a data bus. The address bus outputs address data to be given to a memory apparatus. The scramble unit scrambles write-in data into a storage position in the memory apparatus identified by the address data to obtain confidential data. The data bus outputs the confidential data. The scramble unit includes a first scrambler, a first converter and a second scrambler. The first scrambler XORs first mask data corresponding to the address data and the write-in data for each bit and makes it first scrambled data. The first converter performs one-to-one substitution conversion of the first scrambled data. The second scrambler XORs second mask data corresponding to the address data and data after the conversion of the first scrambled data by the first converter and outputs obtained second scrambled data as the confidential data.
摘要翻译：数据处理装置包括地址总线，加扰单元和数据总线。地址总线输出要提供给存储装置的地址数据。加扰单元将写入数据加密到由地址数据识别的存储装置中的存储位置，以获得机密数据。数据总线输出机密数据。加扰单元包括第一加扰器，第一转换器和第二加扰器。第一加扰器将对应于地址数据的第一掩码数据和每个位的写入数据进行异或，并使其成为第一个加扰数据。第一转换器执行第一加扰数据的一对一替换转换。第二加扰器将对应于地址数据的第二掩码数据和由第一转换器转换第一加扰数据之后的数据进行异或，并将获得的第二加密数据作为机密数据输出。

3. 发明授权

US06956951B2 Extended key preparing apparatus, extended key preparing method, recording medium and computer program 失效
标题翻译：扩展密钥准备装置，扩展密钥准备方法，记录介质和计算机程序
公开(公告)号：US06956951B2
公开(公告)日：2005-10-18
申请号：US09811551
申请日：2001-03-20
申请人： Takeshi Shimoyama , Koichi Ito , Masahiko Takenaka , Naoya Torii , Jun Yajima , Hitoshi Yanami , Kazuhiro Yokoyama
发明人： Takeshi Shimoyama , Koichi Ito , Masahiko Takenaka , Naoya Torii , Jun Yajima , Hitoshi Yanami , Kazuhiro Yokoyama
IPC分类号： H04L9/06 , H04L9/00
CPC分类号： H04L9/0625 , H04L2209/12
摘要： Intermediate data ai, bi, ci, and di are prepared by an intermediate data preparing equipment 4 from a cryptographic key through a nonlinear type function operation and the like, an extended key preparing equipment 5 selects a [Xr], b [Yr], c [Zr], and d [Wr] corresponding to the number of stages r from the intermediate data, and rearranges the data as well as conducts that of bit operation to prepare extended keys, whereby an extended key preparing apparatus by which an extended key required in the case where common key cryptosystem is applied can be safely prepared at a high speed, a process for preparing such an extended key, and a recording medium used therefor are provided.
摘要翻译：中间数据准备设备（中间数据准备设备）通过中间数据准备设备来制备中间数据，中间数据和/ 通过非线性类型函数操作等从加密密钥4输出的数据，扩展密钥准备设备5选择[X，R]，b [Y] Z＆lt; r＆gt;]和对应于来自中间数据的级数r的d [W SUB]，并且重新排列数据，并且进行位操作以进行准备扩展密钥，从而可以高速安全地准备应用公共密钥密码系统所需的扩展密钥的扩展密钥准备装置，用于制备这样的扩展密钥的处理及其使用的记录介质。

4. 发明授权

US07793134B2 Information processing apparatus working at variable operating frequency 有权
标题翻译：以可变工作频率工作的信息处理设备
公开(公告)号：US07793134B2
公开(公告)日：2010-09-07
申请号：US11943092
申请日：2007-11-20
申请人： Takeshi Shimoyama
发明人： Takeshi Shimoyama
IPC分类号： G06F1/00
CPC分类号： G06F13/4243
摘要： An information processing apparatus includes a clock signal generator unit that generates a clock signal which is variable in frequency. The information processing apparatus also includes a timing information calculator unit that calculates timing information corresponding to frequency information about the clock signal and acquires the frequency information before a variation in the clock signal. The information processing apparatus further includes an information processor unit that executes an information processing operation for a memory at an execution timing which is controlled by the timing information. The clock signal is supplied to the information processor unit as an operating clock signal. The timing information calculator unit determines whether an address of the memory of a previous information processing operation matches with an address of the memory of the information processing operation to produce a determination result and calculates the timing information based on the determination result.
摘要翻译：信息处理装置包括：时钟信号发生器单元，其生成频率可变的时钟信号。信息处理装置还包括定时信息计算器单元，其计算与时钟信号相关的频率信息的定时信息，并且在时钟信号变化之前获取频率信息。信息处理装置还包括信息处理单元，该信息处理单元在由定时信息控制的执行定时执行存储器的信息处理操作。时钟信号作为操作时钟信号提供给信息处理器单元。定时信息计算单元确定先前的信息处理操作的存储器的地址是否与信息处理操作的存储器的地址匹配以产生确定结果，并且基于确定结果来计算定时信息。

5. 发明申请

US20100007770A1 MEMORY ACCESS CONTROL APPARATUS AND IMAGE PICKUP APPARATUS 失效
标题翻译：存储器访问控制装置和图像拾取装置
公开(公告)号：US20100007770A1
公开(公告)日：2010-01-14
申请号：US12487124
申请日：2009-06-18
申请人： Tomohiro KOGANEZAWA , Takeshi Shimoyama , Kingo Koyama , Takuji Himeno
发明人： Tomohiro KOGANEZAWA , Takeshi Shimoyama , Kingo Koyama , Takuji Himeno
IPC分类号： H04N5/225 , G06F12/02
CPC分类号： H04N5/232 , G06F13/1689 , H04N5/23245
摘要： A memory access control apparatus includes a memory controller controlling a memory adopting a DDR format; a DDR-PHY adjusting the timing of an interface signal between the memory controller and the memory; a DDR-PHY controller controlling the DDR-PHY; and a clock controller controlling the frequency of a clock signal. A first request signal for controlling the operation of the memory in a self-refresh mode is supplied to the memory controller, a second request signal for resetting the DDR-PHY is supplied to the DDR-PHY controller, a third request signal for changing the clock frequency is supplied to the clock controller, a fourth request signal for setting a parameter for the DDR-PHY is supplied to the DDR-PHY controller, and a fifth request signal for canceling the operation of the memory in the self-refresh mode is supplied to the memory controller in order to change the clock frequency of the memory.
摘要翻译：存储器访问控制装置包括控制采用DDR格式的存储器的存储器控制器; DDR-PHY调整存储器控制器和存储器之间的接口信号的定时; 控制DDR-PHY的DDR-PHY控制器; 以及控制时钟信号的频率的时钟控制器。用于在自刷新模式下控制存储器的操作的第一请求信号被提供给存储器控制器，用于复位DDR-PHY的第二请求信号被提供给DDR-PHY控制器，第三请求信号用于改变将时钟频率提供给时钟控制器，将用于设置DDR-PHY的参数的第四请求信号提供给DDR-PHY控制器，并且用于在自刷新模式下取消存储器的操作的第五请求信号是提供给存储器控制器以便改变存储器的时钟频率。

6. 发明授权

US07356726B2 Frequency control apparatus for controlling the operation frequency of an object 失效
标题翻译：用于控制物体的操作频率的频率控制装置
公开(公告)号：US07356726B2
公开(公告)日：2008-04-08
申请号：US10552897
申请日：2004-05-07
申请人： Takeshi Shimoyama , Tetsumasa Meguro , Tsutomu Teranishi , Yasuo Nakano , Hirokazu Kawahara
发明人： Takeshi Shimoyama , Tetsumasa Meguro , Tsutomu Teranishi , Yasuo Nakano , Hirokazu Kawahara
IPC分类号： G06F1/04
CPC分类号： G06F1/324 , G06F1/3203 , H03L7/06 , H03L7/07 , H03L7/0991 , H03L7/16 , Y02D10/126
摘要： A frequency control apparatus and an information processing apparatus includes an observation section for observing an operation state of a control object which operates with a variably controlled frequency, a frequency determination section for determining a clock frequency in response to the operation state, and a frequency limitation section for limiting a range or a value of the clock frequency determined by the frequency determination section. If the frequency determined in response to the operation state of the control object is within an allowable range, the control is performed with the frequency, but if the frequency is outside the allowable range, the frequency is limited to the range.
摘要翻译：频率控制装置和信息处理装置包括：用于观察以可变控制频率工作的控制对象的操作状态的观察部，响应于操作状态确定时钟频率的频率确定部，以及频率限制用于限制由频率确定部分确定的时钟频率的范围或值。如果响应于控制对象的操作状态而确定的频率在容许范围内，则以频率进行控制，但是如果频率在容许范围之外，则频率被限制在该范围内。

7. 发明申请

US20070294446A1 INFORMATION PROCESSING APPARATUS, METHOD OF SAME, AND PROGRAM FOR SAME 失效
标题翻译：信息处理装置，其方法和程序
公开(公告)号：US20070294446A1
公开(公告)日：2007-12-20
申请号：US11736323
申请日：2007-04-17
申请人： Yoshito Nagao , Takeshi Shimoyama
发明人： Yoshito Nagao , Takeshi Shimoyama
IPC分类号： G06F13/00
CPC分类号： G06F13/3625 , G06F13/364
摘要： An information processing apparatus configured to control communications of a plurality of devices via a common communication channel on the basis of predetermined priority levels of the devices includes a changing unit configured to change the priority level of a predetermined device, which is one of the plurality of devices, having a first priority level to a second priority level for a predetermined amount of time and a controlling unit configured to control the length of the predetermined amount of time.
摘要翻译：一种信息处理装置，被配置为基于设备的预定优先级来经由公共通信信道来控制多个设备的通信，所述信息处理设备包括：改变单元，被配置为改变作为所述多个设备中的一个的预定设备的优先级; 设备，具有预定时间量的第一优先级到第二优先级;以及控制单元，被配置为控制预定时间量的长度。

8. 发明申请

US20060058897A1 On-vehicle power supplying apparatus with two power supplies 审中-公开
标题翻译：车载供电装置带有两个电源
公开(公告)号：US20060058897A1
公开(公告)日：2006-03-16
申请号：US11209816
申请日：2005-08-24
申请人： Takashi Senda , Akira Kato , Katsunori Tanaka , Takeshi Shimoyama
发明人： Takashi Senda , Akira Kato , Katsunori Tanaka , Takeshi Shimoyama
IPC分类号： G05B11/01 , G05D11/00 , G05D17/00 , G05D3/12 , G05D5/00 , G05D9/00
CPC分类号： B60R16/03 , B60L58/12 , B60L58/20 , F02N11/0814 , F02N11/0866 , Y02T10/7005 , Y02T10/7044 , Y02T10/7066
摘要： An on-vehicle power supplying apparatus comprises a first battery charged by a generator driven by an on-vehicle engine, a second battery connected to an on-vehicle electric load, and a power adjuster adjusting power to be supplied from both of the first and second batteries to the electric load. For adjusting the power, he power adjuster uses a predetermined order in which the first battery is firstly made to supply the power to the electric load, provided that a residual capacity of the first battery is higher than a predetermined threshold, before making both the first and second batteries supply the power to the electric load cooperatively.
摘要翻译：车载供电装置包括由车载发动机驱动的发电机充电的第一电池，连接到车载电力负载的第二电池以及从第一和第二电力供应装置供电的电力调节器第二个电池到电动负载。为了调整功率，如果第一电池的剩余容量高于预定阈值，则电力调节器使用首先使第一电池向电负载供电的预定顺序，并且第二电池协同地向电负载供电。

9. 发明授权

US08350421B2 Motor and it's manufacturing method 有权
标题翻译：电机及其制造方法
公开(公告)号：US08350421B2
公开(公告)日：2013-01-08
申请号：US12352329
申请日：2009-01-12
申请人： Takeshi Shimoyama
发明人： Takeshi Shimoyama
IPC分类号： H02K37/00
CPC分类号： H02K15/022 , H02K5/15 , H02K5/161 , Y10T29/49009
摘要： A motor may include a stator formed with a rotor arrangement hole, a rotor disposed in the rotor arrangement hole, and a plate-like member disposed on at least one end side in an axial direction of the stator. The plate-like member is joined with an end face of the stator structured such that a peripheral edge part of the plate-like member is melted. In this case, it is preferable that the peripheral edge part of the plate-like member is joined with the end face of the stator structured such that an edge part on an opposite side to a face contacting with the end face of the stator is melted by irradiation of a laser beam.
摘要翻译：电动机可以包括形成有转子布置孔的定子，设置在转子布置孔中的转子和设置在定子的轴向方向上的至少一个端侧的板状构件。板状构件与定子的端面结合，使得板状构件的周缘部分熔化。在这种情况下，优选的是，板状构件的周边部分与定子的端面结合，使得与与定子的端面接触的面相反侧的边缘部分熔化通过照射激光束。

10. 发明授权

US08065458B2 Arbitration apparatus, method, and computer readable medium with dynamically adjustable priority scheme 失效
标题翻译：仲裁设备，方法和具有动态可调优先级方案的计算机可读介质
公开(公告)号：US08065458B2
公开(公告)日：2011-11-22
申请号：US11736323
申请日：2007-04-17
申请人： Yoshito Nagao , Takeshi Shimoyama
发明人： Yoshito Nagao , Takeshi Shimoyama
IPC分类号： G06F3/00 , G06F5/00 , G06F12/00 , G06F13/14 , G06F13/38
CPC分类号： G06F13/3625 , G06F13/364
摘要： An information processing apparatus configured to control communications of a plurality of devices via a common communication channel on the basis of predetermined priority levels of the devices includes a changing unit configured to change the priority level of a predetermined device, which is one of the plurality of devices, having a first priority level to a second priority level for a predetermined amount of time and a controlling unit configured to control the length of the predetermined amount of time.
摘要翻译：一种信息处理装置，被配置为基于设备的预定优先级来经由公共通信信道来控制多个设备的通信，所述信息处理设备包括：改变单元，被配置为改变作为所述多个设备中的一个的预定设备的优先级; 设备，具有预定时间量的第一优先级到第二优先级;以及控制单元，被配置为控制预定时间量的长度。

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