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    • 1. 发明授权
    • Information processing apparatus working at variable operating frequency
    • 以可变工作频率工作的信息处理设备
    • US07793134B2
    • 2010-09-07
    • US11943092
    • 2007-11-20
    • Takeshi Shimoyama
    • Takeshi Shimoyama
    • G06F1/00
    • G06F13/4243
    • An information processing apparatus includes a clock signal generator unit that generates a clock signal which is variable in frequency. The information processing apparatus also includes a timing information calculator unit that calculates timing information corresponding to frequency information about the clock signal and acquires the frequency information before a variation in the clock signal. The information processing apparatus further includes an information processor unit that executes an information processing operation for a memory at an execution timing which is controlled by the timing information. The clock signal is supplied to the information processor unit as an operating clock signal. The timing information calculator unit determines whether an address of the memory of a previous information processing operation matches with an address of the memory of the information processing operation to produce a determination result and calculates the timing information based on the determination result.
    • 信息处理装置包括:时钟信号发生器单元,其生成频率可变的时钟信号。 信息处理装置还包括定时信息计算器单元,其计算与时钟信号相关的频率信息的定时信息,并且在时钟信号变化之前获取频率信息。 信息处理装置还包括信息处理单元,该信息处理单元在由定时信息控制的执行定时执行存储器的信息处理操作。 时钟信号作为操作时钟信号提供给信息处理器单元。 定时信息计算单元确定先前的信息处理操作的存储器的地址是否与信息处理操作的存储器的地址匹配以产生确定结果,并且基于确定结果来计算定时信息。
    • 2. 发明申请
    • MEMORY ACCESS CONTROL APPARATUS AND IMAGE PICKUP APPARATUS
    • 存储器访问控制装置和图像拾取装置
    • US20100007770A1
    • 2010-01-14
    • US12487124
    • 2009-06-18
    • Tomohiro KOGANEZAWATakeshi ShimoyamaKingo KoyamaTakuji Himeno
    • Tomohiro KOGANEZAWATakeshi ShimoyamaKingo KoyamaTakuji Himeno
    • H04N5/225G06F12/02
    • H04N5/232G06F13/1689H04N5/23245
    • A memory access control apparatus includes a memory controller controlling a memory adopting a DDR format; a DDR-PHY adjusting the timing of an interface signal between the memory controller and the memory; a DDR-PHY controller controlling the DDR-PHY; and a clock controller controlling the frequency of a clock signal. A first request signal for controlling the operation of the memory in a self-refresh mode is supplied to the memory controller, a second request signal for resetting the DDR-PHY is supplied to the DDR-PHY controller, a third request signal for changing the clock frequency is supplied to the clock controller, a fourth request signal for setting a parameter for the DDR-PHY is supplied to the DDR-PHY controller, and a fifth request signal for canceling the operation of the memory in the self-refresh mode is supplied to the memory controller in order to change the clock frequency of the memory.
    • 存储器访问控制装置包括控制采用DDR格式的存储器的存储器控​​制器; DDR-PHY调整存储器控制器和存储器之间的接口信号的定时; 控制DDR-PHY的DDR-PHY控制器; 以及控制时钟信号的频率的时钟控制器。 用于在自刷新模式下控制存储器的操作的第一请求信号被提供给存储器控制器,用于复位DDR-PHY的第二请求信号被提供给DDR-PHY控制器,第三请求信号用于改变 将时钟频率提供给时钟控制器,将用于设置DDR-PHY的参数的第四请求信号提供给DDR-PHY控制器,并且用于在自刷新模式下取消存储器的操作的第五请求信号是 提供给存储器控制器以便改变存储器的时钟频率。
    • 6. 发明授权
    • Motor and it's manufacturing method
    • 电机及其制造方法
    • US08350421B2
    • 2013-01-08
    • US12352329
    • 2009-01-12
    • Takeshi Shimoyama
    • Takeshi Shimoyama
    • H02K37/00
    • H02K15/022H02K5/15H02K5/161Y10T29/49009
    • A motor may include a stator formed with a rotor arrangement hole, a rotor disposed in the rotor arrangement hole, and a plate-like member disposed on at least one end side in an axial direction of the stator. The plate-like member is joined with an end face of the stator structured such that a peripheral edge part of the plate-like member is melted. In this case, it is preferable that the peripheral edge part of the plate-like member is joined with the end face of the stator structured such that an edge part on an opposite side to a face contacting with the end face of the stator is melted by irradiation of a laser beam.
    • 电动机可以包括形成有转子布置孔的定子,设置在转子布置孔中的转子和设置在定子的轴向方向上的至少一个端侧的板状构件。 板状构件与定子的端面结合,使得板状构件的周缘部分熔化。 在这种情况下,优选的是,板状构件的周边部分与定子的端面结合,使得与与定子的端面接触的面相反侧的边缘部分熔化 通过照射激光束。
    • 8. 发明授权
    • Information processing device, method, and program
    • 信息处理装置,方法和程序
    • US07493508B2
    • 2009-02-17
    • US10527063
    • 2003-07-30
    • Takeshi Shimoyama
    • Takeshi Shimoyama
    • G06F13/00
    • G06F9/3869G06F7/00G06F2207/3884
    • This invention relates to an information processing apparatus as well as to an information processing method and a program for use therewith, the apparatus being arranged to prevent a drop in its processing performance while minimizing power dissipation when a frequency-variable synchronizing clock signal CLK of the apparatus is lowered in frequency. Illustratively, if a selector block 31-2 receives a selection command “select B” which is set depending on the frequency of the synchronizing clock signal CLK and which specifies the bypassing of a holding block 12-2, then data input to and held by a holding block 12-1 on a first clock pulse of the clock signal CLK is arranged, on a second clock pulse, to pass through a selector block 31-1 and a signal processing block 13-1, bypass the holding block 12-2, pass through the selector block 31-2 and a signal processing block 13-2, and be input to and held by a holding block 12-3. This invention applies to data processing apparatuses such as CPUs, DSPs and filters as well as to buses.
    • 本发明涉及一种信息处理设备以及信息处理方法和与其一起使用的程序,该设备被布置为在最小化功率耗散的同时防止其处理性能的下降,当该频率可变同步时钟信号CLK 设备的频率降低。 说明性地,如果选择器块31-2接收到根据同步时钟信号CLK的频率设定并且指定保持块12-2的旁路设置的选择命令“选择B”,则输入到和保持的数据 时钟信号CLK的第一时钟脉冲上的保持块12-1在第二时钟脉冲上被布置成通过选择器块31-1和信号处理块13-1,绕过保持块12-2 通过选择器块31-2和信号处理块13-2,并被保持块12-3输入并保持。 本发明适用于诸如CPU,DSP和滤波器以及总线的数据处理设备。
    • 9. 发明申请
    • INFORMATION PROCESSING APPARATUS WORKING AT VARIABLE OPERATING FREQUENCY
    • 信息处理设备在可变操作频率下工作
    • US20080075214A1
    • 2008-03-27
    • US11943092
    • 2007-11-20
    • Takeshi Shimoyama
    • Takeshi Shimoyama
    • G06F1/04G06F1/12G06F5/06
    • G06F13/4243
    • An information processing apparatus and an information processing method for use therewith are provided so as to implement optimal signal processing without deterioration of performance when using variable operating frequencies. A frequency information operating section (12) of the apparatus adds a corresponding signal cycle to frequency information Inf about a synchronizing clock signal CLKv having a variable frequency. An information processing section of the apparatus is supplied with the synchronizing clock signal as an operating clock signal, and processes information when results of the addition by the frequency information operating section (12) meet a predetermined condition. Optimized processing is thus accomplished in a manner eliminating wasteful latency times.
    • 提供一种使用它的信息处理装置和信息处理方法,以便在使用可变工作频率时实现最佳信号处理而不会降低性能。 设备的频率信息操作部分(12)将相应的信号周期添加到具有可变频率的同步时钟信号CLKv的频率信息Inf。 该装置的信息处理部分被提供有作为操作时钟信号的同步时钟信号,并且当频率信息操作部分(12)的相加结果达到预定条件时处理信息。 因此,以一种消除浪费的延迟时间的方式来实现优化的处理。