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1. 发明申请

US20070161156A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070161156A1
公开(公告)日：2007-07-12
申请号：US11687981
申请日：2007-03-19
申请人： Kazutoshi Shiba , Hiroyuki Kunishima
发明人： Kazutoshi Shiba , Hiroyuki Kunishima
IPC分类号： H01L21/00
CPC分类号： H01L23/5329 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： There is provided a method of manufacturing a semiconductor device in which interconnect capacitance is restrained. The semiconductor device 200 comprises a semiconductor substrate; a second interconnect insulating film 216 constituted of a ladder-type hydrogen siloxane formed on the semiconductor substrate; a second protection film 217 provided on the second interconnect insulating film 216; and an upper interconnect 270 formed in the second interconnect insulating film 216 and the second protection film 217. The second interconnect insulating film 216 is constituted of for example an L-Ox™ (trademark) film, and the second protection film 217 is constituted of for example a silicon oxide film.
摘要翻译：提供一种制造半导体器件的方法，其中互连电容被抑制。半导体器件200包括半导体衬底; 由在半导体衬底上形成的梯型氢硅氧烷构成的第二互连绝缘膜216; 设置在第二互连绝缘膜216上的第二保护膜217; 以及形成在第二互连绝缘膜216和第二保护膜217中的上互连270。第二互连绝缘膜216由例如L-Ox TM（商标）膜构成，第二保护膜217由例如氧化硅膜构成。

2. 发明授权

US07211896B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07211896B2
公开(公告)日：2007-05-01
申请号：US10767335
申请日：2004-01-30
申请人： Kazutoshi Shiba , Hiroyuki Kunishima
发明人： Kazutoshi Shiba , Hiroyuki Kunishima
IPC分类号： H01L23/48 , H01L29/40 , H01L214/763 , H01L21/44
CPC分类号： H01L23/5329 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： There is provided a method of manufacturing a semiconductor device in which interconnect capacitance is restrained. The semiconductor device 200 comprises a semiconductor substrate; a second interconnect insulating film 216 constituted of a ladder-type hydrogen siloxane formed on the semiconductor substrate; a second protection film 217 provided on the second interconnect insulating film 216; and an upper interconnect 270 formed in the second interconnect insulating film 216 and the second protection film 217. The second interconnect insulating film 216 is constituted of for example an L-Ox™ (trademark) film, and the second protection film 217 is constituted of for example a silicon oxide film.
摘要翻译：提供一种制造半导体器件的方法，其中互连电容被抑制。半导体器件200包括半导体衬底; 由在半导体衬底上形成的梯型氢硅氧烷构成的第二互连绝缘膜216; 设置在第二互连绝缘膜216上的第二保护膜217; 以及形成在第二互连绝缘膜216和第二保护膜217中的上互连270。第二互连绝缘膜216由例如L-Ox TM（商标）膜构成，第二保护膜217由例如氧化硅膜构成。

3. 发明授权

US06459126B1 Semiconductor device including a MIS transistor 有权
标题翻译：包括MIS晶体管的半导体器件
公开(公告)号：US06459126B1
公开(公告)日：2002-10-01
申请号：US09852658
申请日：2001-05-11
申请人： Tohru Mogami , Mitsuhiro Togo , Koji Watanabe , Toyoji Yamamoto , Nobuyuki Ikarashi , Kazutoshi Shiba , Toru Tatsumi , Haruhiko Ono
发明人： Tohru Mogami , Mitsuhiro Togo , Koji Watanabe , Toyoji Yamamoto , Nobuyuki Ikarashi , Kazutoshi Shiba , Toru Tatsumi , Haruhiko Ono
IPC分类号： H01L2362
CPC分类号： H01L21/28185 , H01L21/28202 , H01L21/823462 , H01L29/513 , H01L29/518 , H01L2924/0002 , H01L2924/00
摘要： A MIS transistor has a gate insulating film made of silicon oxynitride and having a specific dielectric constant which is larger than the expected specific dielectric constant calculated based on a weighted average of the specific dielectric constants based on the weight ratio of the silicon oxide and the silicon nitride contained in the silicon oxynitride film. The gate insulating film having a smaller thickness prevents impurities in the overlying gate electrode from penetrating through the gate insulating film to degrade the silicon substrate.
摘要翻译： MIS晶体管具有由氮氧化硅制成的栅极绝缘膜，其具有比基于氧化硅和硅的重量比的基于特定介电常数的加权平均值计算的预期比介电常数的比介电常数包含在氮氧化硅膜中的氮化物。具有较小厚度的栅极绝缘膜防止上覆栅极电极中的杂质穿过栅极绝缘膜而劣化硅衬底。

4. 发明授权

US07217654B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07217654B2
公开(公告)日：2007-05-15
申请号：US10969429
申请日：2004-10-21
申请人： Seiji Nagahara , Kazutoshi Shiba , Nobuaki Hamanaka , Tatsuya Usami , Takashi Yokoyama
发明人： Seiji Nagahara , Kazutoshi Shiba , Nobuaki Hamanaka , Tatsuya Usami , Takashi Yokoyama
IPC分类号： H01L21/4763
CPC分类号： H01L21/02063 , H01L21/31116 , H01L21/31138 , H01L21/76807 , H01L21/76808 , H01L21/76811 , H01L21/76825 , H01L21/76828 , H01L21/76831
摘要： A method of manufacturing a semiconductor device having a damascene structure contains a process of forming a first interlayer insulating film (6) and a second interlayer insulating film (4) formed of a low dielectric-constant film on a substrate, forming via holes (9) by using a first resist pattern (1a) formed on the second interlayer insulating film, conducting an organic peeling treatment using organic peeling liquid containing amine components and then forming a second resist pattern (1b) on the second interlayer insulating film. After the wet treatment, before a second antireflection coating (2b) is coated so as to be located below the second resist pattern is coated, at least one of an annealing treatment, a plasma treatment, a UV treatment and an organic solvent treatment is carried out to remove amine components which inhibit the catalysis reaction of acid occurring in the resist at the light exposure, thereby preventing degradation of the resolution of the second resist pattern (1b).
摘要翻译：一种制造具有镶嵌结构的半导体器件的方法包括在衬底上形成第一层间绝缘膜（6）和由低介电常数膜形成的第二层间绝缘膜（4）的工艺，形成通孔（9 ）通过使用形成在第二层间绝缘膜上的第一抗蚀剂图案（1a），使用含有胺成分的有机剥离液进行有机剥离处理，然后在第二层间绝缘膜上形成第二抗蚀剂图案（1b）。在湿处理之后，涂覆第二抗反射涂层（2b）以便位于第二抗蚀图案下方的涂层，退火处理，等离子体处理，UV处理和有机溶剂处理中的至少一个是进行以除去抑制在曝光时在抗蚀剂中发生的酸的催化反应的胺成分，从而防止第二抗蚀剂图案（1b）的分辨率的劣化。

5. 发明申请

US20070096331A1 Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070096331A1
公开(公告)日：2007-05-03
申请号：US11640349
申请日：2006-12-18
申请人： Seiji Nagahara , Kazutoshi Shiba , Nobuaki Hamanaka , Tatsuya Usami , Takashi Yokoyama
发明人： Seiji Nagahara , Kazutoshi Shiba , Nobuaki Hamanaka , Tatsuya Usami , Takashi Yokoyama
IPC分类号： H01L23/48
CPC分类号： H01L21/02063 , H01L21/31116 , H01L21/31138 , H01L21/76807 , H01L21/76808 , H01L21/76811 , H01L21/76825 , H01L21/76828 , H01L21/76831
摘要： A method of manufacturing a semiconductor device having a damascene structure contains a process of forming a first interlayer insulating film and a second interlayer insulating film formed of a low dielectric constant film on a substrate, forming via holes by using a first resist pattern formed on the second interlayer insulating film, conducting an organic peeling treatment using organic peeling liquid containing amine components and then forming a second resist pattern on the second interlayer insulating film. After the wet treatment before a second antireflection coating is coated so as to be located below the second resist pattern is coated, at least one of an annealing treatment, a plasma treatment, a UV treatment and an organic solvent treatment is carried out to remove amine components which inhibit the catalysis reaction of acid occurring in the resist at the light exposure, thereby preventing degradation of the resolution of the second resist pattern.
摘要翻译：一种制造具有镶嵌结构的半导体器件的方法包括在基板上形成第一层间绝缘膜和由低介电常数膜形成的第二层间绝缘膜的工艺，通过使用形成在第一层上绝缘膜上的第一抗蚀剂图案形成通孔第二层间绝缘膜，使用含有胺成分的有机剥离液进行有机剥离处理，然后在第二层间绝缘膜上形成第二抗蚀剂图案。在第二抗反射涂层涂布第二抗蚀剂图案之下的湿处理之后，涂覆第二抗蚀图案，进行退火处理，等离子体处理，UV处理和有机溶剂处理中的至少一种以除去胺抑制在曝光时在抗蚀剂中发生的酸的催化反应的成分，从而防止第二抗蚀剂图案的分辨率的劣化。

6. 发明授权

US06821687B2 Photo mask for fabricating semiconductor device having dual damascene structure 有权
标题翻译：用于制造具有双镶嵌结构的半导体器件的光掩模
公开(公告)号：US06821687B2
公开(公告)日：2004-11-23
申请号：US10112716
申请日：2002-04-02
申请人： Nobuaki Hamanaka , Takashi Yokoyama , Kazutoshi Shiba , Noriaki Oda
发明人： Nobuaki Hamanaka , Takashi Yokoyama , Kazutoshi Shiba , Noriaki Oda
IPC分类号： G03F900
CPC分类号： G03F9/7076 , G03F1/42 , H01L21/76807 , H01L2221/1036
摘要： A photo mask for fabricating a semiconductor device having a dual damascene structure which has a via coupled with a lower wiring layer and has an upper wiring layer coupled with the via. The via and the upper wiring layer are fabricated by filling a via hole and a wiring groove formed in an interlayer insulating film that is formed on the lower wiring layer with a wiring material. The photo mask has a via alignment mark which is used for aligning the via hole with respect to the lower wiring layer and/or a via alignment mark which is used for aligning the wiring groove with respect to the via hole. The width of the via alignment mark is equal to or larger than the width which is optically detectable and an aspect ratio of the via alignment mark is equal to or larger than one fourth of the aspect ratio of the via hole. Preferably, the width of the via alignment mark is equal to or larger than the width of the via hole.
摘要翻译：一种用于制造具有双镶嵌结构的半导体器件的光掩模，其具有与下布线层耦合的通孔，并且具有与通孔耦合的上布线层。通孔和上部布线层通过在布线层下方填充形成在层间绝缘膜上的通孔和布线槽来制造。光掩模具有用于使通孔相对于下布线层对准的通孔对准标记和/或用于使布线槽相对于通孔对准的通孔对准标记。通孔对准标记的宽度等于或大于可光学检测的宽度，并且通孔对准标记的纵横比等于或大于通孔的纵横比的四分之一。优选地，通孔对准标记的宽度等于或大于通孔的宽度。

7. 发明申请

US20050124168A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050124168A1
公开(公告)日：2005-06-09
申请号：US10969429
申请日：2004-10-21
申请人： Seiji Nagahara , Kazutoshi Shiba , Nobuaki Hamanaka , Tatsuya Usami , Takashi Yokoyama
发明人： Seiji Nagahara , Kazutoshi Shiba , Nobuaki Hamanaka , Tatsuya Usami , Takashi Yokoyama
IPC分类号： G03F7/38 , H01L21/027 , H01L21/311 , H01L21/768 , H01L21/00 , H01L21/302 , H01L21/461 , H01L21/84
CPC分类号： H01L21/02063 , H01L21/31116 , H01L21/31138 , H01L21/76807 , H01L21/76808 , H01L21/76811 , H01L21/76825 , H01L21/76828 , H01L21/76831
摘要： A method of manufacturing a semiconductor device having a damascene structure contains a process of forming a first interlayer insulating film (6) and a second interlayer insulating film (4) formed of a low dielectric-constant film on a substrate, forming via holes (9) by using a first resist pattern (1a) formed on the second interlayer insulating film, conducting an organic peeling treatment using organic peeling liquid containing amine components and then forming a second resist pattern (1b) on the second interlayer insulating film. After the wet treatment, before a second antireflection coating (2b) is coated so as to be located below the second resist pattern is coated, at least one of an annealing treatment, a plasma treatment, a UV treatment and an organic solvent treatment is carried out to remove amine components which inhibit the catalysis reaction of acid occurring in the resist at the light exposure, thereby preventing degradation of the resolution of the second resist pattern (1b).
摘要翻译：一种制造具有镶嵌结构的半导体器件的方法包括在衬底上形成第一层间绝缘膜（6）和由低介电常数膜形成的第二层间绝缘膜（4）的工艺，形成通孔（9 ）通过使用形成在第二层间绝缘膜上的第一抗蚀剂图案（1a），使用含有胺成分的有机剥离液进行有机剥离处理，然后在第二层间绝缘膜上形成第二抗蚀剂图案（1b）。在湿处理之后，涂覆第二抗反射涂层（2b）以便位于第二抗蚀图案下方的涂层，退火处理，等离子体处理，UV处理和有机溶剂处理中的至少一个是进行以除去抑制在曝光时在抗蚀剂中发生的酸的催化反应的胺成分，从而防止第二抗蚀剂图案（1b）的分辨率的劣化。

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