专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20050124168A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050124168A1
公开(公告)日：2005-06-09
申请号：US10969429
申请日：2004-10-21
申请人： Seiji Nagahara , Kazutoshi Shiba , Nobuaki Hamanaka , Tatsuya Usami , Takashi Yokoyama
发明人： Seiji Nagahara , Kazutoshi Shiba , Nobuaki Hamanaka , Tatsuya Usami , Takashi Yokoyama
IPC分类号： G03F7/38 , H01L21/027 , H01L21/311 , H01L21/768 , H01L21/00 , H01L21/302 , H01L21/461 , H01L21/84
CPC分类号： H01L21/02063 , H01L21/31116 , H01L21/31138 , H01L21/76807 , H01L21/76808 , H01L21/76811 , H01L21/76825 , H01L21/76828 , H01L21/76831
摘要： A method of manufacturing a semiconductor device having a damascene structure contains a process of forming a first interlayer insulating film (6) and a second interlayer insulating film (4) formed of a low dielectric-constant film on a substrate, forming via holes (9) by using a first resist pattern (1a) formed on the second interlayer insulating film, conducting an organic peeling treatment using organic peeling liquid containing amine components and then forming a second resist pattern (1b) on the second interlayer insulating film. After the wet treatment, before a second antireflection coating (2b) is coated so as to be located below the second resist pattern is coated, at least one of an annealing treatment, a plasma treatment, a UV treatment and an organic solvent treatment is carried out to remove amine components which inhibit the catalysis reaction of acid occurring in the resist at the light exposure, thereby preventing degradation of the resolution of the second resist pattern (1b).
摘要翻译：一种制造具有镶嵌结构的半导体器件的方法包括在衬底上形成第一层间绝缘膜（6）和由低介电常数膜形成的第二层间绝缘膜（4）的工艺，形成通孔（9 ）通过使用形成在第二层间绝缘膜上的第一抗蚀剂图案（1a），使用含有胺成分的有机剥离液进行有机剥离处理，然后在第二层间绝缘膜上形成第二抗蚀剂图案（1b）。在湿处理之后，涂覆第二抗反射涂层（2b）以便位于第二抗蚀图案下方的涂层，退火处理，等离子体处理，UV处理和有机溶剂处理中的至少一个是进行以除去抑制在曝光时在抗蚀剂中发生的酸的催化反应的胺成分，从而防止第二抗蚀剂图案（1b）的分辨率的劣化。

2. 发明授权

US07217654B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07217654B2
公开(公告)日：2007-05-15
申请号：US10969429
申请日：2004-10-21
申请人： Seiji Nagahara , Kazutoshi Shiba , Nobuaki Hamanaka , Tatsuya Usami , Takashi Yokoyama
发明人： Seiji Nagahara , Kazutoshi Shiba , Nobuaki Hamanaka , Tatsuya Usami , Takashi Yokoyama
IPC分类号： H01L21/4763
CPC分类号： H01L21/02063 , H01L21/31116 , H01L21/31138 , H01L21/76807 , H01L21/76808 , H01L21/76811 , H01L21/76825 , H01L21/76828 , H01L21/76831
摘要： A method of manufacturing a semiconductor device having a damascene structure contains a process of forming a first interlayer insulating film (6) and a second interlayer insulating film (4) formed of a low dielectric-constant film on a substrate, forming via holes (9) by using a first resist pattern (1a) formed on the second interlayer insulating film, conducting an organic peeling treatment using organic peeling liquid containing amine components and then forming a second resist pattern (1b) on the second interlayer insulating film. After the wet treatment, before a second antireflection coating (2b) is coated so as to be located below the second resist pattern is coated, at least one of an annealing treatment, a plasma treatment, a UV treatment and an organic solvent treatment is carried out to remove amine components which inhibit the catalysis reaction of acid occurring in the resist at the light exposure, thereby preventing degradation of the resolution of the second resist pattern (1b).
摘要翻译：一种制造具有镶嵌结构的半导体器件的方法包括在衬底上形成第一层间绝缘膜（6）和由低介电常数膜形成的第二层间绝缘膜（4）的工艺，形成通孔（9 ）通过使用形成在第二层间绝缘膜上的第一抗蚀剂图案（1a），使用含有胺成分的有机剥离液进行有机剥离处理，然后在第二层间绝缘膜上形成第二抗蚀剂图案（1b）。在湿处理之后，涂覆第二抗反射涂层（2b）以便位于第二抗蚀图案下方的涂层，退火处理，等离子体处理，UV处理和有机溶剂处理中的至少一个是进行以除去抑制在曝光时在抗蚀剂中发生的酸的催化反应的胺成分，从而防止第二抗蚀剂图案（1b）的分辨率的劣化。

3. 发明申请

US20070096331A1 Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070096331A1
公开(公告)日：2007-05-03
申请号：US11640349
申请日：2006-12-18
申请人： Seiji Nagahara , Kazutoshi Shiba , Nobuaki Hamanaka , Tatsuya Usami , Takashi Yokoyama
发明人： Seiji Nagahara , Kazutoshi Shiba , Nobuaki Hamanaka , Tatsuya Usami , Takashi Yokoyama
IPC分类号： H01L23/48
CPC分类号： H01L21/02063 , H01L21/31116 , H01L21/31138 , H01L21/76807 , H01L21/76808 , H01L21/76811 , H01L21/76825 , H01L21/76828 , H01L21/76831
摘要： A method of manufacturing a semiconductor device having a damascene structure contains a process of forming a first interlayer insulating film and a second interlayer insulating film formed of a low dielectric constant film on a substrate, forming via holes by using a first resist pattern formed on the second interlayer insulating film, conducting an organic peeling treatment using organic peeling liquid containing amine components and then forming a second resist pattern on the second interlayer insulating film. After the wet treatment before a second antireflection coating is coated so as to be located below the second resist pattern is coated, at least one of an annealing treatment, a plasma treatment, a UV treatment and an organic solvent treatment is carried out to remove amine components which inhibit the catalysis reaction of acid occurring in the resist at the light exposure, thereby preventing degradation of the resolution of the second resist pattern.
摘要翻译：一种制造具有镶嵌结构的半导体器件的方法包括在基板上形成第一层间绝缘膜和由低介电常数膜形成的第二层间绝缘膜的工艺，通过使用形成在第一层上绝缘膜上的第一抗蚀剂图案形成通孔第二层间绝缘膜，使用含有胺成分的有机剥离液进行有机剥离处理，然后在第二层间绝缘膜上形成第二抗蚀剂图案。在第二抗反射涂层涂布第二抗蚀剂图案之下的湿处理之后，涂覆第二抗蚀图案，进行退火处理，等离子体处理，UV处理和有机溶剂处理中的至少一种以除去胺抑制在曝光时在抗蚀剂中发生的酸的催化反应的成分，从而防止第二抗蚀剂图案的分辨率的劣化。

4. 发明授权

US06255732B1 Semiconductor device and process for producing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06255732B1
公开(公告)日：2001-07-03
申请号：US09366517
申请日：1999-08-03
申请人： Takashi Yokoyama , Tatsuya Usami
发明人： Takashi Yokoyama , Tatsuya Usami
IPC分类号： H01L2348
CPC分类号： H01L21/76834 , H01L21/76801 , H01L21/76802 , H01L21/76814 , H01L21/76826 , H01L21/76828 , H01L21/76831 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An interlayer insulation film containing a dielectric component represented by a chemical formula having a Si—H bond or a Si—CH3 bond is formed on a substrate. Next, a photoresist is formed on the interlayer insulation film. The photoresist is then formed into a form of a contact hole. Thereafter, dry-etching of the interlayer insulation film is conducted by use of the photoresist as a mask. Subsequently, the photoresist is removed, and the interlayer insulation film is exposed to nitrogen plasma and hydrogen plasma, for example.
摘要翻译：在基板上形成含有由Si-H键或Si-CH3键形成的化学式表示的介电成分的层间绝缘膜。接着，在层间绝缘膜上形成光致抗蚀剂。然后将光致抗蚀剂形成为接触孔的形式。此后，通过使用光致抗蚀剂作为掩模进行层间绝缘膜的干法蚀刻。随后，除去光致抗蚀剂，并且例如将层间绝缘膜暴露于氮等离子体和氢等离子体。

5. 发明授权

US06479407B2 Semiconductor device and process for producing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06479407B2
公开(公告)日：2002-11-12
申请号：US09770114
申请日：2001-01-23
申请人： Takashi Yokoyama , Tatsuya Usami
发明人： Takashi Yokoyama , Tatsuya Usami
IPC分类号： H01L2131
CPC分类号： H01L21/76834 , H01L21/76801 , H01L21/76802 , H01L21/76814 , H01L21/76826 , H01L21/76828 , H01L21/76831 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An interlayer insulation film containing a dielectric component represented by a chemical formula having a Si—E bond or a Si—CH3 bond is formed on a substrate. Next, a photoresist is formed on the interlayer insulation film. The photoresist is then formed into a form of a contact hole. Thereafter, dry-etching of the interlayer insulation film is conducted by use of the photoresist as a mask. Subsequently, the photoresist is removed, and the interlayer insulation film is exposed to nitrogen plasma and hydrogen plasma, for example.
摘要翻译：在基板上形成含有由具有Si-E键或Si-CH3键的化学式表示的电介质成分的层间绝缘膜。接着，在层间绝缘膜上形成光致抗蚀剂。然后将光致抗蚀剂形成为接触孔的形式。此后，通过使用光致抗蚀剂作为掩模进行层间绝缘膜的干法蚀刻。随后，除去光致抗蚀剂，并且例如将层间绝缘膜暴露于氮等离子体和氢等离子体。

6. 发明授权

US08749058B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08749058B2
公开(公告)日：2014-06-10
申请号：US13324925
申请日：2011-12-13
申请人： Tatsuya Usami , Hideaki Tsuchiya , Yukio Miura , Tomoyuki Nakamura , Koichi Ohto , Chikako Ohto , Shinji Yokogawa
发明人： Tatsuya Usami , Hideaki Tsuchiya , Yukio Miura , Tomoyuki Nakamura , Koichi Ohto , Chikako Ohto , Shinji Yokogawa
IPC分类号： H01L29/72
CPC分类号： H01L23/53295 , H01L21/0217 , H01L21/02211 , H01L21/02274 , H01L21/0234 , H01L21/3105 , H01L21/76826 , H01L21/76834 , H01L23/5226 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device includes an interlayer insulating film, a wiring provided in the interlayer insulating film, and a SiN film provided over the interlayer insulating film and over the wiring. The peak positions of Si—N bonds of the SiN film, which are measured by FTIR, are within the range of 845 cm−1 to 860 cm−1. This makes it possible to inhibit current leakage in a silicon nitride film, which is a barrier insulating film for preventing the diffusion of wiring metal.
摘要翻译：半导体器件包括层间绝缘膜，设置在层间绝缘膜中的布线以及设置在层间绝缘膜上并在布线上的SiN膜。通过FTIR测量的SiN膜的Si-N键的峰位置在845cm -1至860cm -1的范围内。这使得可以抑制作为用于防止布线金属扩散的阻挡绝缘膜的氮化硅膜中的电流泄漏。

7. 发明授权

US08617914B2 Method of forming semiconductor device having seal ring structure 有权
标题翻译：形成具有密封环结构的半导体器件的方法
公开(公告)号：US08617914B2
公开(公告)日：2013-12-31
申请号：US13137847
申请日：2011-09-16
申请人： Tatsuya Usami
发明人： Tatsuya Usami
IPC分类号： H01L21/00
CPC分类号： H01L21/76811 , H01L21/76808 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： A method of producing a semiconductor device includes forming, on a first insulating film formed on a substrate, a first groove in an element-forming region to form one of a via and a wiring therein, and a first seal ring groove in a seal ring part, forming one of a via and a wiring in the first groove and a first metal layer in the first seal ring groove, and then removing the metal material in a part exposed to an outside of the first groove and the first seal ring groove, forming a second insulating film on the first insulating film, forming, on the second insulating film, a second groove, and a second seal ring groove in the seal ring part on the first seal ring groove, and forming one of a via and a wiring in the second groove and a second metal layer.
摘要翻译：一种制造半导体器件的方法包括在形成在基板上的第一绝缘膜上形成元件形成区域中的第一槽，以在其中形成通孔和布线之一，以及密封环中的第一密封环槽在第一槽中形成通孔和配线之一，在第一密封环槽中形成第一金属层，然后在暴露于第一槽和第一密封环槽的外侧的部分除去金属材料，在所述第一绝缘膜上形成第二绝缘膜，在所述第二绝缘膜上形成所述第一密封环槽中的所述密封环部分中的第二槽和第二密封环槽，并且形成通孔和布线在第二槽和第二金属层中。

8. 发明申请

US20120181694A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120181694A1
公开(公告)日：2012-07-19
申请号：US13324925
申请日：2011-12-13
申请人： Tatsuya Usami , Hideaki Tsuchiya , Yukio Miura , Tomoyuki Nakamura , Koichi Ohto , Chikako Ohto , Shinji Yokogawa
发明人： Tatsuya Usami , Hideaki Tsuchiya , Yukio Miura , Tomoyuki Nakamura , Koichi Ohto , Chikako Ohto , Shinji Yokogawa
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L23/53295 , H01L21/0217 , H01L21/02211 , H01L21/02274 , H01L21/0234 , H01L21/3105 , H01L21/76826 , H01L21/76834 , H01L23/5226 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device includes an interlayer insulating film, a wiring provided in the interlayer insulating film, and a SiN film provided over the interlayer insulating film and over the wiring. The peak positions of Si—N bonds of the SiN film, which are measured by FTIR, are within the range of 845 cm−1 to 860 cm−1. This makes it possible to inhibit current leakage in a silicon nitride film, which is a barrier insulating film for preventing the diffusion of wiring metal.
摘要翻译：半导体器件包括层间绝缘膜，设置在层间绝缘膜中的布线以及设置在层间绝缘膜上并在布线上的SiN膜。通过FTIR测量的SiN膜的Si-N键的峰位置在845cm -1至860cm -1的范围内。这使得可以抑制作为用于防止布线金属扩散的阻挡绝缘膜的氮化硅膜中的电流泄漏。

9. 发明授权

US07969010B2 Semiconductor device and manufacturing process therefor 有权
标题翻译：半导体器件及其制造工艺
公开(公告)号：US07969010B2
公开(公告)日：2011-06-28
申请号：US11362110
申请日：2006-02-27
申请人： Tatsuya Usami
发明人： Tatsuya Usami
IPC分类号： H01L21/31
CPC分类号： H01L21/7682 , H01L21/76825 , H01L21/76829 , H01L21/76852 , H01L21/76885 , H01L21/76889 , H01L23/5222 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A semiconductor device has a semiconductor substrate, a first interconnect made of a copper-containing metal which is formed over the semiconductor substrate, a conductive first plug formed over the first interconnect and connected to the first interconnect, a Cu silicide layer over the first interconnect in an area other than the area where the first plug is formed, a Cu silicide layer over the first plug, and a first porous MSQ film formed over an area from the side surface of the first interconnect to the side surface of the first plug and covering the side surface of the first interconnect, the upper portion of the first interconnect and the side surface of the first plug.
摘要翻译：半导体器件具有半导体衬底，由半导体衬底上形成的含铜金属制成的第一互连，形成在第一互连上并连接到第一互连的导电第一插塞，第一互连上的铜硅化物层在除了形成第一插头的区域之外的区域中，在第一插头上方的Cu硅化物层和形成在从第一互连的侧表面到第一插头的侧表面的区域上的第一多孔MSQ膜，以及覆盖第一互连的侧表面，第一互连的上部和第一插塞的侧表面。

10. 发明授权

US07674721B2 Semiconductor device, semiconductor wafer, and methods of producing same device and wafer 有权
标题翻译：半导体器件，半导体晶片及其制造方法
公开(公告)号：US07674721B2
公开(公告)日：2010-03-09
申请号：US11797293
申请日：2007-05-02
申请人： Tatsuya Usami
发明人： Tatsuya Usami
IPC分类号： H01L21/316
CPC分类号： H01L21/76897 , H01L21/02134 , H01L21/02137 , H01L21/02164 , H01L21/022 , H01L21/02274 , H01L21/02282 , H01L21/3122 , H01L21/3124 , H01L21/76801 , H01L21/76828 , H01L21/76829 , H01L21/76832 , H01L21/76835 , H01L23/5329 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A method of forming a multi-layered insulation film includes forming a first insulation layer using a first feed gas, the first insulation layer including methyl silsesquioxane (MSQ), forming a second insulation layer using a second feed gas, the second insulation layer including a polysiloxane compound having an Si—H group such that the second insulation layer is in contact with a top of the first insulation layer, and forming a third insulation layer including an inorganic material such that the third insulation layer is in contact with a top of the second insulation layer.
摘要翻译：形成多层绝缘膜的方法包括使用第一进料气体形成第一绝缘层，第一绝缘层包括甲基硅倍半氧烷（MSQ），使用第二进料气体形成第二绝缘层，第二绝缘层包括具有Si-H基团的聚硅氧烷化合物，使得第二绝缘层与第一绝缘层的顶部接触，以及形成包含无机材料的第三绝缘层，使得第三绝缘层与第一绝缘层的顶部接触第二绝缘层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式