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1. 发明授权

US06545322B2 Semiconductor protection device 有权
标题翻译：半导体保护装置
公开(公告)号：US06545322B2
公开(公告)日：2003-04-08
申请号：US09998943
申请日：2001-10-31
申请人： Kazutoshi Ishii , Toshihiko Omi
发明人： Kazutoshi Ishii , Toshihiko Omi
IPC分类号： H01L2362
CPC分类号： H01L27/027
摘要： There is provided a semiconductor integrated circuit device with high electrostatic resistance. A semiconductor device is provided with a transistor for input-output protection having a desired size in which its channel length is varied with respect to a channel width direction.
摘要翻译：提供了具有高静电电阻的半导体集成电路器件。半导体器件设置有用于输入输出保护的晶体管，其具有其通道长度相对于沟道宽度方向变化的期望尺寸。

2. 发明授权

US06713820B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06713820B2
公开(公告)日：2004-03-30
申请号：US10119420
申请日：2002-04-08
申请人： Toshihiko Omi , Kazutoshi Ishii
发明人： Toshihiko Omi , Kazutoshi Ishii
IPC分类号： H01L2976
CPC分类号： H01L23/4824 , H01L21/823475 , H01L29/41758 , H01L29/4238 , H01L2924/0002 , Y10S257/902 , H01L2924/00
摘要： A semiconductor device is provided in which each of contacts between a source and a drain of a MOS transistor and a metallic wiring is either a contact having an arbitrary one side longer than the other side, or source contacts and well contacts are made batting contacts each having an arbitrary one side of a diffusion region having the same polarity as that of a well shorter than the other side. Thus, the contact shape is longitudinal in a transistor width direction, which makes it possible that a large current is caused to flow with a small interval of gates thereof.
摘要翻译：提供了一种半导体器件，其中MOS晶体管和金属布线的源极和漏极之间的每个触点是具有比另一侧长的任意一侧的触点，或者源极触点和阱触点各自成为击打触点具有与比另一侧短的阱极性相同极性的扩散区域的任意一侧。因此，接触形状在晶体管宽度方向上是纵向的，这使得可能以较小的间隔的栅极流过大电流。

3. 发明授权

US07161198B2 Semiconductor integrated circuit device having MOS transistor 失效
标题翻译：具有MOS晶体管的半导体集成电路器件
公开(公告)号：US07161198B2
公开(公告)日：2007-01-09
申请号：US10236413
申请日：2002-09-06
申请人： Toshihiko Omi , Hitomi Watanabe , Kazutoshi Ishii , Naoto Saitoh
发明人： Toshihiko Omi , Hitomi Watanabe , Kazutoshi Ishii , Naoto Saitoh
IPC分类号： H01L29/76
CPC分类号： H01L29/7816 , H01L29/0878 , H01L29/1083 , H01L29/1095 , H01L29/42368 , H01L29/7833 , H01L29/7835
摘要： An N-channel MOS transistor of a semiconductor device having a high withstand voltage employs a drain structure with a low concentration and a large diffusion depth, which causes a problem in that a sufficiently high withstand voltage cannot be obtained due to a parasitic NPN transistor formed among the drain, the well, and the semiconductor substrate which are arranged in the stated order. According to the present invention, provided are a semiconductor device, including: a semiconductor substrate; an epitaxial layer having an electric polarity identical with that of the semiconductor substrate, which is formed on the semiconductor substrate; a buried diffusion layer having the electric polarity different from that of the semiconductor substrate, which is formed between the semiconductor substrate and the epitaxial layer; and a well region having the electric polarity identical with that of the buried diffusion layer, which is formed above the buried diffusion layer and is electrically connected therewith, in which a MOS transistor is formed in a well having a structure in which the buried diffusion layer is electrically connected with the well region, and a manufacturing method therefor.
摘要翻译：具有高耐受电压的半导体器件的N沟道MOS晶体管采用具有低浓度和大扩散深度的漏极结构，这导致由于形成的寄生NPN晶体管而不能获得足够高的耐受电压的问题在排列，阱和半导体衬底之中，以所述顺序排列。根据本发明，提供一种半导体器件，包括：半导体衬底; 具有与半导体衬底的电极性相同的电极的外延层，其形成在半导体衬底上; 形成在半导体衬底和外延层之间的具有与半导体衬底的电极性不同的电极的掩埋扩散层; 以及具有与掩埋扩散层的电极性相同的电极性的阱区，其形成在掩埋扩散层的上方并与其电连接，其中MOS晶体管形成在具有埋入扩散层的结构的阱中，与该阱区电连接，及其制造方法。

4. 发明授权

US06492692B1 Semiconductor integrated circuit and manufacturing method therefore 有权
标题翻译：因此，半导体集成电路和制造方法
公开(公告)号：US06492692B1
公开(公告)日：2002-12-10
申请号：US09407382
申请日：1999-09-28
申请人： Kazutoshi Ishii , Naoto Inoue , Koushi Maemura , Shoji Nakanishi , Yoshikazu Kojima , Kiyoaki Kadoi , Takao Akiba , Yasuhiro Moya , Kentaro Kuhara
发明人： Kazutoshi Ishii , Naoto Inoue , Koushi Maemura , Shoji Nakanishi , Yoshikazu Kojima , Kiyoaki Kadoi , Takao Akiba , Yasuhiro Moya , Kentaro Kuhara
IPC分类号： H01L2972
CPC分类号： H01L24/05 , H01L21/78 , H01L23/53228 , H01L23/53238 , H01L24/03 , H01L24/13 , H01L24/16 , H01L24/48 , H01L2224/02126 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05012 , H01L2224/05017 , H01L2224/05022 , H01L2224/05073 , H01L2224/05166 , H01L2224/05552 , H01L2224/05556 , H01L2224/05557 , H01L2224/05558 , H01L2224/05572 , H01L2224/05599 , H01L2224/05624 , H01L2224/06051 , H01L2224/13017 , H01L2224/13027 , H01L2224/13099 , H01L2224/13144 , H01L2224/4807 , H01L2224/48453 , H01L2224/48463 , H01L2224/75252 , H01L2224/85201 , H01L2224/85399 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01029 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/05042 , H01L2924/10253 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/3025 , H01L2224/45099 , H01L2924/00 , H01L2924/00012
摘要： To decrease the area of a chip, improve the manufacturing efficiency and decrease the cost in a semiconductor device such as a driver integrated circuit having a number of output pads, and an electronic circuit device such as electronic clock. There are disposed output pads superposed in two dimensions on driving transistors or logic circuits connected thereto, respectively. Further, not only aluminum interconnection but also bump electrodes or barrier metals are used for the interconnection of the semiconductor device. In a case where a semiconductor integrated circuit is electrically adhered on to a printed circuit board in a face down manner, a solder bump disposed on the semiconductor integrated circuit and the interconnection of the printed circuit board are directly connected to each other, thereby realizing the electrical connection. On this occasion, the bump electrode as the external connecting terminal of the semiconductor integrated circuit is laminated on the transistor.
摘要翻译：为了减小芯片的面积，提高制造效率，降低诸如具有多个输出焊盘的驱动器集成电路等半导体装置以及诸如电子时钟之类的电子电路装置的成本。在驱动晶体管或连接到其的逻辑电路上分别布置有两个重叠的输出焊盘。此外，不仅铝互连而且凸起电极或阻挡金属用于半导体器件的互连。在半导体集成电路以面朝下的方式电粘接到印刷电路板的情况下，设置在半导体集成电路上的焊料凸块和印刷电路板的互连直接连接，从而实现电气连接。在这种情况下，作为半导体集成电路的外部连接端子的突起电极层叠在晶体管上。

5. 发明授权

US6134136A Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US6134136A
公开(公告)日：2000-10-17
申请号：US236896
申请日：1999-01-26
申请人： Kazutoshi Ishii , Sumitaka Gotou , Yasuhiro Moya , Yoshihide Kanakubo , Tatuya Kitta
发明人： Kazutoshi Ishii , Sumitaka Gotou , Yasuhiro Moya , Yoshihide Kanakubo , Tatuya Kitta
IPC分类号： B41J2/345 , G11C5/00 , H01L21/822 , H01L27/04 , G11C5/02
CPC分类号： G09G3/3685 , B41J2/3359 , G09G2330/04 , H01L2924/0002
摘要： Reducing the chip area while improving the manufacturing efficiency as well as reducing costs in a semiconductor integrated circuit device such as a thermal head driver IC. A plurality of terminal electrodes were provided within an external data input/output circuit with an input terminal and output terminal being electrically connected to each other. In addition, an input/output protection circuit was provided to a respective one of such plurality of terminal electrodes with the input terminal and output terminal electrically connected together.
摘要翻译：在提高制造效率的同时降低芯片面积并降低诸如热敏头驱动器IC的半导体集成电路器件的成本。多个端子电极设置在外部数据输入/输出电路内，输入端子和输出端子彼此电连接。此外，输入/输出保护电路被提供给这些多个端子电极中的相应一个，输入端子和输出端子电连接在一起。

6. 发明申请

US20050124083A1 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20050124083A1
公开(公告)日：2005-06-09
申请号：US10936738
申请日：2004-09-08
申请人： Kazutoshi Ishii , Jun Osanai , Yuichiro Kitajima , Yukimasa Minami , Keisuke Uemura , Miwa Wake
发明人： Kazutoshi Ishii , Jun Osanai , Yuichiro Kitajima , Yukimasa Minami , Keisuke Uemura , Miwa Wake
IPC分类号： H01L21/66 , G01R31/26 , H01L21/00 , H01L21/02 , H01L21/82 , H01L21/8234 , H01L21/8238 , H01L27/06 , H01L27/088 , H01L27/092 , H01L29/78
CPC分类号： H01L22/14 , G01R31/2644 , H01L22/20
摘要： A manufacturing method for a semiconductor device which is capable of manufacturing the semiconductor device with a high quality in high yields while reducing variations in electric characteristic is disclosed. The manufacturing method according to the present invention includes a main body wafer manufacturing process for manufacturing a wafer on which a semiconductor device to be completed as a product is formed and a monitor wafer manufacturing process for manufacturing a wafer on which a monitor element is formed, the processes sharing a monitoring step alone, the main body wafer manufacturing process including a variation reduction step, the monitor wafer manufacturing process including a quality check step and a condition setting step.
摘要翻译：公开了一种半导体器件的制造方法，该半导体器件能够以降低电特性的变化的方式高产量地制造高质量的半导体器件。根据本发明的制造方法包括用于制造其上形成作为产品而要完成的半导体器件的晶片的主体晶片制造工艺和用于制造其上形成有监视元件的晶片的监视晶片制造工艺，所述处理单独共享监视步骤，所述主体晶片制造工艺包括变化减小步骤，所述监视晶片制造过程包括质量检查步骤和条件设置步骤。

7. 发明授权

US5663589A Current regulating semiconductor integrated circuit device and fabrication method of the same 失效
标题翻译：电流调节半导体集成电路器件及其制造方法
公开(公告)号：US5663589A
公开(公告)日：1997-09-02
申请号：US314140
申请日：1994-09-28
申请人： Yutaka Saitoh , Jun Osanai , Yoshikazu Kojima , Kazutoshi Ishii
发明人： Yutaka Saitoh , Jun Osanai , Yoshikazu Kojima , Kazutoshi Ishii
IPC分类号： H01L21/8234 , H01L27/08 , H01L27/088 , H01L29/76 , H01L21/04
CPC分类号： H01L27/0814 , Y10S257/907 , Y10S257/91
摘要： A semiconductor integrated device having a current regulating diode may be substantially reduced in size and improved in performance by forming the current regulating diode of a plurality of MOS transistors each having a gate, a drain region, and a source region formed in a semiconductor substrate, the source regions and the substrate regions being electrically coupled to each other, the drain regions of at least two of the MOS transistors being electrically coupled, and the source regions of each of the MOS transistors being electrically coupled, the coupled drain regions, the coupled source regions, and the coupled gates forming a drain terminal, a source terminal and a gate terminal, respectively. In order to set a desired regulated current, selected coupling lines in the current regulating diode may be cut. This may be accomplished, for example, by measuring a first current which flows in the drain terminal while applying a first voltage to the gate terminal and a second voltage to the drain terminal relative to an electric potential of the source terminal, then measuring a second current which flows in the drain terminal while applying a third voltage to the gate terminal and the second voltage to the drain terminal relative to an electric potential of the source terminal. In order to achieve the desired current characteristic, selected conductive lines between coupled drains or between coupled sources are then cut.
摘要翻译：具有电流调节二极管的半导体集成器件可以通过形成多个MOS晶体管的电流调节二极管来大大减小尺寸并提高其性能，每个MOS晶体管具有形成在半导体衬底中的栅极，漏极区域和源极区域，源极区域和衬底区域彼此电耦合，至少两个MOS晶体管的漏极区域电耦合，并且每个MOS晶体管的源极区域电耦合，耦合的漏极区域，耦合的源极区域和耦合栅极分别形成漏极端子，源极端子和栅极端子。为了设定期望的调节电流，可以切断电流调节二极管中的选择的耦合线。这可以例如通过测量在漏极端子中流动的第一电流，同时向栅极端子施加第一电压，并且相对于源极端子的电位向漏极端子施加第二电压，然后测量第二电压相对于源极端子的电位向漏极端子施加第三电压而向漏极端子施加第三电压而流过漏极端子的电流。为了实现期望的电流特性，然后切割耦合的漏极之间或耦合的源之间的选定的导线。

8. 发明授权

US5449637A Method of producing low and high voltage MOSFETs with reduced masking steps 失效
标题翻译：降低屏蔽步骤生产低压和高压MOSFET的方法
公开(公告)号：US5449637A
公开(公告)日：1995-09-12
申请号：US128059
申请日：1993-09-27
申请人： Yutaka Saito , Yoshikazu Kojima , Kazutoshi Ishii
发明人： Yutaka Saito , Yoshikazu Kojima , Kazutoshi Ishii
IPC分类号： H01L21/265 , H01L21/266 , H01L21/8238 , H01L27/092
CPC分类号： H01L21/8238
摘要： An electroconductive or insulative film 100 is formed over a surface of a semiconductor substrate 1. A first photoresist 101 is coated over the film 100, and is then patterned. The film 100 is selectively removed by etching to expose a given area of the substrate 1. Subsequently an impurity of the first conductivity type is doped into the exposed area to form a first impurity region. After removing the first photoresist 101, a second photoresist 103 is coated entirely over the film 100, and is then patterned. Subsequently, the film 100 is selectively removed from another given area by etching. Another impurity of the second conductivity type is doped into the exposed area to form a second impurity region 104. Only the two steps of the photoresist patterning are carried out to form the impurity regions of the different conductivity types, thereby reducing production cost of the semiconductor device. The impurity can be doped by ion implantation while covering the film 100 with the photoresist, thereby facilitating micronization and integration of the semiconductor device.
摘要翻译：在半导体衬底1的表面上形成导电或绝缘膜100.第一光致抗蚀剂101涂覆在膜100上，然后被图案化。通过蚀刻选择性地去除膜100以暴露衬底1的给定区域。随后将第一导电类型的杂质掺杂到暴露区域中以形成第一杂质区域。在去除第一光致抗蚀剂101之后，将第二光致抗蚀剂103整个涂覆在膜100上，然后被图案化。随后，通过蚀刻从另一给定区域选择性地去除膜100。第二导电类型的另一杂质被掺杂到暴露区域中以形成第二杂质区域104.只进行光致抗蚀剂图案化的两个步骤以形成不同导电类型的杂质区域，从而降低半导体的制造成本设备。可以通过离子注入来掺杂杂质，同时用光致抗蚀剂覆盖膜100，从而有助于半导体器件的微粉化和集成。

9. 发明授权

US07335518B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07335518B2
公开(公告)日：2008-02-26
申请号：US10935974
申请日：2004-09-08
申请人： Kazutoshi Ishii , Jun Osanai , Yuichiro Kitajima , Yukimasa Minami , Keisuke Uemura , Miwa Wake
发明人： Kazutoshi Ishii , Jun Osanai , Yuichiro Kitajima , Yukimasa Minami , Keisuke Uemura , Miwa Wake
IPC分类号： H01L21/00
CPC分类号： H01L22/20 , H01L21/823857
摘要： In a manufacturing method for a semiconductor device, a main body wafer is formed, and a monitor wafer on which a monitor element is formed is provided. Characteristics of the main body wafer are copied onto the monitor element by simultaneously processing the main body wafer and the monitor wafer. The characteristic of the monitor element is measured by checking a process influence of the monitor element. Manufacturing conditions are set in accordance with the process influence of the monitor element. Variations in electric characteristics of the main body wafer are reduced in accordance with the set manufacturing conditions.
摘要翻译：在半导体器件的制造方法中，形成主体晶片，并且设置有形成有监视元件的监视晶片。通过同时处理主体晶片和监视晶片，将主体晶片的特性复制到监视器元件上。通过检查监视器元件的过程影响来测量监视元件的特性。制造条件根据监控元件的过程影响设定。根据设定的制造条件，能够减小主体晶片的电特性的变化。

10. 发明申请

US20050124082A1 Method for manufacturing semiconductor device 有权
公开(公告)号：US20050124082A1
公开(公告)日：2005-06-09
申请号：US10936736
申请日：2004-09-08
申请人： Kazutoshi Ishii , Jun Osanai , Yuichiro Kitajima , Yukimasa Minami , Keisuke Uemura , Miwa Wake
发明人： Kazutoshi Ishii , Jun Osanai , Yuichiro Kitajima , Yukimasa Minami , Keisuke Uemura , Miwa Wake
IPC分类号： H01L21/66 , G01R31/26 , H01L21/00 , H01L21/02 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/78
CPC分类号： H01L22/12 , H01L22/14 , H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： A manufacturing method for a semiconductor device which is capable of manufacturing the semiconductor device with a high quality in high yields while reducing variations in electric characteristic is disclosed. The manufacturing method according to the present invention includes a main body wafer manufacturing process for manufacturing a wafer on which a semiconductor device to be completed as a product is formed and a monitor wafer manufacturing process for manufacturing a wafer on which a monitor element is formed, the processes sharing a monitoring step alone, the main body wafer manufacturing process including a variation reduction step, the monitor wafer manufacturing process including a quality check step and a condition setting step.

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