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1. 发明授权

US06753568B1 Memory device 失效
标题翻译：内存设备
公开(公告)号：US06753568B1
公开(公告)日：2004-06-22
申请号：US09362200
申请日：1999-07-28
申请人： Kazuo Nakazato , Kiyoo Itoh , Hiroshi Mizuta , Toshihiko Sato , Toshikazu Shimada , Haroon Ahmed
发明人： Kazuo Nakazato , Kiyoo Itoh , Hiroshi Mizuta , Toshihiko Sato , Toshikazu Shimada , Haroon Ahmed
IPC分类号： H01L2976
CPC分类号： H01L21/28185 , B82Y10/00 , G11C13/0014 , G11C13/02 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/772 , H01L29/78642 , H01L29/7883 , H01L29/7888
摘要： A memory device includes a memory node (1) to which charge is written through a tunnel barrier configuration (2) from a control electrode (9). The stored charge effects the conductivity of a source/drain path (4) and data is read by monitoring the conductivity of the path. The charge barrier configuration comprises a multiple tunnel barrier configuration, which may comprise alternating layers (16) of polysilicon of 3 nm thickness and layers (15) of Si3N4 of 1 nm thickness, overlying polycrystalline layer of silicon (1) which forms the memory node. Alternative barrier configurations (2) are described, including a Schottky barrier configuration, and conductive nanometer scale conductive islands (30, 36, 44), which act as the memory node, distributed in an electrically insulating matrix.
摘要翻译：存储器件包括从控制电极（9）通过隧道势垒配置（2）写入电荷的存储器节点（1）。存储的电荷影响源/漏路径（4）的电导率，并且通过监测路径的电导率来读取数据。电荷势垒配置包括多隧道势垒结构，其可以包括3nm厚度的多晶硅的交替层（16）和1nm厚度的Si 3 N 4层（15），覆盖形成存储器节点的硅的多晶层（1）。描述了包括肖特基势垒结构的替代屏障配置（2）和用作存储节点的导电纳米级导电岛（30,36,44），其分布在电绝缘矩阵中。

2. 发明授权

US5952692A Memory device with improved charge storage barrier structure 失效
标题翻译：具有改善电荷存储屏障结构的存储器件
公开(公告)号：US5952692A
公开(公告)日：1999-09-14
申请号：US958845
申请日：1997-10-28
申请人： Kazuo Nakazato , Kiyoo Itoh , Hiroshi Mizuta , Toshihiko Sato , Toshikazu Shimada , Haroon Ahmed
发明人： Kazuo Nakazato , Kiyoo Itoh , Hiroshi Mizuta , Toshihiko Sato , Toshikazu Shimada , Haroon Ahmed
IPC分类号： H01L29/78 , G11C13/02 , G11C16/02 , H01L21/28 , H01L29/06 , H01L29/51 , H01L29/772 , H01L29/786 , H01L29/788
CPC分类号： H01L21/28185 , B82Y10/00 , G11C13/0014 , G11C13/02 , H01L21/28194 , H01L21/28229 , H01L29/511 , H01L29/517 , H01L29/772 , H01L29/78642 , H01L29/7888 , H01L21/28211
摘要： A memory device includes a memory node (1) to which charge is written through a tunnel barrier configuration (2) from a control electrode (9). The stored charge effects the conductivity of a source/drain path (4) and data is read by monitoring the conductivity of the path. The charge barrier configuration comprises a multiple tunnel barrier configuration, which may comprise alternating layers (16) of polysilicon of 3 nm thickness and layers (15) of Si.sub.3 N.sub.4 of 1 nm thickness, overlying polycrystalline layer of silicon (1) which forms the memory node. Alternative barrier configurations (2) are described, including a Schottky barrier configuration, and conductive nanometre scale conductive islands (30, 36, 44), which act as the memory node, distributed in an electrically insulating matrix.
摘要翻译：存储器件包括从控制电极（9）通过隧道势垒配置（2）写入电荷的存储器节点（1）。存储的电荷影响源/漏路径（4）的电导率，并且通过监测路径的电导率来读取数据。电荷势垒配置包括多隧道势垒结构，其可以包括3nm厚度的多晶硅的交替层（16）和1nm厚度的Si 3 N 4层（15），覆盖形成存储器节点的硅的多晶层（1）。描述了包括肖特基势垒结构的替代屏障配置（2）和用作存储节点的导电纳米级导电岛（30,36,44），其分布在电绝缘矩阵中。

3. 发明授权

US07132713B2 Controllable conduction device with electrostatic barrier 失效
标题翻译：带静电屏障的可控制传导装置
公开(公告)号：US07132713B2
公开(公告)日：2006-11-07
申请号：US10121596
申请日：2002-04-15
申请人： Kazuo Nakazato , Kiyoo Itoh , Hiroshi Mizuta , Toshikazu Shimada , Hideo Sunami , Tatsuya Teshima , Toshiyuki Mine , Ken Yamaguchi
发明人： Kazuo Nakazato , Kiyoo Itoh , Hiroshi Mizuta , Toshikazu Shimada , Hideo Sunami , Tatsuya Teshima , Toshiyuki Mine , Ken Yamaguchi
IPC分类号： H01L29/76 , H01L31/109
CPC分类号： H01L27/10858 , B82Y10/00 , G11C11/16 , H01L21/28273 , H01L27/10808 , H01L27/1082 , H01L27/10873 , H01L27/10876 , H01L27/11 , H01L29/154 , H01L29/42324 , H01L29/66825 , H01L29/772 , H01L29/78609 , H01L29/78618 , H01L29/78642 , H01L29/78687 , H01L29/7881 , H01L29/882
摘要： A controllable conduction device in the form of a transistor comprises source and drain regions 5, 2 between which extends a conduction path P for charge carriers, a gate 4 for controlling charge carrier flow along the conduction path and a multiple layer structure 3 providing a multiple tunnel junction configuration in the conduction path, with the result that current leakage is blocked by the multiple tunnel junction configuration when the transistor is in its off state. Vertical and lateral transistor configurations are described, together with use of the transistor in complimentary pairs and for a random access memory cell. Improved gate structures are described which are also applicable to memory devices that incorporate the tunnel barrier configuration to store charge on the memory node.
摘要翻译：晶体管形式的可控导电器件包括源极和漏极区域5，其间延伸用于电荷载流子的导电路径P，用于控制沿导电路径的电荷载流子的栅极4和提供多个导通路径中的隧道结结构，结果当晶体管处于其截止状态时，漏电流被多重隧道结构造阻塞。描述了垂直和横向晶体管配置，以及使用晶体管的互补对和随机存取存储器单元。描述了改进的栅极结构，其也适用于结合隧道势垒配置以在存储器节点上存储电荷的存储器件。

4. 发明授权

US6060723A Controllable conduction device 失效
公开(公告)号：US6060723A
公开(公告)日：2000-05-09
申请号：US95058
申请日：1998-06-10
申请人： Kazuo Nakazato , Kiyoo Itoh , Hiroshi Mizuta , Toshikazu Shimada , Hideo Sunami , Tatsuya Teshima , Toshiyuki Mine , Ken Yamaguchi
发明人： Kazuo Nakazato , Kiyoo Itoh , Hiroshi Mizuta , Toshikazu Shimada , Hideo Sunami , Tatsuya Teshima , Toshiyuki Mine , Ken Yamaguchi
IPC分类号： G11C11/16 , H01L21/28 , H01L21/336 , H01L21/8242 , H01L21/8244 , H01L27/108 , H01L27/11 , H01L29/15 , H01L29/423 , H01L29/772 , H01L29/786 , H01L29/788 , H01L29/88 , H01L29/06 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109
CPC分类号： H01L27/10858 , B82Y10/00 , G11C11/16 , H01L21/28273 , H01L27/10808 , H01L27/1082 , H01L27/10873 , H01L27/10876 , H01L27/11 , H01L29/154 , H01L29/42324 , H01L29/66825 , H01L29/772 , H01L29/78609 , H01L29/78618 , H01L29/78642 , H01L29/78687 , H01L29/7881 , H01L29/882
摘要： A controllable conduction device in the form of a transistor comprises source and drain regions 5, 2 between which extends a conduction path P for charge carriers, a gate 4 for controlling charge carrier flow along the conduction path and a multiple layer structure 3 providing a multiple tunnel junction configuration in the conduction path, with the result that current leakage is blocked by the multiple tunnel junction configuration when the transistor is in its off state. Vertical and lateral transistor configurations are described, together with use of the transistor in complimentary pairs and for a random access memory cell. Improved gate structures are described which are also applicable to memory devices that incorporate the tunnel barrier configuration to store charge on the memory node.

5. 发明授权

US06169308A Semiconductor memory device and manufacturing method thereof 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US06169308A
公开(公告)日：2001-01-02
申请号：US09166858
申请日：1998-10-06
申请人： Hideo Sunami , Kiyoo Itoh , Toshikazu Shimada , Kazuo Nakazato , Hiroshi Mizuta
发明人： Hideo Sunami , Kiyoo Itoh , Toshikazu Shimada , Kazuo Nakazato , Hiroshi Mizuta
IPC分类号： H01L2972
CPC分类号： B82Y10/00 , G11C16/02 , H01L27/108 , H01L27/1082 , H01L27/10858 , H01L27/10873 , H01L27/10876 , H01L27/11 , H01L29/154 , H01L29/42324 , H01L29/511 , H01L29/772 , H01L29/78618 , H01L29/78642 , H01L29/78687 , H01L29/7881 , H01L29/7883 , H01L29/7888
摘要： A high speed/large capacity DRAM (Dynamic Random Access Memory) is generally refreshed each 0.1 sec because it loses information stored therein due to a leakage current. The DRAM also loses information stored therein upon cutoff of a power source. Meanwhile, a nonvolatile ROM (Read-only Memory) cannot be configured as a high speed/large capacity memory. A semiconductor memory device of the present invention realizes nonvolatile characteristic by shielding a drain functioning as a memory node from a leakage current by a tunnel insulator, and also realizes stable and high speed operation by adding a transistor for reading to a memory cell.
摘要翻译：通常由于漏电流而丢失存储在其中的信息，所以每0.1秒钟通常刷新高速/大容量DRAM（动态随机存取存储器）。在断电时，DRAM也会丢失存储在其中的信息。同时，非易失性ROM（只读存储器）不能被配置为高速/大容量存储器。本发明的半导体存储器件通过屏蔽用作存储器节点的漏极与隧道的泄漏电流来实现非易失性特性绝缘体，并且通过将用于读取的晶体管添加到存储单元来实现稳定和高速操作。

6. 发明授权

US06211531B1 Controllable conduction device 失效
标题翻译：可控导通装置
公开(公告)号：US06211531B1
公开(公告)日：2001-04-03
申请号：US09492171
申请日：2000-01-27
申请人： Kazuo Nakazato , Kiyoo Itoh , Hiroshi Mizuta , Toshikazu Shimada , Hideo Sunami , Tatsuya Teshima , Toshiyuki Mine , Ken Yamaguchi
发明人： Kazuo Nakazato , Kiyoo Itoh , Hiroshi Mizuta , Toshikazu Shimada , Hideo Sunami , Tatsuya Teshima , Toshiyuki Mine , Ken Yamaguchi
IPC分类号： H01L2906
CPC分类号： H01L27/10858 , B82Y10/00 , G11C11/16 , H01L21/28273 , H01L27/10808 , H01L27/1082 , H01L27/10873 , H01L27/10876 , H01L27/11 , H01L29/154 , H01L29/42324 , H01L29/66825 , H01L29/772 , H01L29/78609 , H01L29/78618 , H01L29/78642 , H01L29/78687 , H01L29/7881 , H01L29/882
摘要： A controllable conduction device in the form of a transistor comprises source and drain regions 5, 2 between which extends a conduction path P for charge carriers, a gate 4 for controlling charge carrier flow along the conduction path and a multiple layer structure 3 providing a multiple tunnel junction configuration in the conduction path, with the result that current leakage is blocked by the multiple tunnel junction configuration when the transistor is in its off state. Vertical and lateral transistor configurations are described, together with use of the transistor in complimentary pairs and for a random access memory cell. Improved gate structures are described which are also applicable to memory devices that incorporate the tunnel barrier configuration to store charge on the memory node.
摘要翻译：晶体管形式的可控导电器件包括源极和漏极区域5，其间延伸用于电荷载流子的导电路径P，用于控制沿导电路径的电荷载流子的栅极4和提供多个导通路径中的隧道结结构，结果当晶体管处于其截止状态时，漏电流被多重隧道结构造阻塞。描述了垂直和横向晶体管配置，以及使用晶体管的互补对和随机存取存储器单元。描述了改进的栅极结构，其也适用于结合隧道势垒配置以在存储器节点上存储电荷的存储器件。

7. 发明授权

US06825527B2 Semiconductor memory device and manufacturing method 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US06825527B2
公开(公告)日：2004-11-30
申请号：US10454527
申请日：2003-06-05
申请人： Hideo Sunami , Kiyoo Itoh , Toshikazu Shimada , Kazuo Nakazato , Hiroshi Mizuta
发明人： Hideo Sunami , Kiyoo Itoh , Toshikazu Shimada , Kazuo Nakazato , Hiroshi Mizuta
IPC分类号： H01L2972
CPC分类号： B82Y10/00 , G11C16/02 , H01L27/108 , H01L29/511 , H01L29/772 , H01L29/785 , H01L29/78642 , H01L29/7883 , H01L29/7888
摘要： A high speed/large capacity DRAM (Dynamic Random Access Memory) is generally refreshed each 0.1 sec because it loses information stored therein due to a leakage current. The DRAM also loses information stored therein upon cutoff of a power source. Meanwhile, a nonvolatile ROM (Read-only Memory) cannot be configured as a high speed/large capacity memory. A semiconductor memory device of the present invention realizes nonvolatile characteristic by shielding a drain functioning as a memory node from a leakage current by a tunnel insulator, and also realizes stable and high speed operation by adding a transistor for reading to a memory cell.
摘要翻译：通常由于漏电流而丢失存储在其中的信息，所以每0.1秒钟通常刷新高速/大容量DRAM（动态随机存取存储器）。在断电时，DRAM也会丢失存储在其中的信息。同时，非易失性ROM（只读存储器）不能被配置为高速/大容量存储器。本发明的半导体存储器件通过屏蔽用作存储器节点的漏极与隧道的泄漏电流来实现非易失性特性绝缘体，并且通过将用于读取的晶体管添加到存储单元来实现稳定和高速操作。

8. 发明授权

US06642574B2 Semiconductor memory device and manufacturing method thereof 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US06642574B2
公开(公告)日：2003-11-04
申请号：US09727497
申请日：2000-12-04
申请人： Hideo Sunami , Kiyoo Itoh , Toshikazu Shimada , Kazuo Nakazato , Hiroshi Mizuta
发明人： Hideo Sunami , Kiyoo Itoh , Toshikazu Shimada , Kazuo Nakazato , Hiroshi Mizuta
IPC分类号： H01L2972
CPC分类号： B82Y10/00 , G11C16/02 , H01L27/108 , H01L29/511 , H01L29/772 , H01L29/785 , H01L29/78642 , H01L29/7883 , H01L29/7888
摘要： A high speed/large capacity DRAM (Dynamic Random Access Memory) is generally refreshed each 0.1 sec because it loses information stored therein due to a leakage current. The DRAM also loses information stored therein upon cutoff of a power source. Meanwhile, a nonvolatile ROM (Read-only Memory) cannot be configured as a high speed/large capacity memory. A semiconductor memory device of the present invention realizes nonvolatile characteristic by shielding a drain functioning as a memory node from a leakage current by a tunnel insulator, and also realizes stable and high speed operation by adding a transistor for reading to a memory cell.
摘要翻译：通常由于漏电流而丢失存储在其中的信息，所以每0.1秒钟通常刷新高速/大容量DRAM（动态随机存取存储器）。在断电时，DRAM也会丢失存储在其中的信息。同时，非易失性ROM（只读存储器）不能被配置为高速/大容量存储器。本发明的半导体存储器件通过屏蔽用作存储器节点的漏极与隧道的泄漏电流来实现非易失性特性绝缘体，并且通过将用于读取的晶体管添加到存储单元来实现稳定和高速操作。

9. 发明授权

US5677637A Logic device using single electron coulomb blockade techniques 失效
标题翻译：使用单电子库仑封锁技术的逻辑器件
公开(公告)号：US5677637A
公开(公告)日：1997-10-14
申请号：US606835
申请日：1996-02-27
申请人： Kazuo Nakazato , Haroon Ahmed , Julian D. White
发明人： Kazuo Nakazato , Haroon Ahmed , Julian D. White
IPC分类号： G01R29/12 , G11C11/404 , G11C11/4091 , G11C11/56 , G11C19/18 , H03K19/08 , H03K19/23 , H03K19/00
CPC分类号： B82Y10/00 , G11C11/404 , G11C11/4091 , G11C11/56 , G11C19/182 , H03K19/08 , G01R29/12 , G11C2216/08 , Y10S977/937
摘要： A memory device includes a memory node (2) to which is connected a tunnel barrier configuration such that the node exhibits first and second quantized memory states for which the level of stored charge is limited by Coulomb Blockade and a surplus or shortfall of a small number of electrons for example ten electrons or even a single electron can be used to represent quantized memory states. A series of the nodes N0-N3 that are interconnected by tunnel barriers D can be arranged as a logic device. Clock waveforms V1-V3 applied to clock lines C1 1-C1 3 selectively alter the probability of charge carriers passing through the tunnel diodes D from node to node. An output device, typically a Coulomb blockade electrometer provides an output logical signal indicative of the logical state of node N3. Arrays of separately addressable memory cells M.sub.mn are also described, that utilize gated multiple tunnel junctions (MTJs) as their barrier configurations. Side gated GaAs MTJ structures formed by selective etching and lithography are described. Also, gate structures which modulate a conductive channel with depletion regions to form multiple tunnel junctions are disclosed.
摘要翻译：存储器装置包括存储器节点（2），其连接有隧道势垒配置，使得节点具有第一和第二量化的存储器状态，存储电荷的级别由库仑阻塞限制，少量或少量的少量的电子，例如十个电子或甚至单个电子可以用于表示量化的记忆状态。通过隧道屏障D互连的一系列节点N0-N3可以被布置为逻辑设备。施加到时钟线C1 1 -C1 3的时钟波形V1-V3选择性地改变从节点到节点通过隧道二极管D的电荷载流子的概率。输出装置（通常是库仑阻塞静电计）提供指示节点N3的逻辑状态的输出逻辑信号。还描述了单独可寻址存储器单元Mmn的阵列，其利用门控多隧道结（MTJ）作为其屏障配置。描述了通过选择性蚀刻和光刻形成的侧栅GaAs MTJ结构。此外，公开了用耗尽区调制导电沟道以形成多个隧道结的栅极结构。

10. 发明授权

US06762951B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US06762951B2
公开(公告)日：2004-07-13
申请号：US10330077
申请日：2002-12-30
申请人： Kiyoo Itoh , Kazuo Nakazato
发明人： Kiyoo Itoh , Kazuo Nakazato
IPC分类号： G11C1124
CPC分类号： G11C11/4076 , G11C11/404 , G11C11/405 , G11C16/0408 , G11C2207/2281 , G11C2207/229
摘要： A semiconductor integrated circuit device utilizing a memory cell containing a transistor to write information and a storage MOSFET to retain an information voltage in the gate, a word line placed to intersect with a write data line and a read data line, for connecting to the control terminal of the write transistor and a memory cell array for issuing an output on the read data line corresponding to the read signal from said memory cell in response to a select signal from said write transistor and by means of a data select circuit select one from among said plurality of read data lines from the data line select circuit and connect to either a first or second common data line, precharge said read data line to a first voltage within a first period, discharge said read data line to a second voltage by means of a second storage MOSFET of said memory cell set to on status for said word line selected within the second period, precharge said first and second common data lines to a third voltage between said first and said second voltages within said first period and, amplify the read signal appearing on either of the common data lines from the read data line selected by said data line select circuit within said second period by using the precharge voltage on said other common data line as a reference voltage.
摘要翻译：一种半导体集成电路器件，其利用包含晶体管来写入信息的存储单元和存储MOSFET来保持栅极中的信息电压，放置为与写入数据线和读取数据线相交的字线，用于连接到控制器写入晶体管的端子和用于响应于来自所述写入晶体管的选择信号而从所述存储单元发出对应于读取信号的所述读取数据线上的输出的存储单元阵列，并且借助于数据选择电路，从所述多条读取数据线从数据线选择电路连接到第一或第二公共数据线，在第一周期内将所述读取数据线预充电到第一电压，借助于所述存储器单元的第二存储MOSFET设置为在所述第二周期内选择的所述字线的状态，将所述第一和第二公共数据线预充电到第三伏特在所述第一周期内的所述第一和所述第二电压之间，并且在所述第二周期内通过使用所述另一个上的预充电电压来放大在所述第二周期内由所述数据线选择电路选择的读数据线上出现在任一公共数据线上的读信号公共数据线作为参考电压。

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