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1. 发明授权

US5400275A Semiconductor memory device using ferroelectric capacitor and having only one sense amplifier selected 失效
标题翻译：使用铁电电容器并且仅选择一个读出放大器的半导体存储器件
公开(公告)号：US5400275A
公开(公告)日：1995-03-21
申请号：US712092
申请日：1991-06-07
申请人： Kazuhide Abe , Hiroshi Toyoda , Koji Yamakawa , Motomasa Imai , Koji Sakui
发明人： Kazuhide Abe , Hiroshi Toyoda , Koji Yamakawa , Motomasa Imai , Koji Sakui
IPC分类号： G11C11/22 , H01L27/115 , G11C7/00
CPC分类号： H01L27/11502 , G11C11/22
摘要： A semiconductor memory device comprises a plurality of memory cells arranged in the form of a matrix to constitute rows-and columns, a plurality of first driving lines, connected to the memory cells, for transmitting a first driving signal to the memory cells, one of the plurality of first driving lines being selected by a row address, a plurality of second driving lines, connected to the memory cells, for transmitting a second driving signal to the memory cells, one of the plurality of second driving lines being selected by a column address, a plurality of read/write lines, connected to the memory cells, for performing read/write operations with respect to the memory cells, and a plurality of sense amplifiers connected to the read/ write lines, wherein one of the plurality of sense amplifiers is selected by the column address, and the memory cells in the same column are connected to the same sense amplifier through the read/write lines.
摘要翻译：一种半导体存储器件包括以矩阵形式布置以构成行和列的多个存储器单元，连接到存储器单元的多条第一驱动线，用于将第一驱动信号发送到存储器单元，其中之一所述多个第一驱动线由行地址选择，多个第二驱动线连接到所述存储单元，用于将第二驱动信号发送到所述存储单元，所述多个第二驱动线中的一个由列选择连接到存储器单元的多个读/写线，用于对存储单元执行读/写操作，以及连接到读/写线的多个读出放大器，其中多个感测中的一个放大器由列地址选择，同一列中的存储单元通过读/写线连接到相同的读出放大器。

2. 发明授权

US5155573A Ferroelectric capacitor and a semiconductor device having the same 失效
标题翻译：电解电容器和具有该电容器的半导体器件
公开(公告)号：US5155573A
公开(公告)日：1992-10-13
申请号：US633324
申请日：1990-12-24
申请人： Kazuhide Abe , Hiroshi Toyoda , Koji Yamakawa , Motomasa Imai , Mitsuo Harata , Koji Sakui
发明人： Kazuhide Abe , Hiroshi Toyoda , Koji Yamakawa , Motomasa Imai , Mitsuo Harata , Koji Sakui
IPC分类号： H01L21/02 , H01L21/8246 , H01L27/115 , H01L29/92
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/60
摘要： A ferroelectric capacitor includes a ferroelectric layer consisting of lead zirconate titanate formed on a silicon substrate, a plurality of rectangular trenches formed in the direction of thickness of the ferroelectric layer with a ferroelectric material therebetween, and first and second electrodes consisting of metal tungsten buried in the trenches to oppose each other with the ferroelectric material therebetween.
摘要翻译：铁电电容器包括由在硅衬底上形成的锆钛酸铅构成的铁电层，在其间具有铁电体的铁电层的厚度方向上形成的多个矩形沟槽，以及埋入金属钨的第一和第二电极沟槽之间用铁电材料彼此相对。

3. 发明授权

US5297077A Memory having ferroelectric capacitors polarized in nonvolatile mode 失效
标题翻译：具有以非易失性模式极化的铁电电容器的存储器
公开(公告)号：US5297077A
公开(公告)日：1994-03-22
申请号：US676546
申请日：1991-03-28
申请人： Motomasa Imai , Hiroshi Toyoda , Kazuhide Abe , Koji Yamakawa , Hisakazu Iizuka , Mitsuo Harata , Koji Sakui
发明人： Motomasa Imai , Hiroshi Toyoda , Kazuhide Abe , Koji Yamakawa , Hisakazu Iizuka , Mitsuo Harata , Koji Sakui
IPC分类号： G11C11/22 , G11C14/00
CPC分类号： G11C14/00 , G11C11/22
摘要： A semiconductor memory device comprises a ferroelectric capacitor, a voltage output circuit for outputting a first voltage for reversely polarizing the ferroelectric capacitor and a second voltage by which the polarization of the ferroelectric capacitor is not reversed, regardless of data stored in the ferroelectric capacitor, a first reference capacitor having a such a capacitance as to accumulate less charge than charge which the ferroelectric capacitor accumulates, when the second voltage is applied to the ferroelectric capacitor, a second reference capacitor having such a capacitance that as to accumulate greater charge than the charge which the ferroelectric capacitor accumulates while the ferroelectric capacitor is forwardly polarized, when the first voltage is applied to the ferroelectric capacitor, thus reversely polarizing the ferroelectric capacitor, a sense amplifier connected to the ferroelectric capacitor and the first or second reference capacitor, a reference-capacitor selecting circuit for connecting the first reference capacitor to the sense amplifier when the voltage output circuit outputs the second voltage, and connecting the second reference capacitor to the sense amplifier while the voltage output circuit outputs the first voltage, and a circuit for determining data from the presence or absence of an electric charge in the ferroelectric capacitors while the memory is set in volatile mode, and for determining data from the direction in which the ferroelectric capacitor is polarized, while the memory is set in nonvolatile mode.
摘要翻译：半导体存储器件包括铁电电容器，用于输出用于使强电介质电容器反向极化的第一电压的电压输出电路和强电介质电容器的极化不反转的第二电压，而与铁电电容器中存储的数据无关第一参考电容器具有这样的电容，即当第二电压被施加到铁电电容器时，积累比铁电电容器累积的电荷少的电荷，第二参考电容器具有这样的电容，以便积累比电荷更大的电荷当铁电电容器向前偏振时，铁电电容器累积，当第一电压施加到铁电电容器时，从而使铁电电容器反向极化，连接到铁电电容器和第一或第二参考电容器的读出放大器，参考电容器 s 选择电路，用于当电压输出电路输出第二电压时将第一参考电容器连接到读出放大器，并且在电压输出电路输出第一电压时将第二参考电容器连接到读出放大器;以及电路，用于从当存储器被设置为易失性模式时，铁电电容器中存在或不存在电荷，并且用于从存储器设置为非易失性模式时从铁电电容器被极化的方向确定数据。

4. 发明授权

US08737131B2 Programming memory cells using smaller step voltages for higher program levels 有权
标题翻译：使用更小的步进电压编程存储器单元以实现更高的程序级
公开(公告)号：US08737131B2
公开(公告)日：2014-05-27
申请号：US13305795
申请日：2011-11-29
申请人： Koji Sakui
发明人： Koji Sakui
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3427
摘要： Memory devices and methods are disclosed. An embodiment of one such method includes programming a first memory cell to a first program level by applying a first series of programming pulses to a control gate of the first memory cell, where the programming pulses of the first series have voltages that sequentially increase by a certain first voltage; and programming a second memory cell to a second program level that is higher than the first program level by applying a second series of programming pulses to a control gate of the second memory cell, where the programming pulses of the second series have voltages that sequentially increase by a certain second voltage less than the certain first voltage.
摘要翻译：公开了存储器件和方法。一种这样的方法的实施例包括通过将第一系列编程脉冲施加到第一存储器单元的控制栅极来将第一存储器单元编程为第一程序级，其中第一系列的编程脉冲具有依次增加的电压一定的第一电压; 以及通过将第二系列编程脉冲施加到所述第二存储器单元的控制栅极来将第二存储器单元编程为高于所述第一编程电平的第二编程电平，其中所述第二系列的编程脉冲具有顺序增加的电压通过一定的第二电压小于一定的第一电压。

5. 发明申请

US20140036590A1 PARTIAL BLOCK MEMORY OPERATIONS 审中-公开
标题翻译：部分块存储器操作
公开(公告)号：US20140036590A1
公开(公告)日：2014-02-06
申请号：US13564458
申请日：2012-08-01
申请人： Peter Sean Feeley , Koji Sakui , Akira Goda
发明人： Peter Sean Feeley , Koji Sakui , Akira Goda
IPC分类号： G11C16/04
摘要： Methods and apparatuses are disclosed, such as those including a block of memory cells that includes strings of charge storage devices. Each of the strings may comprise a plurality of charge storage devices formed in a plurality of tiers. The apparatus may comprise a plurality of access lines shared by the strings. Each of the plurality of access lines may be coupled to the charge storage devices corresponding to a respective tier of the plurality of tiers. The apparatus may comprise a plurality of sub-sources associated with the strings. Each of the plurality of sub-sources may be coupled to a source select gate of each string of a respective subset of a plurality of subsets of the strings, and each sub-source may be independently selectable from other sub-sources to select the strings of its respective subset independently of other strings corresponding to other subsets.
摘要翻译：公开了诸如包括包含电荷存储装置串的存储器单元块的方法和装置。每个串可以包括以多层形成的多个电荷存储装置。该装置可以包括由串共享的多个接入线。多个接入线路中的每一个可以耦合到与多个层级的相应层对应的电荷存储装置。该装置可以包括与弦相关联的多个子源。多个子源中的每一个可以耦合到字符串的多个子集的相应子集的每个串的源选择门，并且每个子源可以独立地从其他子源中选择以选择字符串独立于对应于其他子集的其他字符串。

6. 发明申请

US20130336070A1 APPARATUSES AND METHODS TO MODIFY PILLAR POTENTIAL 有权
标题翻译：修改支柱潜力的装置和方法
公开(公告)号：US20130336070A1
公开(公告)日：2013-12-19
申请号：US13525035
申请日：2012-06-15
申请人： Koji Sakui , Peter Sean Feeley
发明人： Koji Sakui , Peter Sean Feeley
IPC分类号： G11C16/10 , H01L29/788
CPC分类号： G11C16/10 , G11C16/02 , G11C16/0466 , G11C16/0483
摘要： Apparatus are disclosed, such as a block including a number of strings of charge storage devices, each string including a number of charge storage devices associated with a pillar, and each pillar including semiconductor material. Methods are disclosed, such as a method that includes performing a first operation on a first charge storage device associated with a pillar in the block, modifying an electrical potential of the pillar, and performing a second operation on a second charge storage device in the block. Additional apparatus and methods are described.
摘要翻译：公开了诸如包括多个电荷存储装置串的块的每个串，包括与柱相关联的多个电荷存储装置，并且每个支柱包括半导体材料。公开了一种方法，例如包括在与块中的柱相关联的第一电荷存储装置上执行第一操作的方法，修改支柱的电位，以及对块中的第二电荷存储装置执行第二操作。描述附加的装置和方法。

7. 发明授权

US08537623B2 Devices and methods of programming memory cells 有权
标题翻译：编程存储单元的设备和方法
公开(公告)号：US08537623B2
公开(公告)日：2013-09-17
申请号：US13178217
申请日：2011-07-07
申请人： Koichi Kawai , Koji Sakui , Peter Feeley
发明人： Koichi Kawai , Koji Sakui , Peter Feeley
IPC分类号： G11C11/34
CPC分类号： G11C16/3404 , G11C11/5628 , G11C16/10 , G11C16/3427 , G11C16/3459
摘要： Devices and methods of programming memory cells, both SLC and MLC, such as to reduce charge-storage structure to charge-storage structure coupling, are shown and described. Programming of memory cells can include comparing a first page of data to a second page of data, and further programming cells corresponding to the first page of data that will not likely be affected by coupling from programming the second page of data.
摘要翻译：显示和描述了将存储器单元（SLC和MLC）编程的设备和方法，例如将电荷存储结构减少到电荷存储结构耦合。存储器单元的编程可以包括将数据的第一页与第二页数据进行比较，以及进一步对与第一页数据相对应的编程单元，该第一页数据不会受编程第二页数据的耦合的影响。

8. 发明申请

US20130135937A1 PROGRAMMING MEMORY CELLS USING SMALLER STEP VOLTAGES FOR HIGHER PROGRAM LEVELS 有权
标题翻译：使用较小程序级电压编程存储器电池
公开(公告)号：US20130135937A1
公开(公告)日：2013-05-30
申请号：US13305795
申请日：2011-11-29
申请人： Koji Sakui
发明人： Koji Sakui
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3427
摘要： Memory devices and methods are disclosed. An embodiment of one such method includes programming a first memory cell to a first program level by applying a first series of programming pulses to a control gate of the first memory cell, where the programming pulses of the first series have voltages that sequentially increase by a certain first voltage; and programming a second memory cell to a second program level that is higher than the first program level by applying a second series of programming pulses to a control gate of the second memory cell, where the programming pulses of the second series have voltages that sequentially increase by a certain second voltage less than the certain first voltage.
摘要翻译：公开了存储装置和方法。一种这样的方法的实施例包括通过将第一系列编程脉冲施加到第一存储器单元的控制栅极来将第一存储器单元编程为第一程序级，其中第一系列的编程脉冲具有依次增加的电压一定的第一电压; 以及通过将第二系列编程脉冲施加到所述第二存储器单元的控制栅极来将第二存储器单元编程为高于所述第一编程电平的第二编程电平，其中所述第二系列的编程脉冲具有顺序增加的电压通过一定的第二电压小于一定的第一电压。

9. 发明申请

US20080212373A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE WITH A STACKED GATE INCLUDING A FLOATING GATE AND A CONTROL GATE 失效
标题翻译：具有包括浮动门和控制门的堆叠门的半导体集成电路装置
公开(公告)号：US20080212373A1
公开(公告)日：2008-09-04
申请号：US12027744
申请日：2008-02-07
申请人： Takehiro HASEGAWA , Akira Umezawa , Koji Sakui , Fumitaka Arai , Ryo Mitani
发明人： Takehiro HASEGAWA , Akira Umezawa , Koji Sakui , Fumitaka Arai , Ryo Mitani
IPC分类号： G11C16/04 , H01L29/788
CPC分类号： H01L27/11524 , G11C11/005 , G11C16/0433 , G11C16/0483 , G11C16/08 , G11C16/20 , H01L27/105 , H01L27/115 , H01L27/11517 , H01L27/11521 , H01L27/11526 , H01L27/11546
摘要： A semiconductor integrated circuit device includes first and second nonvolatile semiconductor memories. The first memory has first and second select transistors and first memory cell transistors. The first memory cell transistor has a first floating gate on a first gate insulating film and a first control gate on a first inter-gate insulating film. The second memory has a third select transistor and a second memory cell transistor. The second memory cell transistor has a second floating gate on a second gate insulating film and a second control gate on a second inter-gate insulating film. The first and second gate insulating films have the same film thickness. The first and second floating gates have the same film thickness. The first and second inter-gate insulating films have the same film thickness. The first and second control gates have the same film thickness.
摘要翻译：半导体集成电路器件包括第一和第二非易失性半导体存储器。第一存储器具有第一和第二选择晶体管和第一存储单元晶体管。第一存储单元晶体管在第一栅极绝缘膜上具有第一浮置栅极，在第一栅极间绝缘膜上具有第一控制栅极。第二存储器具有第三选择晶体管和第二存储单元晶体管。第二存储单元晶体管在第二栅极绝缘膜上具有第二浮置栅极，在第二栅极绝缘膜上具有第二控制栅极。第一和第二栅极绝缘膜具有相同的膜厚度。第一和第二浮栅具有相同的膜厚度。第一和第二栅极间绝缘膜具有相同的膜厚度。第一和第二控制栅具有相同的膜厚度。

10. 发明申请

US20080192549A1 Nonvolatile Semiconductor Storage Device and Operation Method Thereof 有权
标题翻译：非易失性半导体存储器件及其操作方法
公开(公告)号：US20080192549A1
公开(公告)日：2008-08-14
申请号：US11815387
申请日：2006-02-03
申请人： Michio Nakagawa , Koji Sakui
发明人： Michio Nakagawa , Koji Sakui
IPC分类号： G11C16/12
CPC分类号： G11C16/12 , G11C16/3468
摘要： To provide a nonvolatile semiconductor storage device and a drive method thereof capable of preventing lowering efficiency of write or erase operation and reducing the write time and the erase time. [MEANS FOR SOLVING PROBLEMS] A nonvolatile semiconductor storage device includes an electrically rewritable memory cell formed by a floating gate and a control gate layered on a semiconductor layer. The nonvolatile semiconductor storage device applies a plurality of threshold value fluctuation pulses having a stepwise high potential to the memory cell and then detects a threshold value of the memory cell. When the threshold value of the memory cell is not a predetermined value, a plurality of threshold value fluctuation pulses having stepwise high potential are applied to the memory cell from a potential of the lastly applied threshold value fluctuation pulse, among the plurality of threshold value fluctuation pulses, to which a certain potential is added.
摘要翻译：提供一种能够防止写入或擦除操作的降低效率并减少写入时间和擦除时间的非易失性半导体存储器件及其驱动方法。解决问题的手段非易失性半导体存储装置包括由浮置栅极和层叠在半导体层上的控制栅极形成的电可重写存储单元。非易失性半导体存储装置向存储单元施加具有逐级高电位的多个阈值波动脉冲，然后检测存储单元的阈值。当存储单元的阈值不是预定值时，具有逐步高电位的多个阈值波动脉冲从最近施加的阈值波动脉冲的电位在多个阈值波动之中被施加到存储单元脉冲，添加一定的电位。

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