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1. 发明申请

US20070115018A1 STRUCTURE AND METHOD FOR MONITORING STRESS-INDUCED DEGRADATION OF CONDUCTIVE INTERCONNECTS 有权
标题翻译：用于监测导电互连的应力诱导降解的结构和方法
公开(公告)号：US20070115018A1
公开(公告)日：2007-05-24
申请号：US11163948
申请日：2005-11-04
申请人： Kaushik Chanda , Birendra Agarwala , Lawrence Clevenger , Andrew Cowley , Ronald Filippi , Jason Gill , Tom Lee , Baozhen Li , Paul McLaughlin , Du Nguyen , Hazara Rathore , Timothy Sullivan , Chih-Chao Yang
发明人： Kaushik Chanda , Birendra Agarwala , Lawrence Clevenger , Andrew Cowley , Ronald Filippi , Jason Gill , Tom Lee , Baozhen Li , Paul McLaughlin , Du Nguyen , Hazara Rathore , Timothy Sullivan , Chih-Chao Yang
IPC分类号： G01R31/26
CPC分类号： G01R31/2858 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A microelectronic element such as a chip or microelectronic wiring substrate is provided which includes a plurality of conductive interconnects for improved resistance to thermal stress. At least some of the conductive interconnects include a metallic plate, a metallic connecting line and an upper metallic via. The metallic connecting line has an upper surface at least substantially level with an upper surface of the metallic plate, an inner end connected to the metallic plate at one of the peripheral edges, and an outer end horizontally displaced from the one peripheral edge. The metallic connecting line has a width much smaller than the width of the one peripheral edge of the metallic plate and has length greater than the width of the one peripheral edge. The upper metallic via has a bottom end in contact with the metallic connecting line at a location that is horizontally displaced from the one peripheral edge by at least about 3 microns (μm).
摘要翻译：提供了诸如芯片或微电子布线基板的微电子元件，其包括用于改善耐热应力的多个导电互连。至少一些导电互连件包括金属板，金属连接线和上金属通孔。所述金属连接线具有与所述金属板的上表面至少基本平齐的上表面，在所述周边边缘中的一个处连接到所述金属板的内端和从所述一个周边边缘水平移位的外端。金属连接线的宽度远小于金属板的一个周边边缘的宽度，并且其长度大于一个周边边缘的宽度。上金属通孔在与一个外围边缘水平位移至少约3微米（mum）的位置处具有与金属连接线接触的底端。

2. 发明申请

US20080107149A1 Method for monitoring stress-induced degradation of conductive interconnects 失效
标题翻译：用于监测导电互连的应力诱导退化的方法
公开(公告)号：US20080107149A1
公开(公告)日：2008-05-08
申请号：US12004011
申请日：2007-12-19
申请人： Kaushik Chanda , Birendra Agarwala , Lawrence Clevenger , Andrew Cowley , Ronald Filippi , Jason Gill , Tom Lee , Baozhen Li , Paul McLaughlin , Du Nguyen , Hazara Rathore , Timothy Sullivan , Chih-Chao Yang
发明人： Kaushik Chanda , Birendra Agarwala , Lawrence Clevenger , Andrew Cowley , Ronald Filippi , Jason Gill , Tom Lee , Baozhen Li , Paul McLaughlin , Du Nguyen , Hazara Rathore , Timothy Sullivan , Chih-Chao Yang
IPC分类号： G01N25/72 , G01R31/26
CPC分类号： G01R31/2858 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A microelectronic element such as a chip or microelectronic wiring substrate is provided which includes a plurality of conductive interconnects for improved resistance to thermal stress. At least some of the conductive interconnects include a metallic plate, a metallic connecting line and an upper metallic via. The metallic connecting line has an upper surface at least substantially level with an upper surface of the metallic plate, an inner end connected to the metallic plate at one of the peripheral edges, and an outer end horizontally displaced from the one peripheral edge. The metallic connecting line has a width much smaller than the width of the one peripheral edge of the metallic plate and has length greater than the width of the one peripheral edge. The upper metallic via has a bottom end in contact with the metallic connecting line at a location that is horizontally displaced from the one peripheral edge by at least about 3 microns (μm).
摘要翻译：提供了诸如芯片或微电子布线基板的微电子元件，其包括用于改善耐热应力的多个导电互连。至少一些导电互连件包括金属板，金属连接线和上金属通孔。所述金属连接线具有与所述金属板的上表面至少基本平齐的上表面，在所述周边边缘中的一个处连接到所述金属板的内端和从所述一个周边边缘水平移位的外端。金属连接线的宽度远小于金属板的一个周边边缘的宽度，并且其长度大于一个周边边缘的宽度。上金属通孔在与一个外围边缘水平位移至少约3微米（mum）的位置处具有与金属连接线接触的底端。

3. 发明申请

US20060281338A1 METHOD FOR PREDICTION OF PREMATURE DIELECTRIC BREAKDOWN IN A SEMICONDUCTOR 审中-公开
标题翻译：在半导体中预测电介质破坏的方法
公开(公告)号：US20060281338A1
公开(公告)日：2006-12-14
申请号：US11160213
申请日：2005-06-14
申请人： Kaushik Chanda , Hazara Rathore , Paul McLaughlin , Robert Edwards , Lawrence Clevenger , Andrew Cowley , Chih-Chao Yang , Conrad Barile
发明人： Kaushik Chanda , Hazara Rathore , Paul McLaughlin , Robert Edwards , Lawrence Clevenger , Andrew Cowley , Chih-Chao Yang , Conrad Barile
IPC分类号： H01L21/00
CPC分类号： H01L22/14 , G01R31/2642 , G01R31/2831
摘要： The invention predicts premature dielectric breakdown in a semiconductor. At least one dielectric breakdown mode is calculated for the semiconductor wafer. If a one mode is calculated, premature dielectric breakdown will be associated with any semiconductor with a breakdown voltage less than a predetermined standard deviation of a plurality of breakdown voltages within said calculated mode. If multiple modes are calculated, the mode that most accurately represents dielectric breakdown for the semiconductor wafer is determined and premature dielectric breakdown will be associated with any semiconductor with a breakdown voltage less than a predetermined standard of the calculated mode that most accurately represents dielectric breakdown for the semiconductor wafer.
摘要翻译：本发明预测半导体中的过早的介质击穿。对于半导体晶片计算至少一个绝缘击穿模式。如果计算一种模式，则过早的介电击穿将与在所述计算模式中具有小于多个击穿电压的预定标准偏差的击穿电压的任何半导体相关联。如果计算多个模式，则确定最准确地代表半导体晶片的电介质击穿的模式，并且过早的电介质击穿将与任何具有小于计算模式的预定标准的击穿电压的半导体相关联，其最准确地表示用于半导体晶片。

4. 发明申请

US20050186689A1 Method and structure for determining thermal cycle reliability 失效
标题翻译：确定热循环可靠性的方法和结构
公开(公告)号：US20050186689A1
公开(公告)日：2005-08-25
申请号：US10783462
申请日：2004-02-20
申请人： Ronald Filippi , Jason Gill , Vincent McGahay , Paul McLaughlin , Conal Murray , Hazara Rathore , Thomas Shaw , Ping-Chuan Wang
发明人： Ronald Filippi , Jason Gill , Vincent McGahay , Paul McLaughlin , Conal Murray , Hazara Rathore , Thomas Shaw , Ping-Chuan Wang
IPC分类号： H01L21/66 , H01L23/544
CPC分类号： H01L22/34 , H01L22/32 , H01L23/5226 , H01L23/562 , H01L2924/0002 , H05K1/0268 , H05K1/0269 , H05K1/092 , Y10S438/927 , Y10T29/49004 , H01L2924/00
摘要： A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure built by the manufacturing process is evaluated based on the yield performance before the thermal cycling.
摘要翻译：用于评估通过制造工艺构建的半导体芯片结构的可靠性的装置和方法包括根据制造过程构建的测试结构。测试结构热循环，测量结构的产量。基于在热循环之前的产量性能来评估由制造工艺构建的半导体芯片结构的可靠性。

5. 发明申请

US20060273460A1 Method and structure for determining thermal cycle reliability 有权
标题翻译：确定热循环可靠性的方法和结构
公开(公告)号：US20060273460A1
公开(公告)日：2006-12-07
申请号：US11502196
申请日：2006-08-10
申请人： Ronald Filippi , Jason Gill , Vincent McGahay , Paul McLaughlin , Conal Murray , Hazara Rathore , Thomas Shaw , Ping-Chuan Wang
发明人： Ronald Filippi , Jason Gill , Vincent McGahay , Paul McLaughlin , Conal Murray , Hazara Rathore , Thomas Shaw , Ping-Chuan Wang
IPC分类号： H01L23/58 , H01L23/48 , H01L29/10 , H01L23/52 , H01L29/40
CPC分类号： H01L22/34 , H01L22/32 , H01L23/5226 , H01L23/562 , H01L2924/0002 , H05K1/0268 , H05K1/0269 , H05K1/092 , Y10S438/927 , Y10T29/49004 , H01L2924/00
摘要： A device and method for evaluating reliability of a semiconductor chip structure built by a manufacturing process includes a test structure built in accordance with a manufacturing process. The test structure is thermal cycled and the yield of the test structure is measured. The reliability of the semiconductor chip structure built by the manufacturing process is evaluated based on the yield performance before the thermal cycling.
摘要翻译：用于评估通过制造工艺构建的半导体芯片结构的可靠性的装置和方法包括根据制造过程构建的测试结构。测试结构热循环，测量结构的产量。基于在热循环之前的产量性能来评估由制造工艺构建的半导体芯片结构的可靠性。

6. 发明申请

US20110117737A1 Method of Forming Metal Interconnect Structures in Ultra Low-K Dielectrics 有权
标题翻译：在超低K电介质中形成金属互连结构的方法
公开(公告)号：US20110117737A1
公开(公告)日：2011-05-19
申请号：US12949158
申请日：2010-11-18
申请人： Birendra Agarwala , Du Nguyen , Hazara Rathore
发明人： Birendra Agarwala , Du Nguyen , Hazara Rathore
IPC分类号： H01L21/768
CPC分类号： H01L21/76885 , H01L21/76805 , H01L21/76807 , H01L21/76813 , H01L21/76829 , H01L21/76841
摘要： A metal interconnect structure in ultra low-k dielectrics is described having a capped interconnect layer; an interconnect feature with a contact via and a contact line formed in a dielectric layer, where the via is partially embedded into the interconnect layer; and a thin film formed on the dielectric layer and separating the dielectric layer from the contact line. A method of fabricating the interconnect structure is also described and includes forming a first dielectric on a capped interconnect element; forming a thin film over the first dielectric; forming a second dielectric on the thin film; forming a via opening on the second dielectric, the thin film and extending into the first dielectric; forming a line trench on a portion of the second dielectric; and filling the via opening and the line trench with a conductive material for forming a contact via and a contact line, where the contact via is partially embedded in the interconnect element.
摘要翻译：在超低k电介质中的金属互连结构被描述为具有封端的互连层; 具有接触通孔和形成在电介质层中的接触线的互连特征，其中通孔部分地嵌入到互连层中; 以及形成在电介质层上并将电介质层与接触线分离的薄膜。还描述了制造互连结构的方法，并且包括在封盖的互连元件上形成第一电介质; 在第一电介质上形成薄膜; 在薄膜上形成第二电介质; 在所述第二电介质上形成通孔，所述薄膜延伸到所述第一电介质中; 在所述第二电介质的一部分上形成线沟槽; 以及用用于形成接触通孔和接触线的导电材料填充所述通孔开口和所述线沟槽，其中所述接触通孔部分地嵌入所述互连元件中。

7. 发明申请

US20060014376A1 Stacked via-stud with improved reliability in copper metallurgy 审中-公开
标题翻译：堆叠通孔，提高了铜冶金的可靠性
公开(公告)号：US20060014376A1
公开(公告)日：2006-01-19
申请号：US11230841
申请日：2005-09-20
申请人： Birendra Agarwala , Conrad Barile , Hormazdyar Dalal , Brett Engel , Michael Lane , Ernest Levine , Xiao Liu , Vincent McGahay , John McGrath , Conal Murray , Jawahar Nayak , Du Nguyen , Hazara Rathore , Thomas Shaw
发明人： Birendra Agarwala , Conrad Barile , Hormazdyar Dalal , Brett Engel , Michael Lane , Ernest Levine , Xiao Liu , Vincent McGahay , John McGrath , Conal Murray , Jawahar Nayak , Du Nguyen , Hazara Rathore , Thomas Shaw
IPC分类号： H01L21/4763 , H01L21/44 , H01L21/31
CPC分类号： H01L23/53295 , H01L21/76807 , H01L21/76829 , H01L21/76838 , H01L23/5226 , H01L2924/0002 , Y10T428/24917 , H01L2924/00
摘要： A multilevel semiconductor integrated circuit (IC) structure including a first interconnect level including a layer of dielectric material over a semiconductor substrate, the layer of dielectric material comprising a dense material for passivating semiconductor devices and local interconnects underneath; multiple interconnect layers of dielectric material formed above the layer of dense dielectric material, each layer of dielectric material including at least a layer of low-k dielectric material; and, a set of stacked via-studs in the low-k dielectric material layers, each of said set of stacked via studs interconnecting one or more patterned conductive structures, a conductive structure including a cantilever formed in the low-k dielectric material. The dielectric layer of each of the multiple interconnection levels includes a soft low-k dielectric material, wherein the cantilever and set of stacked via-studs are integrated within the soft low-k dielectric material to increase resistance to thermal fatigue crack formation. In one embodiment, each of the set of stacked via-studs in the low-k dielectric material layers is provided with a cantilever, such that the cantilevers are interwoven by connecting a cantilever on one level to a bulk portion of the conductor line on adjacent levels of interconnection, thereby increasing flexibility of stacked via-studs between interconnection levels.
摘要翻译：一种多级半导体集成电路（IC）结构，包括在半导体衬底上包括电介质材料层的第一互连电平，所述介电材料层包括用于钝化半导体器件的致密材料和其下的局部互连; 形成在致密电介质材料层之上的电介质材料的多个互连层，每层介电材料包括至少一层低k电介质材料; 以及在低k电介质材料层中的一组堆叠的通孔螺钉，每组所述一组堆叠通孔柱互连一个或多个图案化导电结构，包括形成在低k电介质材料中的悬臂的导电结构。多个互连级别中的每一个的电介质层包括软的低k电介质材料，其中悬臂和一组堆叠的通孔螺钉集成在软低k电介质材料内，以增加对热疲劳裂纹形成的抵抗力。在一个实施例中，低k电介质材料层中的每组叠置通孔螺柱设置有悬臂，使得悬臂通过将一个级上的悬臂连接到相邻的导体线的主体部分而交织互连级别，从而增加互连级别之间堆叠通孔的灵活性。

8. 发明授权

US08466056B2 Method of forming metal interconnect structures in ultra low-k dielectrics 有权
标题翻译：在超低k电介质中形成金属互连结构的方法
公开(公告)号：US08466056B2
公开(公告)日：2013-06-18
申请号：US12949158
申请日：2010-11-18
申请人： Birendra Agarwala , Du Nguyen , Hazara Rathore
发明人： Birendra Agarwala , Du Nguyen , Hazara Rathore
IPC分类号： H01L21/4763
CPC分类号： H01L21/76885 , H01L21/76805 , H01L21/76807 , H01L21/76813 , H01L21/76829 , H01L21/76841
摘要： A metal interconnect structure in ultra low-k dielectrics is described having a capped interconnect layer; an interconnect feature with a contact via and a contact line formed in a dielectric layer, where the via is partially embedded into the interconnect layer; and a thin film formed on the dielectric layer and separating the dielectric layer from the contact line. A method of fabricating the interconnect structure is also described and includes forming a first dielectric on a capped interconnect element; forming a thin film over the first dielectric; forming a second dielectric on the thin film; forming a via opening on the second dielectric, the thin film and extending into the first dielectric; forming a line trench on a portion of the second dielectric; and filling the via opening and the line trench with a conductive material for forming a contact via and a contact line, where the contact via is partially embedded in the interconnect element.
摘要翻译：在超低k电介质中的金属互连结构被描述为具有封端的互连层; 具有接触通孔和形成在电介质层中的接触线的互连特征，其中通孔部分地嵌入到互连层中; 以及形成在电介质层上并将电介质层与接触线分离的薄膜。还描述了制造互连结构的方法，并且包括在封盖的互连元件上形成第一电介质; 在第一电介质上形成薄膜; 在薄膜上形成第二电介质; 在所述第二电介质上形成通孔，所述薄膜延伸到所述第一电介质中; 在所述第二电介质的一部分上形成线沟槽; 以及用用于形成接触通孔和接触线的导电材料填充所述通孔开口和所述线沟槽，其中所述接触通孔部分地嵌入所述互连元件中。

9. 发明申请

US20100176513A1 STRUCTURE AND METHOD OF FORMING METAL INTERCONNECT STRUCTURES IN ULTRA LOW-K DIELECTRICS 审中-公开
标题翻译：金属互连结构在超低K电介质中的结构与方法
公开(公告)号：US20100176513A1
公开(公告)日：2010-07-15
申请号：US12351272
申请日：2009-01-09
申请人： Birendra Agarwala , Du Nguyen , Hazara Rathore
发明人： Birendra Agarwala , Du Nguyen , Hazara Rathore
IPC分类号： H01L29/00 , H01L29/06 , H01L23/522 , H01L21/76
CPC分类号： H01L21/76885 , H01L21/76805 , H01L21/76807 , H01L21/76813 , H01L21/76829 , H01L21/76841
摘要： A metal interconnect structure in ultra low-k dielectrics is described having a capped interconnect layer; an interconnect feature with a contact via and a contact line formed in a dielectric layer, where the via is partially embedded into the interconnect layer; and a thin film formed on the dielectric layer and separating the dielectric layer from the contact line. A method of fabricating the interconnect structure is also described and includes forming a first dielectric on a capped interconnect element; forming a thin film over the first dielectric; forming a second dielectric on the thin film; forming a via opening on the second dielectric, the thin film and extending into the first dielectric; forming a line trench on a portion of the second dielectric; and filling the via opening and the line trench with a conductive material for forming a contact via and a contact line, where the contact via is partially embedded in the interconnect element.
摘要翻译：在超低k电介质中的金属互连结构被描述为具有封端的互连层; 具有接触通孔和形成在电介质层中的接触线的互连特征，其中通孔部分地嵌入到互连层中; 以及形成在电介质层上并将电介质层与接触线分离的薄膜。还描述了制造互连结构的方法，并且包括在封盖的互连元件上形成第一电介质; 在第一电介质上形成薄膜; 在薄膜上形成第二电介质; 在所述第二电介质上形成通孔，所述薄膜延伸到所述第一电介质中; 在所述第二电介质的一部分上形成线沟槽; 以及用用于形成接触通孔和接触线的导电材料填充所述通孔开口和所述线沟槽，其中所述接触通孔部分地嵌入所述互连元件中。

10. 发明申请

US20070111510A1 DUAL DAMASCENE MULTI-LEVEL METALLIZATION 有权
标题翻译：双重DAMASCENE多级金属化
公开(公告)号：US20070111510A1
公开(公告)日：2007-05-17
申请号：US11619748
申请日：2007-01-04
申请人： Birendra Agarwala , Eric Coker , Anthony Correale , Hazara Rathore , Timothy Sullivan , Richard Wachnik
发明人： Birendra Agarwala , Eric Coker , Anthony Correale , Hazara Rathore , Timothy Sullivan , Richard Wachnik
IPC分类号： H01L21/4763
CPC分类号： H01L21/76852 , H01L23/5226 , H01L23/528 , H01L23/5283 , H01L23/53223 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure, comprising: a lower level wire having a side and a bottom, the lower level wire comprising: a lower core conductor and a lower conductive liner, the lower conductive liner on the side and the bottom of the lower level wire; an upper level wire having a side and a bottom, the upper level wire comprising an upper core conductor and an upper conductive liner, the upper conductive liner on the side and the bottom of the upper level wire; and the upper conductive liner in contact with the lower core conductor and also in contact with the lower conductive liner in a liner-to-liner contact region.
摘要翻译：一种互连结构，包括：具有侧面和底部的下层导线，所述下层导线包括：下芯导体和下导电衬垫，所述下层导线的侧面和底部上的下导电衬垫; 具有侧面和底部的上部电线，所述上部电线包括上部芯导体和上部导电衬垫，所述上部导电衬垫位于所述上部电线的侧面和底部; 并且上导电衬套与下芯体导体接触并且还与衬套到衬垫接触区域中的下导电衬套接触。

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