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1. 发明授权

US5745781A Memoryless communications adapter including queueing and matching primitives for scalable distributed parallel computer systems 失效
标题翻译：无记忆通信适配器，包括用于可扩展分布式并行计算机系统的排队和匹配原语
公开(公告)号：US5745781A
公开(公告)日：1998-04-28
申请号：US598931
申请日：1996-02-09
申请人： Kattamuri Ekanadham , Hubertus Franke , Douglas James Joseph , Pratap Pattnaik , Marc Snir
发明人： Kattamuri Ekanadham , Hubertus Franke , Douglas James Joseph , Pratap Pattnaik , Marc Snir
IPC分类号： G06F15/173 , G06F3/00
CPC分类号： G06F15/17381
摘要： A memoryless communications adapter for communicating between the nodes of a distributed parallel computer network, each node including a non-shared program memory coupled to the memoryless communications adapter which interfaces the network. An embodiment of the present invention advantageously provides an adapter that can manipulate queues and matching tables efficiently in hardware and provide a high-level object view of queues and matching in the context of communication between nodes. Preferably, the Queue manipulation logic, Match Table manipulation logic and the Sequence Table manipulation logic are implemented in the adapter hardware which does not keep any state or resources in it that depend on the size of the system or the number of queues/tables instantiated. The actual states of these objects may be kept in the program memory, so that the adapter hardware is memoryless.
摘要翻译：一种用于在分布式并行计算机网络的节点之间进行通信的无记忆通信适配器，每个节点包括耦合到接口网络的无记忆通信适配器的非共享程序存储器。本发明的实施例有利地提供了一种适配器，其可以在硬件中有效地操纵队列和匹配表，并且在节点之间的通信的上下文中提供队列的高级对象视图和匹配。优选地，队列操作逻辑，匹配表操作逻辑和序列表操作逻辑在适配器硬件中实现，该适配器硬件不保持依赖于系统的大小或实例化的队列/表的数量的任何状态或资源。这些对象的实际状态可以保存在程序存储器中，以便适配器硬件是无记忆的。

2. 发明授权

US06480941B1 Secure partitioning of shared memory based multiprocessor system 有权
标题翻译：基于共享内存的多处理器系统的安全分区
公开(公告)号：US06480941B1
公开(公告)日：2002-11-12
申请号：US09256035
申请日：1999-02-23
申请人： Hubertus Franke , Mark Edwin Giampapa , Joefon Jann , Douglas James Joseph , Pratap Chandra Pattnaik
发明人： Hubertus Franke , Mark Edwin Giampapa , Joefon Jann , Douglas James Joseph , Pratap Chandra Pattnaik
IPC分类号： G06F1202
CPC分类号： G06F12/0284
摘要： A method and apparatus for sharing memory in a multiprocessor computing system. More specifically, this invention provides a number of system buses with each bus being connected to a respective memory controller which controls a corresponding partition of the memory. Any one of the processors can use any one of the system buses to send real addresses to the connected memory controller which then converts the real addresses into physical addresses corresponding to the partition of memory that is controlled by the receiving memory controller. The processors can be dynamically assigned to different partitions of the memory by via a switching mechanism.
摘要翻译：一种用于在多处理器计算系统中共享存储器的方法和装置。更具体地，本发明提供了多个系统总线，其中每个总线连接到控制存储器的相应分区的相应存储器控制器。任何一个处理器可以使用系统总线中的任何一个向所连接的存储器控制器发送真实地址，然后将实际地址转换成对应于由接收存储器控制器控制的存储器分区对应的物理地址。处理器可以通过切换机制动态分配给存储器的不同分区。

3. 发明授权

US08229916B2 Method for massively parallel multi-core text indexing 失效
标题翻译：大规模并行多核文本索引的方法
公开(公告)号：US08229916B2
公开(公告)日：2012-07-24
申请号：US12248430
申请日：2008-10-09
申请人： Ankur Narang , Vikas Agarwal , Vijay Kumar Garg , Douglas James Joseph , Monu Kedia , Maged M. Michael
发明人： Ankur Narang , Vikas Agarwal , Vijay Kumar Garg , Douglas James Joseph , Monu Kedia , Maged M. Michael
IPC分类号： G06F17/30
CPC分类号： G06F17/30011
摘要： There is provided, in a parallel pipelined structure on a multi-core device, a method for parallel pipelined multi-core indexing. The method includes generating one or more single document indexes respectively corresponding to one or more single documents of a given data stream. The method further includes generating one or more multi-document interval-based hash tables from the one or more single document indexes. The method also includes generating a global hash table formed from merging one or more of the multi-document interval-based hash tables, the global hash table representing a collective index for all of the single documents for which the one or more single document indexes were generated.
摘要翻译：在多核设备上以并行流水线结构提供了一种用于并行流水线多核索引的方法。该方法包括分别对应于给定数据流的一个或多个单个文档生成一个或多个单个文档索引。该方法还包括从一个或多个单个文档索引生成一个或多个基于多文档间隔的散列表。该方法还包括生成通过合并一个或多个基于多文档间隔的散列表形成的全局哈希表，全局散列表表示一个或多个单个文档索引的所有单个文档的集合索引生成。

4. 发明申请

US20090267238A1 BRIDGES FOR INTERCONNECTING INTERPOSERS IN MULTI-CHIP INTEGRATED CIRCUITS 有权
标题翻译：用于在多芯片集成电路中互连接口的桥
公开(公告)号：US20090267238A1
公开(公告)日：2009-10-29
申请号：US12110579
申请日：2008-04-28
申请人： Douglas James Joseph , John Ulrich Knickerbocker
发明人： Douglas James Joseph , John Ulrich Knickerbocker
IPC分类号： H01L23/538 , H01L21/60
CPC分类号： H01L23/49833 , H01L24/16 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L2224/16 , H01L2224/16145 , H01L2224/16227 , H01L2224/17181 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06572 , H01L2924/00013 , H01L2924/01079 , H01L2924/12044 , H01L2924/14 , H01L2924/1433 , H01L2924/15192 , H01L2924/15311 , H01L2224/29099
摘要： A structure and a method for forming the same. The structure includes a substrate, a first interposer on the substrate, a second interposer on the substrate, and a first bridge. The first and second interposers are electrically connected to the substrate. The first bridge is electrically connected to the first and second interposers.
摘要翻译：一种结构及其形成方法。该结构包括衬底，衬底上的第一插入件，衬底上的第二插入件和第一桥。第一和第二插入件电连接到基板。第一桥电连接到第一和第二插入件。

5. 发明申请

US20110312129A1 INTERCONNECTION IN MULTI-CHIP WITH INTERPOSERS AND BRIDGES 有权
标题翻译：多芯片互连与间插和桥接
公开(公告)号：US20110312129A1
公开(公告)日：2011-12-22
申请号：US13219801
申请日：2011-08-29
申请人： Douglas James Joseph , John Ulrich Knickerbocker
发明人： Douglas James Joseph , John Ulrich Knickerbocker
IPC分类号： H01L21/60
CPC分类号： H01L23/49833 , H01L24/16 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L2224/16 , H01L2224/16145 , H01L2224/16227 , H01L2224/17181 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06572 , H01L2924/00013 , H01L2924/01079 , H01L2924/12044 , H01L2924/14 , H01L2924/1433 , H01L2924/15192 , H01L2924/15311 , H01L2224/29099
摘要： A structure formation method. The method may include: attaching a substrate, a first interposer, a second interposer, and a first bridge together such that the first interposer is on and electrically connected to the substrate, the second interposer is on and electrically connected to the substrate, the first interposer comprises at least a first transistor, and the second interposer comprises at least a second transistor. The method may alternatively include: disposing both a first and second interposer on a substrate, wherein the first and second interposer are each electrically connected to the substrate; and electrically connecting a first bridge to the first and second interposers, wherein (i) the first bridge is in direct physical contact with the substrate or (ii) a bottom surface of the first bridge is within the substrate and below a top surface of the substrate.
摘要翻译：一种结构形成方法。该方法可以包括：将基板，第一插入件，第二插入件和第一桥接器连接在一起，使得第一插入件在基板上并电连接到第二插入器，第二插入器在基板上电连接，至少包括第一晶体管，并且第二插入器至少包括第二晶体管。该方法可以可替代地包括：将第一和第二插入件布置在衬底上，其中第一和第二插入器各自电连接到衬底; 以及将第一桥接电连接到所述第一和第二插入件，其中（i）所述第一桥与所述衬底直接物理接触，或（ii）所述第一桥的底表面在所述衬底内并且位于所述衬底的顶表面之下基质。

6. 发明授权

US6105071A Source and destination initiated interrupt system for message arrival notification 失效
标题翻译：源和目的地发起的消息到达通知中断系统
公开(公告)号：US6105071A
公开(公告)日：2000-08-15
申请号：US826888
申请日：1997-04-08
申请人： Christine M. Desnoyers , Douglas James Joseph , Francis A. Kampf
发明人： Christine M. Desnoyers , Douglas James Joseph , Francis A. Kampf
IPC分类号： G06F9/46 , G06F9/48 , G06F13/00
CPC分类号： G06F9/4812 , G06F9/546
摘要： A method, system, and associated program code and data structures are provided for a message processing system in which messages are passed from source nodes to destination nodes. Notification of the arrival of the messages at the destination nodes can be effected by programmable source initiated interrupts or destination initiated interrupts. The source initiated interrupts are implemented as set fields embedded in the message packets sent from a source node to a destination node and trigger the requisite interrupt at the destination node upon message arrival. The destination initiated interrupts are implemented as pre-set fields in anticipatory buffers which are allocated at the destination node for incoming messages from the source node. Standard incoming message queue polling, as well as interrupt enabling and disabling functions are also provided, which together allow the system to selectively invoke interrupt or alternative strategies to notify destination nodes of arriving messages.
摘要翻译：为消息处理系统提供了一种方法，系统和相关联的程序代码和数据结构，其中消息从源节点传递到目标节点。可以通过可编程源启动的中断或目的地发起的中断来实现消息到目的地节点的到达的通知。源发起的中断被实现为嵌套在从源节点发送到目的地节点的消息分组中的设置字段，并且在消息到达时触发目的地节点处的必要中断。目的地发起的中断被实现为预定缓冲区中的预置字段，其在目的地节点处分配用于来自源节点的传入消息。还提供了标准输入消息队列轮询以及中断使能和禁用功能，这些功能一起允许系统选择性地调用中断或替代策略来通知目的地节点到达的消息。

7. 发明授权

US08008764B2 Bridges for interconnecting interposers in multi-chip integrated circuits 有权
标题翻译：用于在多芯片集成电路中互连插入器的桥接器
公开(公告)号：US08008764B2
公开(公告)日：2011-08-30
申请号：US12110579
申请日：2008-04-28
申请人： Douglas James Joseph , John Ulrich Knickerbocker
发明人： Douglas James Joseph , John Ulrich Knickerbocker
IPC分类号： H01L23/02 , H05K7/00
CPC分类号： H01L23/49833 , H01L24/16 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L2224/16 , H01L2224/16145 , H01L2224/16227 , H01L2224/17181 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06572 , H01L2924/00013 , H01L2924/01079 , H01L2924/12044 , H01L2924/14 , H01L2924/1433 , H01L2924/15192 , H01L2924/15311 , H01L2224/29099
摘要： A structure and a method for forming the same. The structure includes a substrate, a first interposer on the substrate, a second interposer on the substrate, and a first bridge. The first and second interposers are electrically connected to the substrate. The first bridge is electrically connected to the first and second interposers.
摘要翻译：一种结构及其形成方法。该结构包括衬底，衬底上的第一插入件，衬底上的第二插入件和第一桥。第一和第二插入件电连接到基板。第一桥电连接到第一和第二插入件。

8. 发明授权

US08138015B2 Interconnection in multi-chip with interposers and bridges 有权
标题翻译：多芯片与内插器和桥接器的互连
公开(公告)号：US08138015B2
公开(公告)日：2012-03-20
申请号：US13219801
申请日：2011-08-29
申请人： Douglas James Joseph , John Ulrich Knickerbocker
发明人： Douglas James Joseph , John Ulrich Knickerbocker
IPC分类号： H01L21/00
CPC分类号： H01L23/49833 , H01L24/16 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L2224/16 , H01L2224/16145 , H01L2224/16227 , H01L2224/17181 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06572 , H01L2924/00013 , H01L2924/01079 , H01L2924/12044 , H01L2924/14 , H01L2924/1433 , H01L2924/15192 , H01L2924/15311 , H01L2224/29099
摘要： A structure formation method. The method may include: attaching a substrate, a first interposer, a second interposer, and a first bridge together such that the first interposer is on and electrically connected to the substrate, the second interposer is on and electrically connected to the substrate, the first interposer comprises at least a first transistor, and the second interposer comprises at least a second transistor. The method may alternatively include: disposing both a first and second interposer on a substrate, wherein the first and second interposer are each electrically connected to the substrate; and electrically connecting a first bridge to the first and second interposers, wherein (i) the first bridge is in direct physical contact with the substrate or (ii) a bottom surface of the first bridge is within the substrate and below a top surface of the substrate.
摘要翻译：一种结构形成方法。该方法可以包括：将基板，第一插入件，第二插入件和第一桥接器连接在一起，使得第一插入件在基板上并电连接到第二插入器，第二插入器在基板上并电连接到第一基板至少包括第一晶体管，并且第二插入器至少包括第二晶体管。该方法可以可替代地包括：将第一和第二插入件布置在衬底上，其中第一和第二插入器各自电连接到衬底; 以及将第一桥接电连接到所述第一和第二插入件，其中（i）所述第一桥与所述衬底直接物理接触，或（ii）所述第一桥的底表面在所述衬底内并且位于所述衬底的顶表面之下基质。

9. 发明申请

US20100094870A1 METHOD FOR MASSIVELY PARALLEL MULTI-CORE TEXT INDEXING 失效
标题翻译：用于大规模并行多重文本索引的方法
公开(公告)号：US20100094870A1
公开(公告)日：2010-04-15
申请号：US12248430
申请日：2008-10-09
申请人： Ankur Narang , Vikas Agarwal , Vijay Kumar Garg , Douglas James Joseph , Monu Kedia , Magad M. Michael
发明人： Ankur Narang , Vikas Agarwal , Vijay Kumar Garg , Douglas James Joseph , Monu Kedia , Magad M. Michael
IPC分类号： G06F17/30 , G06F9/00
CPC分类号： G06F17/30011
摘要： There is provided, in a parallel pipelined structure on a multi-core device, a method for parallel pipelined multi-core indexing. The method includes generating one or more single document indexes respectively corresponding to one or more single documents of a given data stream. The method further includes generating one or more multi-document interval-based hash tables from the one or more single document indexes. The method also includes generating a global hash table formed from merging one or more of the multi-document interval-based hash tables, the global hash table representing a collective index for all of the single documents for which the one or more single document indexes were generated.
摘要翻译：在多核设备上以并行流水线结构提供了一种用于并行流水线多核索引的方法。该方法包括分别对应于给定数据流的一个或多个单个文档生成一个或多个单个文档索引。该方法还包括从一个或多个单个文档索引生成一个或多个基于多文档间隔的散列表。该方法还包括生成通过合并一个或多个基于多文档间隔的散列表形成的全局哈希表，全局散列表表示一个或多个单个文档索引的所有单个文档的集合索引生成。

10. 发明授权

US6098105A Source and destination initiated interrupt method for message arrival notification 失效
标题翻译：源和目的地发起的消息到达通知中断方法
公开(公告)号：US6098105A
公开(公告)日：2000-08-01
申请号：US835434
申请日：1997-04-08
申请人： Christine M. Desnoyers , Douglas James Joseph , Francis A. Kampf
发明人： Christine M. Desnoyers , Douglas James Joseph , Francis A. Kampf
IPC分类号： H04L12/56 , G06F13/00
CPC分类号： H04L49/9047 , H04L12/5693 , H04L47/62 , H04L49/90 , H04L49/901 , H04L49/9068
摘要： A method, system, and associated program code and data structures are provided for a message processing system in which messages are passed from source nodes to destination nodes. Notification of the arrival of the messages at the destination nodes can be effected by programmable source initiated interrupts or destination initiated interrupts. The source initiated interrupts are implemented as set fields embedded in the message packets sent from a source node to a destination node and trigger the requisite interrupt at the destination node upon message arrival. The destination initiated interrupts are implemented as pre-set fields in anticipatory buffers which are allocated at the destination node for incoming messages from the source node. Standard incoming message queue polling, as well as interrupt enabling and disabling functions are also provided, which together allow the system to selectively invoke interrupt or alternative strategies to notify destination nodes of arriving messages.
摘要翻译：为消息处理系统提供了一种方法，系统和相关联的程序代码和数据结构，其中消息从源节点传递到目标节点。可以通过可编程源启动的中断或目的地发起的中断来实现消息到目的地节点的到达的通知。源发起的中断被实现为嵌套在从源节点发送到目的地节点的消息分组中的设置字段，并且在消息到达时触发目的地节点处的必要中断。目的地发起的中断被实现为预定缓冲区中的预置字段，其在目的地节点处分配用于来自源节点的传入消息。还提供了标准输入消息队列轮询以及中断使能和禁用功能，这些功能一起允许系统选择性地调用中断或替代策略来通知目的地节点到达的消息。

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