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1. 发明授权

US5132771A Semiconductor memory device having flip-flop circuits 失效
标题翻译：具有触发电路的半导体存储器件
公开(公告)号：US5132771A
公开(公告)日：1992-07-21
申请号：US503928
申请日：1990-04-04
申请人： Toshiaki Yamanaka , Naotaka Hashimoto , Takashi Hashimoto , Akihiro Shimizu , Koichiro Ishibashi , Katsuro Sasaki , Katsuhiro Shimohigashi , Eiji Takeda , Yoshio Sakai , Takashi Nishida , Osamu Minato , Toshiaki Masuhara , Shoji Hanamura , Shigeru Honjo , Nobuyuki Moriwaki
发明人： Toshiaki Yamanaka , Naotaka Hashimoto , Takashi Hashimoto , Akihiro Shimizu , Koichiro Ishibashi , Katsuro Sasaki , Katsuhiro Shimohigashi , Eiji Takeda , Yoshio Sakai , Takashi Nishida , Osamu Minato , Toshiaki Masuhara , Shoji Hanamura , Shigeru Honjo , Nobuyuki Moriwaki
IPC分类号： G11C11/412 , H01L27/11
CPC分类号： G11C11/4125 , H01L27/1104 , Y10S257/903
摘要： A semiconductor static random access memory having a high .alpha.-ray immunity and a high packing density is provided which is also capable of high-speed operation. A semiconductor memory device comprises static random access memory cells each including a flip-flop circuit. Storage nodes of each flip-flop circuit have respective pn-junctions formed at regions sandwiched between gate electrodes of first insulated gate field effect transistors and gate electrodes of second insulated gate field effect transistors, respectively. The pn-junction has an area smaller than that of a channel portion of the first or second insulated gate field effect transistor. The gate electrode of one of the two first insulated gate field effect transistors and the drain region of the other insulated gate field effect transistor, on one hand, and the drain region of the one insulated gate field effect transistor and the gate electrode of the other insulated gate field effect transistor, on the other hand, are electrically cross-coupled mutually through first and second electrically conductive films, respectively. Also, to increase packing density and enhance immunity to soft error, the gate electrodes of the first and second insulated gate field effect transistors extend substantially in parallel with one another and the channel regions of the first and second insulated gate field effect transistors extend substantially in parallel with one another.
摘要翻译：提供了具有高α射线抗扰度和高封装密度的半导体静态随机存取存储器，其也能够进行高速操作。半导体存储器件包括每个包括触发器电路的静态随机存取存储器单元。每个触发器电路的存储节点分别形成在夹在第一绝缘栅场效应晶体管的栅电极和第二绝缘栅场效应晶体管的栅电极之间的区域处的各pn结。 pn结的面积小于第一或第二绝缘栅场效应晶体管的沟道部分的面积。两个第一绝缘栅场效应晶体管中的一个的栅极电极和另一个绝缘栅场效应晶体管的漏极区域以及一个绝缘栅场效应晶体管的漏极区域和另一个绝缘栅极场效应晶体管的栅极电极另一方面，绝缘栅场效应晶体管分别通过第一和第二导电膜互相交叉耦合。此外，为了增加封装密度并增强对软误差的抵抗力，第一和第二绝缘栅场效应晶体管的栅极彼此基本平行地延伸，并且第一和第二绝缘栅场效应晶体管的沟道区域基本上以彼此平行。

2. 发明授权

US5126974A Sense amplifier for a memory device 失效
标题翻译：用于存储器件的感应放大器
公开(公告)号：US5126974A
公开(公告)日：1992-06-30
申请号：US465040
申请日：1990-01-16
申请人： Katsuro Sasaki , Katsuhiro Shimohigashi , Koichiro Ishibashi , Shoji Hanamura
发明人： Katsuro Sasaki , Katsuhiro Shimohigashi , Koichiro Ishibashi , Shoji Hanamura
IPC分类号： G11C7/06 , G11C11/419
CPC分类号： G11C7/062 , G11C11/419 , G11C7/065
摘要： A MOS transistor sense amplifier employs cross coupled positive feedback for the load circuit of a differential amplifier with an equalizing switch at the amplifier output, and preferably also at the input. This basis amplifier circuit may be repeated in stages. When stages are employed, it is desirable that the first stage employs current mirror loading of the differential amplifier to reduce the data delay. Data delay is further reduced by providing strong amplification during the sense portion of the read cycle with a preamplifier, which preamplifier has its amplification reduced, preferably to unity by being turned off, when the sense portion of the cycle is finished, and most preferably when the input and output data lines are directly connected independently of the preamplifier, so that the preamplifier may be completely turned off to lower power consumption.
摘要翻译： MOS晶体管感测放大器采用交叉耦合的正反馈给差分放大器的负载电路，在放大器输出端具有均衡开关，优选也在输入端。该基本放大器电路可以分阶段地重复。当采用级时，期望第一级采用差分放大器的电流镜像负载来减少数据延迟。通过在读周期的感测部分期间通过在前置放大器上提供强放大来进一步降低数据延迟，当循环的感测部分完成时，前置放大器的放大减小，优选地被关闭，优选地，当输入和输出数据线独立于前置放大器直接连接，从而可以完全关闭前置放大器以降低功耗。

3. 发明授权

US5021944A Semiconductor memory having redundancy circuit for relieving defects 失效
标题翻译：具有用于消除缺陷的冗余电路的半导体存储器
公开(公告)号：US5021944A
公开(公告)日：1991-06-04
申请号：US376245
申请日：1989-07-06
申请人： Katsuro Sasaki , Katsuhiro Shimohigashi , Shoji Hanamura
发明人： Katsuro Sasaki , Katsuhiro Shimohigashi , Shoji Hanamura
IPC分类号： G11C11/413 , G11C29/00 , G11C29/04
CPC分类号： G11C29/846
摘要： A method and apparatus for quickly masking defective memory elements with substitute memory elements includes first and second memory blocks. The first memory block includes a first memory array and a second spare memory array. The second memory block includes a second memory array and a first spare memory array. A first word from the first memory array is selected concurrently with a first substitute word from the first spare memory. An address signal is decoded and then compared with data representative of a defective word. In the event it is determined, as a result of this comparison, that the first word is defective, the first substitute word is then communicated to a common data bus. Alternatively, the first word is communicated to the common data bus.
摘要翻译：用替代存储器元件快速掩蔽有缺陷的存储器元件的方法和装置包括第一和第二存储器块。第一存储器块包括第一存储器阵列和第二备用存储器阵列。第二存储器块包括第二存储器阵列和第一备用存储器阵列。与来自第一备用存储器的第一替代字同时选择来自第一存储器阵列的第一个字。地址信号被解码，然后与表示有缺陷的字的数据进行比较。在确定的情况下，作为该比较的结果，第一个字是有缺陷的，然后第一个替代字被传送到公共数据总线。或者，第一个字被传送到公共数据总线。

4. 发明授权

US5047706A Constant current-constant voltage circuit 失效
标题翻译：恒流恒压电路
公开(公告)号：US5047706A
公开(公告)日：1991-09-10
申请号：US577512
申请日：1990-09-05
申请人： Koichiro Ishibashi , Katsuro Sasaki , Katsuhiro Shimohigashi
发明人： Koichiro Ishibashi , Katsuro Sasaki , Katsuhiro Shimohigashi
IPC分类号： G05F1/46 , G05F3/24 , G11C11/407 , H01L21/822 , H01L27/04
CPC分类号： G05F3/247 , G05F1/463 , G05F1/465 , G05F3/245 , Y10S323/907
摘要： In a constant current-constant voltage circuit disclosed herein, gates of MOSFETs Q.sub.1 and Q.sub.2 are connected together, and the gate of the MOSFET Q.sub.1 is connected to the drain thereof. Further, the source of the MOSFET Q.sub.1 is connected to ground potential GND whereas the source of the MOSFET Q.sub.2 is connected to the drain of a MOSFET Q.sub.3 having a gate connected to power supply voltage V.sub.DD and a source connected to the ground voltage GND. A current mirror circuit including Q.sub.4 and Q.sub.5 has an input and an output respectively connected to the drain of the second MOSFET Q.sub.2 and the drain of the first MOSFET Q.sub.1. A first coefficient (W.sub.3 L.sub.2 /L.sub.3 W.sub.2) depending upon channel lengths (L.sub.2, L.sub.3) and channel widths (W.sub.2, W.sub.3) of the MOSFETs Q.sub.2 and Q.sub.3 is set at a value not larger than a predetermined value. Therefore, the MOSFET Q.sub.3 operates in a linear region as high resistance, and the MOSFETs Q.sub.1 and Q.sub.2 operate in a sub-threshold region. As a result, the dependence upon temperature is significantly improved.
摘要翻译：在本文公开的恒定电流恒定电压电路中，MOSFET Q1和Q2的栅极连接在一起，并且MOSFET Q1的栅极连接到其漏极。此外，MOSFET Q1的源极连接到地电位GND，而MOSFET Q2的源极连接到具有连接到电源电压VDD的栅极和连接到地电压GND的源极的MOSFET Q3的漏极。包括Q4和Q5的电流镜电路具有分别连接到第二MOSFET Q2的漏极和第一MOSFET Q1的漏极的输入和输出。取决于MOSFET Q2和Q3的沟道长度（L2，L3）和沟道宽度（W2，W3）的第一系数（W3L2 / L3W2）被设置为不大于预定值的值。因此，MOSFET Q3以高电阻工作在线性区域，并且MOSFET Q1和Q2在亚阈值区域中工作。结果，对温度的依赖性显着提高。

5. 发明授权

US5134581A Highly stable semiconductor memory with a small memory cell area 失效
标题翻译：高度稳定的半导体存储器具有小的存储单元面积
公开(公告)号：US5134581A
公开(公告)日：1992-07-28
申请号：US604469
申请日：1990-10-29
申请人： Koichiro Ishibashi , Katsuro Sasaki , Katsuhiro Shimohigashi , Toshiaki Yamanaka , Naotaka Hashimoto , Takashi Hashimoto , Akihiro Shimizu
发明人： Koichiro Ishibashi , Katsuro Sasaki , Katsuhiro Shimohigashi , Toshiaki Yamanaka , Naotaka Hashimoto , Takashi Hashimoto , Akihiro Shimizu
IPC分类号： G11C11/412 , G11C11/419 , H01L21/8244 , H01L27/11
CPC分类号： G11C11/412 , G11C11/419 , H01L27/1108
摘要： In order to obtain a highly stable SRAM cell having a small cell area, a cell ratio R is set to be R=(W.sub.DEFF /L.sub.DEFF)/(W.sub.TEFF /L.sub.TEFF)
摘要翻译：为了获得具有小单元区域的高度稳定的SRAM单元，单元比率R被设置为R =（WDEFF / LDEFF）/（WTEFF / LTEFF）<3，其中LDEFF和WDEFF表示有效信道长度，并且有效沟道宽度分别为两个驱动MOSFET 3和4，LTEFF和WTEFF分别表示两个传输MOSFET 5和6的有效沟道长度和有效沟道宽度。此外，流入有源负载MOSFET 1和2的最大电流IR被设置为大于当跨栅极施加阈值电压时流入驱动器MOSFET 5的电流IL（1×10 -8 A），并且 MOSFET 5.一对有源负载MOSFET 1和2堆叠在驱动器MOSFET 3和4以及传输MOSFET 5和6上。

6. 发明授权

US5088065A Static type semiconductor memory 失效
标题翻译：静态型半导体存储器
公开(公告)号：US5088065A
公开(公告)日：1992-02-11
申请号：US593584
申请日：1990-10-05
申请人： Shoji Hanamura , Masaaki Kubotera , Katsuro Sasaki , Takao Oono , Kiyotsugu Ueda
发明人： Shoji Hanamura , Masaaki Kubotera , Katsuro Sasaki , Takao Oono , Kiyotsugu Ueda
IPC分类号： G11C7/06 , G11C11/419
CPC分类号： G11C7/062 , G11C11/419
摘要： Information read out from a memory cell of a static type semiconductor memory is subjected to multi-stage sense amplification in an initial stage sense amplifier, a post-stage sense amplifier and a main amplifier and then transmitted to the input of an output buffer circuit. Since an equalizing circuit is connected to the complementary inputs of each stage of the multi-stage sense amplifier, an inverse information read operation can be executed at high speed. Initially, the initial stage sense amplifier, the post-stage sense amplifier and the main amplifier are controlled to operate in high amplification gain conditions so as to execute high speed sense amplification and thereafter controlled to operate in such low power consumption conditions that the read-out information output obtained by the high speed sense amplification will not disappear.
摘要翻译：从静态半导体存储器的存储单元读出的信息在初级读出放大器，后级读出放大器和主放大器中进行多级感测放大，然后传输到输出缓冲电路的输入端。由于均衡电路连接到多级读出放大器的各级的互补输入，所以可以高速执行反向信息读取操作。最初，初级读出放大器，后级读出放大器和主放大器被控制为在高放大增益条件下工作，以便执行高速感测放大，此后被控制以在低功耗条件下工作，通过高速感测放大获得的输出信息输出不会消失。

7. 发明授权

US4891792A Static type semiconductor memory with multi-stage sense amplifier 失效
标题翻译：具有多级读出放大器的静态型半导体存储器
公开(公告)号：US4891792A
公开(公告)日：1990-01-02
申请号：US215824
申请日：1988-07-06
申请人： Shoji Hanamura , Masaaki Kubotera , Katsuro Sasaki , Takao Oono , Kiyotsugu Ueda
发明人： Shoji Hanamura , Masaaki Kubotera , Katsuro Sasaki , Takao Oono , Kiyotsugu Ueda
IPC分类号： G11C11/419
CPC分类号： G11C11/419
摘要： Information read out from a memory cell of a static type semiconductor memory is subjected to multi-stage sense amplification in an initial stage sense amplifier, a post-stage snese amplifier and a main amplifier and then transmitted to the input of an output buffer circuit. Since an equalizing circuit is connected to the complementary inputs of each stage of the multi-stage sense amplifier, an inverse information read operation can be executed at high speed. Initially, the initial stage sense amplifier, the post-stage sense amplifier and the main amplifier are controlled to operate in high amplification gain conditions so as to execute high speed sense amplification and thereafter controlled to operate in such low power consumption conditions that the read-out information output obtained by the high speed sense amplification will not disappear.
摘要翻译：从静态型半导体存储器的存储单元读出的信息在初级读出放大器，后置放大器和主放大器中进行多级感测放大，然后传输到输出缓冲器电路的输入端。由于均衡电路连接到多级读出放大器的各级的互补输入，所以可以高速执行反向信息读取操作。最初，初级读出放大器，后级读出放大器和主放大器被控制为在高放大增益条件下工作，以便执行高速感测放大，此后被控制以在低功耗条件下工作，通过高速感测放大获得的输出信息输出不会消失。

8. 发明授权

US5700704A Process for fabricating a semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US5700704A
公开(公告)日：1997-12-23
申请号：US458615
申请日：1995-06-02
申请人： Shuji Ikeda , Satoshi Meguro , Soichiro Hashiba , Isamu Kuramoto , Atsuyoshi Koike , Katsuro Sasaki , Koichiro Ishibashi , Toshiaki Yamanaka , Naotaka Hashimoto , Nobuyuki Moriwaki , Shigeru Takahashi , Atsushi Hiraishi , Yutaka Kobayashi , Seigou Yukutake
发明人： Shuji Ikeda , Satoshi Meguro , Soichiro Hashiba , Isamu Kuramoto , Atsuyoshi Koike , Katsuro Sasaki , Koichiro Ishibashi , Toshiaki Yamanaka , Naotaka Hashimoto , Nobuyuki Moriwaki , Shigeru Takahashi , Atsushi Hiraishi , Yutaka Kobayashi , Seigou Yukutake
IPC分类号： H01L27/11 , H01L21/8244
CPC分类号： H01L27/11 , H01L27/1104 , Y10S257/903 , Y10S257/904
摘要： A method is provided for manufacturing a semiconductor integrated circuit device which includes a capacitor element having a first electrode, a second electrode, and a dielectric film formed between said first electrode and said second electrode. In particular, the method includes the step of forming at least one of the first electrode and second electrode with a polycrystalline silicon film which is deposited over a semiconductor substrate by a CVD method and which is doped with an impurity during said deposition to decrease the resistance of the polycrystalline silicon film. The capacitor element formed by this method is particularly useful for memory cells of static random access memory devices.
摘要翻译：提供一种用于制造半导体集成电路器件的方法，该半导体集成电路器件包括具有形成在所述第一电极和所述第二电极之间的第一电极，第二电极和电介质膜的电容器元件。特别地，该方法包括用多晶硅膜形成第一电极和第二电极中的至少一个的步骤，该多晶硅膜通过CVD方法沉积在半导体衬底上，并且在所述沉积期间掺杂有杂质以降低电阻的多晶硅膜。通过该方法形成的电容器元件对静态随机存取存储器件的存储单元特别有用。

9. 发明授权

US5652457A Semiconductor integrated circuit device and process for fabricating the same 失效
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US5652457A
公开(公告)日：1997-07-29
申请号：US351173
申请日：1994-11-30
申请人： Shuji Ikeda , Satoshi Meguro , Soichiro Hashiba , Isamu Kuramoto , Atsuyoshi Koike , Katsuro Sasaki , Koichiro Ishibashi , Toshiaki Yamanaka , Naotaka Hashimoto , Nobuyuki Moriwaki , Shigeru Takahashi , Atsushi Hiraishi , Yutaka Kobayashi , Seigou Yukutake
发明人： Shuji Ikeda , Satoshi Meguro , Soichiro Hashiba , Isamu Kuramoto , Atsuyoshi Koike , Katsuro Sasaki , Koichiro Ishibashi , Toshiaki Yamanaka , Naotaka Hashimoto , Nobuyuki Moriwaki , Shigeru Takahashi , Atsushi Hiraishi , Yutaka Kobayashi , Seigou Yukutake
IPC分类号： H01L27/11 , H01L29/76
CPC分类号： H01L27/11 , H01L27/1104 , Y10S257/903 , Y10S257/904
摘要： Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and the word lines are individually formed of different conductive layers. The drive MISFETs and the transfer MISFETs are individually arranged to cross each other in the gate length direction. The word lines are extended in the gate length direction of the gate electrodes of the drive MISFETs and caused to cross the gate electrodes of the drive MISFETs partially.The two transfer MISFETs of the memory cell have their individual gate electrodes connected with two respective word lines spaced from each other and extended in an identical direction. The region defined by the two word lines is arranged therein with the two drive MISFETs and the source lines.The source line is formed of a conductive layer identical to that of the word line. The individual data lines of the complementary data line are formed of an identical conductive layer which is different from that of the word line and the source line. The identical conductive layer between the word line and source line and the complementary data line is formed with two word lines: a main word line extended in the first direction identical to that of the word line and source line and used by adopting the divided word line system: and a sub-word line used by adopting the double word line system.
摘要翻译：这里公开了一种半导体集成电路器件，其包括具有其存储单元的SRAM，SRAM由通过字线控制的转移MISFET和驱动MISFET构成。驱动MISFET的栅电极和存储单元的转移MISFET的栅电极和字线分别由不同的导电层形成。驱动MISFET和转移MISFET分别布置成在栅极长度方向上彼此交叉。字线在驱动MISFET的栅电极的栅极长度方向上延伸，并且部分地与驱动MISFET的栅电极交叉。存储器单元的两个转移MISFET的各自的栅极电极与彼此间隔开并沿相同方向延伸的两个相应字线连接。由两个字线限定的区域配置有两个驱动MISFET和源极线。源极线由与字线的导电层相同的导电层形成。互补数据线的各个数据线由与字线和源极线不同的导电层形成。字线和源极线与互补数据线之间的相同的导电层由两条字线形成：主字线在第一方向上延伸，与字线和源极线相同，并通过采用分割字线系统：采用双字线系统使用的子字线。

10. 发明授权

US5005068A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5005068A
公开(公告)日：1991-04-02
申请号：US376953
申请日：1989-07-07
申请人： Shuji Ikeda , Katsuro Sasaki , Kouichi Nagasawa , Satoshi Meguro
发明人： Shuji Ikeda , Katsuro Sasaki , Kouichi Nagasawa , Satoshi Meguro
IPC分类号： H01L21/768 , G11C11/41 , H01L21/8244 , H01L23/522 , H01L27/10 , H01L27/11
CPC分类号： H01L27/11 , H01L27/1112 , Y10S257/903 , Y10S257/904 , Y10S257/906
摘要： A static RAM having first word lines each defined by extended gate electrodes of MISFETs constituting memory cells, and second word lines which are separate from the first word lines. The RAM has a wiring for supplying a fixed potential such as a ground potential to the memory cells, the wiring being formed from the same layer as that for forming the second word lines.
摘要翻译：一种静态RAM，其具有由构成存储单元的MISFET的扩展栅极电极和由第一字线分开的第二字线构成的第一字线。 RAM具有用于向存储单元提供诸如地电位的固定电位的布线，布线由与用于形成第二字线的层相同的层形成。

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