专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06992358B2 Semiconductor device and method for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06992358B2
公开(公告)日：2006-01-31
申请号：US10874732
申请日：2004-06-24
申请人： Katsuhiko Hieda , Kazuya Matsuzawa , Daisuke Hagishima
发明人： Katsuhiko Hieda , Kazuya Matsuzawa , Daisuke Hagishima
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/785 , H01L27/108 , H01L27/10814 , H01L27/10829 , H01L27/10873 , H01L27/10879 , H01L27/1211 , H01L29/42392 , H01L29/66545 , H01L29/66795 , H01L29/7854 , H01L29/78648
摘要： Disclosed is a semiconductor device comprising an underlying insulating film having a depression, a semiconductor structure which includes a first semiconductor portion having a portion formed on the underlying insulating film and a first overlap portion which overlaps the depression, a second semiconductor portion having a portion formed on the underlying insulating film and a second overlap portion which overlaps the depression, and a third semiconductor portion disposed between the first and second semiconductor portions and having a portion disposed above the depression, wherein overlap width of the first overlap portion and overlap width of the second overlap portion are equal to each other, a gate electrode including a first electrode portion covering upper and side surfaces of the third semiconductor portion and a second electrode portion formed in the depression, and a gate insulating film interposed between the semiconductor structure and the gate electrode.
摘要翻译：公开了一种半导体器件，包括具有凹陷的基底绝缘膜，半导体结构，其包括具有形成在下面的绝缘膜上的部分的第一半导体部分和与凹部重叠的第一重叠部分，第二半导体部分形成有部分在第一半导体部分和第二半导体部分之间并且具有设置在该凹部之上的部分的第三半导体部分，其中第一重叠部分的重叠宽度和第二重叠部分的重叠宽度第二重叠部分彼此相等，栅电极包括覆盖第三半导体部分的上表面和第二表面的第一电极部分和形成在凹陷部中的第二电极部分，以及插入在半导体结构和栅极之间的栅极绝缘膜电极。

2. 发明申请

US20060084215A1 Semiconductor device and method for manufacturing the same 审中-公开
公开(公告)号：US20060084215A1
公开(公告)日：2006-04-20
申请号：US11289279
申请日：2005-11-30
申请人： Katsuhiko Hieda , Kazuya Matsuzawa , Daisuke Hagishima
发明人： Katsuhiko Hieda , Kazuya Matsuzawa , Daisuke Hagishima
IPC分类号： H01L21/8234
CPC分类号： H01L29/785 , H01L27/108 , H01L27/10814 , H01L27/10829 , H01L27/10873 , H01L27/10879 , H01L27/1211 , H01L29/42392 , H01L29/66545 , H01L29/66795 , H01L29/7854 , H01L29/78648
摘要： Disclosed is a semiconductor device comprising an underlying insulating film having a depression, a semiconductor structure which includes a first semiconductor portion having a portion formed on the underlying insulating film and a first overlap portion which overlaps the depression, a second semiconductor portion having a portion formed on the underlying insulating film and a second overlap portion which overlaps the depression, and a third semiconductor portion disposed between the first and second semiconductor portions and having a portion disposed above the depression, wherein overlap width of the first overlap portion and overlap width of the second overlap portion are equal to each other, a gate electrode including a first electrode portion covering upper and side surfaces of the third semiconductor portion and a second electrode portion formed in the depression, and a gate insulating film interposed between the semiconductor structure and the gate electrode.

3. 发明申请

US20050121703A1 Semiconductor device and method for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050121703A1
公开(公告)日：2005-06-09
申请号：US10874732
申请日：2004-06-24
申请人： Katsuhiko Hieda , Kazuya Matsuzawa , Daisuke Hagishima
发明人： Katsuhiko Hieda , Kazuya Matsuzawa , Daisuke Hagishima
IPC分类号： H01L29/423 , H01L21/336 , H01L21/8242 , H01L27/108 , H01L27/12 , H01L29/49 , H01L29/786 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/785 , H01L27/108 , H01L27/10814 , H01L27/10829 , H01L27/10873 , H01L27/10879 , H01L27/1211 , H01L29/42392 , H01L29/66545 , H01L29/66795 , H01L29/7854 , H01L29/78648
摘要： Disclosed is a semiconductor device comprising an underlying insulating film having a depression, a semiconductor structure which includes a first semiconductor portion having a portion formed on the underlying insulating film and a first overlap portion which overlaps the depression, a second semiconductor portion having a portion formed on the underlying insulating film and a second overlap portion which overlaps the depression, and a third semiconductor portion disposed between the first and second semiconductor portions and having a portion disposed above the depression, wherein overlap width of the first overlap portion and overlap width of the second overlap portion are equal to each other, a gate electrode including a first electrode portion covering upper and side surfaces of the third semiconductor portion and a second electrode portion formed in the depression, and a gate insulating film interposed between the semiconductor structure and the gate electrode.
摘要翻译：公开了一种半导体器件，包括具有凹陷的基底绝缘膜，半导体结构，其包括具有形成在下面的绝缘膜上的部分的第一半导体部分和与凹部重叠的第一重叠部分，第二半导体部分形成有部分在第一半导体部分和第二半导体部分之间并且具有设置在该凹部之上的部分的第三半导体部分，其中第一重叠部分的重叠宽度和第二重叠部分的重叠宽度第二重叠部分彼此相等，栅电极包括覆盖第三半导体部分的上表面和第二表面的第一电极部分和形成在凹陷部中的第二电极部分，以及插入在半导体结构和栅极之间的栅极绝缘膜电极。

4. 发明授权

US07224019B2 Semiconductor device and method of manufacture thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07224019B2
公开(公告)日：2007-05-29
申请号：US11064453
申请日：2005-02-24
申请人： Katsuhiko Hieda , Daisuke Hagishima
发明人： Katsuhiko Hieda , Daisuke Hagishima
IPC分类号： H01L27/12 , G11C11/34
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L29/42332 , H01L29/7851 , H01L29/7881
摘要： A semiconductor device comprises a semiconductor substrate, an electrically rewritable semiconductor memory cell provided on the semiconductor substrate, the memory cell comprising an island semiconductor portion provided on the surface of the semiconductor substrate or above the semiconductor substrate, a first insulating film provided on a top surface of the island semiconductor portion, a second insulating film provided on a side surface of the island semiconductor portion and being smaller in thickness than the first insulating film, and a charge storage layer provided on the side surface of the island semiconductor portion with the second insulating film interposed therebetween and on a side surface of the first insulating film, a third insulating film provided on the charge storage layer, and a control gate electrode provided on the third insulating film.
摘要翻译：半导体器件包括半导体衬底，设置在半导体衬底上的电可重写半导体存储单元，所述存储单元包括设置在半导体衬底的表面上或半导体衬底上的岛状半导体部分，设置在顶部上的第一绝缘膜岛半导体部分的表面，设置在岛状半导体部分的侧表面上并且厚度小于第一绝缘膜的第二绝缘膜，以及设置在岛半导体部分的侧表面上的电荷存储层，第二绝缘膜具有第二绝缘膜绝缘膜和第一绝缘膜的侧面，设置在电荷存储层上的第三绝缘膜和设置在第三绝缘膜上的控制栅电极。

5. 发明申请

US20070287245A1 Semiconductor device and method of manufacture thereof 失效
公开(公告)号：US20070287245A1
公开(公告)日：2007-12-13
申请号：US11790391
申请日：2007-04-25
申请人： Katsuhiko Hieda , Daisuke Hagishima
发明人： Katsuhiko Hieda , Daisuke Hagishima
IPC分类号： H01L21/8238
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L29/42332 , H01L29/7851 , H01L29/7881
摘要： A semiconductor device comprises a semiconductor substrate, an electrically rewritable semiconductor memory cell provided on the semiconductor substrate, the memory cell comprising an island semiconductor portion provided on the surface of the semiconductor substrate or above the semiconductor substrate, a first insulating film provided on a top surface of the island semiconductor portion, a second insulating film provided on a side surface of the island semiconductor portion and being smaller in thickness than the first insulating film, and a charge storage layer provided on the side surface of the island semiconductor portion with the second insulating film interposed therebetween and on a side surface of the first insulating film, a third insulating film provided on the charge storage layer, and a control gate electrode provided on the third insulating film.

6. 发明授权

US07579241B2 Semiconductor device and method of manufacture thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07579241B2
公开(公告)日：2009-08-25
申请号：US11790391
申请日：2007-04-25
申请人： Katsuhiko Hieda , Daisuke Hagishima
发明人： Katsuhiko Hieda , Daisuke Hagishima
IPC分类号： H01L21/8247
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L29/42332 , H01L29/7851 , H01L29/7881
摘要： A semiconductor device comprises a semiconductor substrate, an electrically rewritable semiconductor memory cell provided on the semiconductor substrate, the memory cell comprising an island semiconductor portion provided on the surface of the semiconductor substrate or above the semiconductor substrate, a first insulating film provided on a top surface of the island semiconductor portion, a second insulating film provided on a side surface of the island semiconductor portion and being smaller in thickness than the first insulating film, and a charge storage layer provided on the side surface of the island semiconductor portion with the second insulating film interposed therebetween and on a side surface of the first insulating film, a third insulating film provided on the charge storage layer, and a control gate electrode provided on the third insulating film.
摘要翻译：半导体器件包括半导体衬底，设置在半导体衬底上的电可重写半导体存储单元，所述存储单元包括设置在半导体衬底的表面上或半导体衬底上的岛半导体部分，设置在顶部的第一绝缘膜岛半导体部分的表面，设置在岛状半导体部分的侧表面上并且厚度小于第一绝缘膜的第二绝缘膜，以及设置在岛半导体部分的侧表面上的电荷存储层，第二绝缘膜具有第二绝缘膜绝缘膜和第一绝缘膜的侧面，设置在电荷存储层上的第三绝缘膜和设置在第三绝缘膜上的控制栅电极。

7. 发明申请

US20050226047A1 Semiconductor device and method of manufacture thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050226047A1
公开(公告)日：2005-10-13
申请号：US11064453
申请日：2005-02-24
申请人： Katsuhiko Hieda , Daisuke Hagishima
发明人： Katsuhiko Hieda , Daisuke Hagishima
IPC分类号： H01L21/8247 , G11C11/34 , G11C16/04 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/115 , G11C16/0483 , H01L27/11519 , H01L27/11521 , H01L27/11524 , H01L29/42332 , H01L29/7851 , H01L29/7881
摘要： A semiconductor device comprises a semiconductor substrate, an electrically rewritable semiconductor memory cell provided on the semiconductor substrate, the memory cell comprising an island semiconductor portion provided on the surface of the semiconductor substrate or above the semiconductor substrate, a first insulating film provided on a top surface of the island semiconductor portion, a second insulating film provided on a side surface of the island semiconductor portion and being smaller in thickness than the first insulating film, and a charge storage layer provided on the side surface of the island semiconductor portion with the second insulating film interposed therebetween and on a side surface of the first insulating film, a third insulating film provided on the charge storage layer, and a control gate electrode provided on the third insulating film.
摘要翻译：半导体器件包括半导体衬底，设置在半导体衬底上的电可重写半导体存储单元，所述存储单元包括设置在半导体衬底的表面上或半导体衬底上的岛半导体部分，设置在顶部的第一绝缘膜岛半导体部分的表面，设置在岛状半导体部分的侧表面上并且厚度小于第一绝缘膜的第二绝缘膜，以及设置在岛半导体部分的侧表面上的电荷存储层，第二绝缘膜具有第二绝缘膜绝缘膜和第一绝缘膜的侧面，设置在电荷存储层上的第三绝缘膜和设置在第三绝缘膜上的控制栅电极。

8. 发明申请

US20100250223A1 SEMICONDUCTOR CIRCUIT DETERIORATION SIMULATION METHOD AND COMPUTER PROGRAM MEDIUM 审中-公开
标题翻译：半导体电路测量模拟方法和计算机程序介质
公开(公告)号：US20100250223A1
公开(公告)日：2010-09-30
申请号：US12652434
申请日：2010-01-05
申请人： Daisuke Hagishima , Kazuya Matsuzawa , Yuichiro Mitani , Shigeto Fukatsu , Kouichirou Inoue
发明人： Daisuke Hagishima , Kazuya Matsuzawa , Yuichiro Mitani , Shigeto Fukatsu , Kouichirou Inoue
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A semiconductor circuit deterioration simulation method for a circuit including MOSFETs includes inserting a dynamic voltage source associated with a fluctuation in voltage/current characteristics into each gate terminal of a plurality of MOSFETs in series, calculating dynamic deterioration amounts of the plurality of MOSFETs by performing circuit simulation and calculating a dynamic deterioration amount, and repeating the above processing to perform the circuit deterioration simulation over the long term.
摘要翻译：包括MOSFET的电路的半导体电路劣化模拟方法包括将与电压/电流特性波动相关联的动态电压源串联插入到多个MOSFET的每个栅极端子中，通过执行电路来计算多个MOSFET的动态劣化量模拟并计算动态劣化量，并且重复上述处理以长期执行电路恶化模拟。

9. 发明授权

US08525251B2 Nonvolatile programmable logic switch 失效
标题翻译：非易失性可编程逻辑开关
公开(公告)号：US08525251B2
公开(公告)日：2013-09-03
申请号：US13221292
申请日：2011-08-30
申请人： Daisuke Hagishima , Atsuhiro Kinoshita , Kazuya Matsuzawa , Kazutaka Ikegami , Yoshifumi Nishi
发明人： Daisuke Hagishima , Atsuhiro Kinoshita , Kazuya Matsuzawa , Kazutaka Ikegami , Yoshifumi Nishi
IPC分类号： H01L29/792
CPC分类号： H01L29/7881 , G11C16/0408 , H01L27/1052 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L27/11807 , H01L29/66825
摘要： A nonvolatile programmable logic switch according to an embodiment includes: a memory cell transistor including: a first source region and a first drain region of a second conductivity type formed at a distance from each other in a first semiconductor region of a first conductivity type; a first insulating film, a charge storage film, a second insulating film, and a control gate stacked in this order and formed on the first semiconductor region between the first source region and the first drain region; a pass transistor including: a second source region and a second drain region of a second conductivity type formed at a distance from each other in a second semiconductor region of the first conductivity type; a third insulating film, a gate electrode stacked in this order and formed on the second semiconductor region between the second source region and the second drain region, the gate electrode being electrically connected to the first drain region; and an electrode for applying a substrate bias to the first and second semiconductor regions.
摘要翻译：根据实施例的非易失性可编程逻辑开关包括：存储单元晶体管，包括：在第一导电类型的第一半导体区域中彼此间隔开形成的第二导电类型的第一源极区域和第一漏极区域; 第一绝缘膜，电荷存储膜，第二绝缘膜和控制栅极，并且形成在第一源极区域和第一漏极区域之间的第一半导体区域上; 传输晶体管，包括：在第一导电类型的第二半导体区域中彼此成一定距离地形成的第二导电类型的第二源极区域和第二漏极区域; 第三绝缘膜，栅极电极，并且形成在第二源极区域和第二漏极区域之间的第二半导体区域上，栅极电连接到第一漏极区域; 以及用于将衬底偏压施加到第一和第二半导体区域的电极。

10. 发明申请

US20120026779A1 NONVOLATILE MEMORIES AND RECONFIGURABLE CIRCUITS 有权
标题翻译：非易失性存储器和可重新配置的电路
公开(公告)号：US20120026779A1
公开(公告)日：2012-02-02
申请号：US13213871
申请日：2011-08-19
申请人： Kazutaka Ikegami , Atsuhiro Kinoshita , Daisuke Hagishima
发明人： Kazutaka Ikegami , Atsuhiro Kinoshita , Daisuke Hagishima
IPC分类号： G11C11/00
CPC分类号： G11C13/0002 , G11C2213/72 , G11C2213/77 , G11C2213/79 , H01L27/2409 , H01L27/2436 , H01L45/146 , H03K19/1776
摘要： A nonvolatile memory according to an embodiment includes at least one memory cell including: a variable resistance memory comprising one end connected to a first terminal, and the other end connected to a second terminal, a drive voltage being applied to the first terminal; and a diode comprising a cathode connected to the second terminal, and an anode connected to a third terminal, a ground potential being applied to the third terminal. An output of the memory cell is output from the second terminal, the output of the memory cell depends on a resistance state of the variable resistance memory.
摘要翻译：根据实施例的非易失性存储器包括至少一个存储单元，包括：可变电阻存储器，包括连接到第一端子的一端，并且另一端连接到第二端子，施加到第一端子的驱动电压; 以及二极管，包括连接到第二端子的阴极和连接到第三端子的阳极，将地电位施加到第三端子。存储单元的输出从第二端输出，存储单元的输出取决于可变电阻存储器的电阻状态。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式