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1. 发明授权

US5974539A Three input arithmetic logic unit with shifter and mask generator 失效
标题翻译：三输入算术逻辑单元，带移位器和掩码发生器
公开(公告)号：US5974539A
公开(公告)日：1999-10-26
申请号：US160298
申请日：1993-11-30
申请人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Phillip Moyse
发明人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Phillip Moyse
IPC分类号： G06F5/01 , G06F9/302 , G06F9/315
CPC分类号： G06F9/30167 , G06F5/015
摘要： A three input arithmetic logic unit (230) generates a combination of the three inputs that is selected by a function signal. The second input signal comes from a controllable shifter (235). The shift amount is a default shift amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the shifter (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the shift amount. The output of the shift (235) may be stored independently of the arithmetic logic unit (230) result. The third input signal comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). One preferred form of the mask has a number of right justified 1's corresponding to a mask input signal. This mask input signal may be the default shift amount or a predetermined number of the least significant bits of the third input signal as selected by a multiplexer. A second preferred form of the mask is selected one of the left most 1, the right most 1, the left most bit change or the right most bit change of a predetermined set of the least significant bits of data recalled from a data register.
摘要翻译：三输入算术逻辑单元（230）产生由功能信号选择的三个输入的组合。第二输入信号来自可控移位器（235）。移位量是存储在特殊数据寄存器中的默认偏移量，是从数据寄存器或零调用的预定数据位组。一个恒定源（236）连接到移位器（235）以提供“1”的多位数字信号。这允许产生形式2N的第二输入信号，其中N是移位量。移位（235）的输出可以独立于算术逻辑单元（230）结果存储。第三输入信号来自多路复用器（233），其在指定的指令字段，从数据寄存器调用的数据或从掩码生成器输入的掩码（239）之间进行选择。掩模的一个优选形式具有对应于掩模输入信号的许多右对齐1。该掩模输入信号可以是由多路复用器选择的第三输入信号的默认偏移量或预定数量的最低有效位。选择掩模的第二优选形式是从数据寄存器回调的数据的最低有效位的预定集合的最左1，最右1，最左位变化或最右位变化中的一个。

2. 发明授权

US5742538A Long instruction word controlling plural independent processor operations 失效
公开(公告)号：US5742538A
公开(公告)日：1998-04-21
申请号：US632785
申请日：1996-04-15
申请人： Karl M. Guttag , Christopher J. Read , Keith Balmer
发明人： Karl M. Guttag , Christopher J. Read , Keith Balmer
IPC分类号： G06F7/52 , G06F7/57 , G06F9/30 , G06F9/302 , G06F9/315 , G06F9/38
CPC分类号： G06F7/53 , G06F7/57 , G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/30145 , G06F9/30167 , G06F9/3851 , G06F9/3853 , G06F9/3867 , G06F9/3885 , G06F2207/382
摘要： A data processing apparatus including a multiplier unit forming a product from L bits of each two data buses of N bits each N is greater than L. The multiplier forms a N bit output having a first portion which is the L most significant bits of the of product and a second portion which is M other bits not including the L least significant bits of the product, where N is the sum of M and L. In the preferred embodiment the M other bits are derived from other bits of the two input data busses, such as the M other bits of the first input data bus. An arithmetic logic unit performs parallel operations (addition, subtraction, Boolean functions) controlled by the same instructions. This arithmetic logic unit is divisible into a selected number of sections for performing identical operations on independent sections of its inputs. The multiplier unit may form dual products from separate parts of the input data. A single instruction controlling both the multiplier unit and the arithmetic logic unit permits addition of dual products. The dual products are temporarily stored in a data register permitting the multiply and add operations to be pipelined. The dual products are formed in one data word and added by a rotate/mask and add operation in a three input arithmetic unit.

3. 发明授权

US5640578A Arithmetic logic unit having plural independent sections and register storing resultant indicator bit from every section 失效
标题翻译：具有多个独立部分的算术逻辑单元和从每个部分存储结果指示符位的寄存器
公开(公告)号：US5640578A
公开(公告)日：1997-06-17
申请号：US158742
申请日：1993-11-30
申请人： Keith Balmer , Nicholas Ing-Simmons , Karl M. Guttag , Robert J. Gove , Jeremiah E. Golston , Christopher J. Read , Sydney W. Poland
发明人： Keith Balmer , Nicholas Ing-Simmons , Karl M. Guttag , Robert J. Gove , Jeremiah E. Golston , Christopher J. Read , Sydney W. Poland
IPC分类号： G06F3/153 , G06F7/575 , G06F9/302 , G06F9/318 , G06F9/32 , G06F12/08 , G06T1/00 , G06T1/20 , G06T11/00 , G09G5/39 , H04N1/387 , G06F7/38 , G06F7/50
CPC分类号： G06F7/575 , G06F9/30014 , G06F9/30036 , G06F9/30094 , G06F9/30189 , G06F9/30192 , G06F2207/382 , G06F2207/3828 , G06F7/49905
摘要： An arithmetic logic unit (230) may be divided into a plurality of independent sections (301, 302, 303, 340). A bit zero of carry status signal corresponding to each section that is stored in a flags register (211), which preferably includes more bits than the maximum number of sections of the arithmetic logic unit (230). New status signals may overwrite the previous status signals or rotate the stored bits and store the new status signals. A status register (210) stores a size indicator that determines the a number of sections of the arithmetic logic unit (230). A status detector has a zero detector (321, 322, 323, 324) for each elementary section (301, 302, 303, 304) of the arithmetic logic unit (230). When there are fewer than the maximum number of sections, these zero signals are ANDed (331, 332, 341). A multiplexer couples the carry-out of an elementary (311, 312, 313, 314) to the carry-in of an adjacent elementary section (301, 302, 303, 304) or not depending on the selected number of sections. The status detector supplies carry outs from each elementary section (301, 302, 303, 304) not coupled to an adjacent elementary section (301, 302, 303, 304) to the flags register (211). Status signals stored in the flags register (211) influence the combination of inputs formed by the arithmetic logic unit (230) within corresponding sections. An expand circuit (238) expands selected bits of flags register (211) to form a third input to a three input arithmetic logic unit (230).
摘要翻译：算术逻辑单元（230）可以被划分为多个独立部分（301,302,303,340）。对应于存储在标志寄存器（211）中的每个部分的进位状态信号的位零，其优选地包括比算术逻辑单元（230）的最大部分数量多的位。新的状态信号可以覆盖先前的状态信号或旋转存储的比特并存储新的状态信号。状态寄存器（210）存储确定算术逻辑单元（230）的段数的大小指示符。状态检测器对于算术逻辑单元（230）的每个基本部分（301,302,303,304）具有零检测器（321,322,323,324）。当小于最大数量的部分时，这些零信号为“与”（331,332,341）。多路复用器将基本（311,312,313,314）的进位输出耦合到相邻基本部分（301,302,303,304）的进位，或者不依赖于所选择的部分数量。状态检测器从没有耦合到相邻基本部分（301,302,303,304）的每个基本部分（301,302,303,304）提供进位到标志寄存器（211）。存储在标志寄存器（211）中的状态信号影响由相应部分内的算术逻辑单元（230）形成的输入的组合。扩展电路（238）扩展标志寄存器（211）的所选位以形成三输入算术逻辑单元（230）的第三输入。

4. 发明授权

US5651127A Guided transfers with variable stepping 失效
标题翻译：引导传输与可变步进
公开(公告)号：US5651127A
公开(公告)日：1997-07-22
申请号：US209123
申请日：1994-03-08
申请人： Robert J. Gove , Karl M. Guttag , Keith Balmer , Christopher J. Read , Iain Robertson , Nicholas Ing Simmons
发明人： Robert J. Gove , Karl M. Guttag , Keith Balmer , Christopher J. Read , Iain Robertson , Nicholas Ing Simmons
IPC分类号： G06F9/345 , G06F9/38 , G06F13/28 , G09G5/393 , G06F91/26 , G06F9/34 , G06F12/00 , G06F12/14
CPC分类号： G09G5/393 , G06F13/28 , G06F9/345 , G06F9/3879
摘要： This invention is a manner of control of the addresses of memory accesses. The data processing device of this invention includes a memory, a control circuit, a guide table and an address generating circuit. The control circuit receives a packet transfer request and packet transfer parameters. The packet transfer parameters include a start address, a number of guide table entries and a table pointer. The guide table includes guide table entries, each guide table entry having an address value and dimension values defining a block of addresses. The table pointer initially points to a first guide table entry in the guide table. The address generating circuit forms a set of block of addresses for memory access corresponding to each guide table entry, having a start address from a predetermined combination of the start address and the address value of the guide table entry. The block of addresses are formed from the dimension values. Following the memory accesses, the address generating circuit updates the table pointer to point to a next entry in the guide table. The address generating circuit may optionally form the predetermined combination of starting address and address value of guide table entry by adding the address value to the prior block starting address or by adding the guide table value to the starting address. The memory access may be a memory read from the block of addresses or a memory write to the block of addresses. In the preferred embodiment, memory, a data processor and a data transfer controller performing the above memory accesses is constructed in a single semiconductor chip. The data transfer controller may access external memory in the same manner as on-chip memory.
摘要翻译：本发明是对存储器存取地址的控制方式。本发明的数据处理装置包括存储器，控制电路，引导表和地址产生电路。控制电路接收分组传送请求和分组传送参数。分组传送参数包括起始地址，指导表条目的数目和表指针。指南表包括指南表条目，每个指南表条目具有定义地址块的地址值和维度值。表指针最初指向指南表中的第一个指南表项。地址生成电路形成与每个引导表条目相对应的用于存储器访问的地址块集合，具有来自引导表条目的起始地址和地址值的预定组合的起始地址。地址块由维度值形成。在存储器访问之后，地址产生电路更新表指针以指向指南表中的下一条目。地址产生电路可以通过将地址值添加到先前块开始地址或通过将引导表值添加到起始地址来可选地形成指南表入口的起始地址和地址值的预定组合。存储器访问可以是从地址块读取的存储器或写入地址块的存储器。在优选实施例中，执行上述存储器访问的存储器，数据处理器和数据传输控制器被构造在单个半导体芯片中。数据传输控制器可以以与片上存储器相同的方式访问外部存储器。

5. 发明授权

US06370558B1 Long instruction word controlling plural independent processor operations 有权
标题翻译：长指令字控制多个独立处理器操作
公开(公告)号：US06370558B1
公开(公告)日：2002-04-09
申请号：US09678746
申请日：2000-10-03
申请人： Karl M. Guttag , Christopher J. Read , Keith Balmer
发明人： Karl M. Guttag , Christopher J. Read , Keith Balmer
IPC分类号： G06F1500
CPC分类号： G06F7/53 , G06F7/57 , G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/30145 , G06F9/30167 , G06F9/3851 , G06F9/3853 , G06F9/3867 , G06F9/3885 , G06F2207/382
摘要： A data processing apparatus including a multiplier unit forming a product from L bits of each two data buses of N bits each N is greater than L. The multiplier forms a N bit output having a first portion which is the L most significant bits of the of product and a second portion which is M other bits not including the L least significant bits of the product, where N is the sum of M and L. In the preferred embodiment the M other bits are derived from other bits of the two input data busses, such as the M other bits of the first input data bus. An arithmetic logic unit performs parallel operations (addition, subtraction, Boolean functions) controlled by the same instructions. This arithmetic logic unit is divisible into a selected number of sections for performing identical operations on independent sections of its inputs. The multiplier unit may form dual products from separate parts of the input data. A single instruction controlling both the multiplier unit and the arithmetic logic unit permits addition of dual products. The dual products are temporarily stored in a data register permitting the multiply and add operations to be pipelined. The dual products are formed in one data word and added by a rotate/mask and add operation in a three input arithmetic unit.
摘要翻译：一种数据处理装置，包括形成从每个N个N位的每两个数据总线的L位产生的乘积的乘数单元，其大于L.乘法器形成具有第一部分的N位输出，第一部分是产品和第二部分，M是不包括乘积的L个最低有效位的M个其他位，其中N是M和L的和。在优选实施例中，M个其他位从两个输入数据总线的其他位导出，例如第一输入数据总线的M个其他位。算术逻辑单元执行由相同指令控制的并行操作（加法，减法，布尔函数）。该算术逻辑单元可分为选定数量的部分，用于在其输入的独立部分上执行相同的操作。乘数单元可以从输入数据的单独部分形成双重产品。控制乘法器单元和算术逻辑单元的单个指令允许添加双重产品。双重产品临时存储在数据寄存器中，允许进行流水线加法操作。双重产品形成一个数据字，并通过旋转/掩码添加，并在三输入算术单元中添加操作。

6. 发明授权

US6116768A Three input arithmetic logic unit with barrel rotator 失效
标题翻译：三输入算术逻辑单元，带桶旋转器
公开(公告)号：US6116768A
公开(公告)日：2000-09-12
申请号：US160299
申请日：1993-11-30
申请人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Phillip Moyse
发明人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Phillip Moyse
IPC分类号： G06F5/01 , G06F9/302 , G06F9/305 , G06F9/308 , G06F9/315 , G06F9/32 , G06F12/02 , G06F7/36
CPC分类号： G06F9/30014 , G06F12/0284 , G06F5/015 , G06F9/30018 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30094 , G06F9/30167 , G06F9/325
摘要： A data processing apparatus includes a three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal comes from a controllable barrel rotator (235). The rotate amount is a default rotate amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the barrel rotator (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the rotate amount. The output of the barrel rotator (235) may be stored independently of the arithmetic logic unit (230) result. In the preferred embodiment of this invention, the three input arithmetic logic unit (230) is embodied in a data processor circuits as a part of a multiprocessor integrated circuit (100) used in image processing.
摘要翻译：数据处理装置包括产生由功能信号选择的三个输入的组合的三输入算术逻辑单元（230）。数据寄存器（200）存储三个数据输入和算术逻辑单元输出。第二输入信号来自可控筒旋转器（235）。旋转量是存储在特殊数据寄存器中的默认旋转量，从数据寄存器或零调用的预定数据位组。恒定源（236）连接到筒旋转器（235）以提供“1”的多位数字信号。这允许产生形式2N的第二输入信号，其中N是旋转量。桶旋转器（235）的输出可以独立于算术逻辑单元（230）的结果存储。在本发明的优选实施例中，三输入算术逻辑单元（230）被实现为作为在图像处理中使用的多处理器集成电路（100）的一部分的数据处理器电路。

7. 发明授权

US5961635A Three input arithmetic logic unit with barrel rotator and mask generator 失效
标题翻译：三输入算术逻辑单元，带筒式旋转器和面罩发生器
公开(公告)号：US5961635A
公开(公告)日：1999-10-05
申请号：US160111
申请日：1993-11-30
申请人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Phillip Moyse
发明人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Phillip Moyse
IPC分类号： G06F5/01 , G06F7/575 , G06F7/76 , G06F9/30
CPC分类号： G06F7/764 , G06F5/01 , G06F7/575
摘要： A three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. The second input signal comes from a controllable barrel rotator (235). The rotate amount is a default rotate amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the barrel rotator (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the rotate amount. The output of the barrel rotator (235) may be stored independently of the arithmetic logic unit (230) result. The third input signal comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). One preferred form of the mask has a number of right justified 1's corresponding to a mask input signal. This mask input signal may be the default barrel rotate amount or a predetermined number of the least significant bits of a third input signal as selected by a multiplexer. A second preferred form of the mask is selected one of the left most 1, the right most 1, the left most bit change or the right most bit change of a predetermined set of the least significant bits of data recalled from a data register.
摘要翻译：三输入算术逻辑单元（230），其生成由功能信号选择的三个输入的组合。第二输入信号来自可控筒旋转器（235）。旋转量是存储在特殊数据寄存器中的默认旋转量，从数据寄存器或零调用的预定数据位组。恒定源（236）连接到筒旋转器（235）以提供“1”的多位数字信号。这允许产生形式2N的第二输入信号，其中N是旋转量。桶旋转器（235）的输出可以独立于算术逻辑单元（230）的结果存储。第三输入信号来自多路复用器（233），其在指定的指令字段，从数据寄存器调用的数据或从掩码生成器输入的掩码（239）之间进行选择。掩模的一个优选形式具有对应于掩模输入信号的许多右对齐1。该掩模输入信号可以是由多路复用器选择的默认桶旋转量或第三输入信号的预定数量的最低有效位。选择掩模的第二优选形式是从数据寄存器回调的数据的最低有效位的预定集合的最左1，最右1，最左位变化或最右位变化中的一个。

8. 发明授权

US5761726A Base address generation in a multi-processing system having plural memories with a unified address space corresponding to each processor 失效
标题翻译：在具有与每个处理器对应的统一地址空间的多个存储器的多处理系统中产生基地址
公开(公告)号：US5761726A
公开(公告)日：1998-06-02
申请号：US479981
申请日：1995-06-07
申请人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Philip Moyse
发明人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Philip Moyse
IPC分类号： G06F5/01 , G06F9/302 , G06F9/305 , G06F9/308 , G06F9/315 , G06F9/32 , G06F12/02 , G06F12/00
CPC分类号： G06F9/30014 , G06F12/0284 , G06F5/015 , G06F9/30018 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30094 , G06F9/30167 , G06F9/325
摘要： A multi-processing system includes a plurality of memories and a plurality of processors. Each of the memories has a unique addressable memory portion of a single memory address space. Each processors has a predetermined plurality of corresponding memories. These corresponding memories have a corresponding base address within said single memory address space The processors generate addresses for read/write access to data stored within said plurality of memories in accordance with received instructions. A switch matrix connected to the memories and the processors responds to an address generated by a processor to selectively route data between that processor and a memories whose unique addressable memory portion encompasses that address. A base address instruction executing on any one of the processors generates the base address corresponding to that processor. The base address preferably is substituted for the contents of a base address register in an address unit including a set of base address registers, a set of index address registers and a full adder.
摘要翻译：多处理系统包括多个存储器和多个处理器。每个存储器具有单个存储器地址空间的唯一可寻址存储器部分。每个处理器具有预定的多个对应的存储器。这些相应的存储器在所述单个存储器地址空间内具有对应的基址。根据接收到的指令，处理器产生用于对存储在所述多个存储器中的数据进行读/写访问的地址。连接到存储器和处理器的开关矩阵响应由处理器产生的地址，以选择性地在该处理器与其唯一可寻址存储器部分包含该地址的存储器之间路由数据。在任一个处理器上执行的基地址指令产生与该处理器对应的基地址。基址优选地代替包括一组基地址寄存器，一组索引地址寄存器和全加器的地址单元中的基地址寄存器的内容。

9. 发明授权

US5634065A Three input arithmetic logic unit with controllable shifter and mask generator 失效
标题翻译：三输入算术逻辑单元，带可控制移位器和掩码发生器
公开(公告)号：US5634065A
公开(公告)日：1997-05-27
申请号：US475134
申请日：1995-06-07
申请人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Philip Moyse
发明人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Philip Moyse
IPC分类号： G06F5/01 , G06F7/575 , G06F7/76 , G06F7/38
CPC分类号： G06F7/764 , G06F5/01 , G06F7/575
摘要： A three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. The second input signal comes from a controllable barrel rotator (235). The rotate amount is a default rotate amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the barrel rotator (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the rotate amount. The output of the barrel rotator (235) may be stored independently of the arithmetic logic unit (230) result. The third input signal comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). One preferred form of the mask has a number of right justified 1's corresponding to a mask input signal. This mask input signal may be the default barrel rotate amount or a predetermined number of the least significant bits of a third input signal as selected by a multiplexer. A second preferred form of the mask is selected one of the left most 1, the right most 1, the left most bit change or the right most bit change of a predetermined set of the least significant bits of data recalled from a data register.
摘要翻译：三输入算术逻辑单元（230），其生成由功能信号选择的三个输入的组合。第二输入信号来自可控筒旋转器（235）。旋转量是存储在特殊数据寄存器中的默认旋转量，从数据寄存器或零调用的预定数据位组。恒定源（236）连接到筒旋转器（235）以提供“1”的多位数字信号。这允许产生形式2N的第二输入信号，其中N是旋转量。桶旋转器（235）的输出可以独立于算术逻辑单元（230）的结果存储。第三输入信号来自多路复用器（233），其在指定的指令字段，从数据寄存器调用的数据或从掩码生成器输入的掩码（239）之间进行选择。掩模的一个优选形式具有对应于掩模输入信号的许多右对齐1。该掩模输入信号可以是由多路复用器选择的默认桶旋转量或第三输入信号的预定数量的最低有效位。选择掩模的第二优选形式是从数据寄存器回调的数据的最低有效位的预定集合的最左1，最右1，最左位变化或最右位变化中的一个。

10. 发明授权

US5600847A Three input arithmetic logic unit with mask generator 失效
标题翻译：三输入算术逻辑单元与掩码发生器
公开(公告)号：US5600847A
公开(公告)日：1997-02-04
申请号：US475162
申请日：1995-06-07
申请人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Philip Moyse
发明人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Philip Moyse
IPC分类号： G06F7/57 , G06F7/38
CPC分类号： G06F7/57
摘要： A data processing apparatus includes a three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal comes from a controllable barrel rotator (235). The rotate amount is a default rotate amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the barrel rotator (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the rotate amount. The output of the barrel rotator (235) may be stored independently of the arithmetic logic unit (230) result. A controllable shifter is an alternative to the barrel rotator (235). The third input signal comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). One preferred form of the mask has a number of right justified 1's corresponding to a mask input signal. This mask input signal may be the default barrel rotate amount or a predetermined number of the least significant bits of a third input signal as selected by a multiplexer. A second preferred form of the mask is selected one of the left most 1, the right most 1, the left most bit change or the right most bit change of a predetermined set of the least significant bits of data recalled from a data register. In the preferred embodiment of this invention, the three input arithmetic logic unit (230) is embodied in a data processor circuits as a part of a multiprocessor integrated circuit (100) used in image processing.
摘要翻译：数据处理装置包括产生由功能信号选择的三个输入的组合的三输入算术逻辑单元（230）。数据寄存器（200）存储三个数据输入和算术逻辑单元输出。第二输入信号来自可控筒旋转器（235）。旋转量是存储在特殊数据寄存器中的默认旋转量，从数据寄存器或零调用的预定数据位组。恒定源（236）连接到筒旋转器（235）以提供“1”的多位数字信号。这允许产生形式2N的第二输入信号，其中N是旋转量。桶旋转器（235）的输出可以独立于算术逻辑单元（230）的结果存储。可控制的换档器是桶旋转器（235）的替代品。第三输入信号来自多路复用器（233），其在指定的指令字段，从数据寄存器调用的数据或从掩码生成器输入的掩码（239）之间进行选择。掩模的一个优选形式具有对应于掩模输入信号的许多右对齐1。该掩模输入信号可以是由多路复用器选择的默认桶旋转量或第三输入信号的预定数量的最低有效位。选择掩模的第二优选形式是从数据寄存器回调的数据的最低有效位的预定集合的最左1，最右1，最左位变化或最右位变化中的一个。在本发明的优选实施例中，三输入算术逻辑单元（230）被实现为作为在图像处理中使用的多处理器集成电路（100）的一部分的数据处理器电路。

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