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1. 发明授权

US5734880A Hardware branching employing loop control registers loaded according to status of sections of an arithmetic logic unit divided into a plurality of sections 失效
标题翻译：硬件分支采用根据划分成多个部分的算术逻辑单元的部分的状态加载的循环控制寄存器
公开(公告)号：US5734880A
公开(公告)日：1998-03-31
申请号：US480230
申请日：1995-06-07
申请人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Philip Moyse
发明人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Philip Moyse
IPC分类号： G06F5/01 , G06F9/302 , G06F9/305 , G06F9/308 , G06F9/315 , G06F9/32 , G06F12/02 , G06F15/00
CPC分类号： G06F9/30014 , G06F12/0284 , G06F5/015 , G06F9/30018 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30094 , G06F9/30167 , G06F9/325
摘要： Conditional hardware branching employs zero overhead loop logic and writing to a loop count register within a program loop. The zero overhead loop logic includes a program counter (701), loop end registers (711, 712, 713), loop start registers (721, 722, 723), loop counter registers (731, 732, 733), comparators (715, 716, 717) and loop priority logic (725). Normally the program counter (701) is incremented each cycle. The comparators (715, 716, 717) compare the address stored in the program counter (701) with respective loop end registers (711, 712, 713). If the address in the program counter (701) equals a loop end address, loop priority logic (725) decrements the loop count register and loads the program counter with the loop start address in loop start register. Hardware looping involves loading a loop count register during program loop operation. An arithmetic logic unit operation generates a status bit loaded into a status register or is split into sections and generates a status bit for each section stored in a multiple flags register (211) used to load the loop. count register. If this is zero then the loop priority logic reloads the program counter (701) with the loop start address and repeats the loop. If this is nonzero, program counter (701) may increment normally or will be loaded with the loop start address of a higher priority loop.
摘要翻译：条件硬件分支采用零开销循环逻辑并写入程序循环内的循环计数寄存器。零开销循环逻辑包括程序计数器（701），循环结束寄存器（711,712,713），循环开始寄存器（721,722,723），循环计数器寄存器（731,732,733），比较器（715， 716,717）和循环优先级逻辑（725）。通常，每个周期递增程序计数器（701）。比较器（715,716,717）将存储在程序计数器（701）中的地址与相应的循环结束寄存器（711,712,713）进行比较。如果程序计数器（701）中的地址等于循环结束地址，则循环优先级逻辑（725）递减循环计数寄存器，并加载循环起始寄存器中循环起始地址的程序计数器。硬件循环涉及在程序循环操作期间加载循环计数寄存器。算术逻辑单元操作产生加载到状态寄存器中的状态位或分割成部分，并且生成用于加载循环的多标志寄存器（211）中存储的每个部分的状态位。计数寄存器如果这是零，则循环优先级逻辑使用循环起始地址重新加载程序计数器（701）并重复循环。如果这是非零的，则程序计数器（701）可以正常地增加或将加载较高优先级循环的循环起始地址。

2. 发明授权

US5974539A Three input arithmetic logic unit with shifter and mask generator 失效
标题翻译：三输入算术逻辑单元，带移位器和掩码发生器
公开(公告)号：US5974539A
公开(公告)日：1999-10-26
申请号：US160298
申请日：1993-11-30
申请人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Phillip Moyse
发明人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Phillip Moyse
IPC分类号： G06F5/01 , G06F9/302 , G06F9/315
CPC分类号： G06F9/30167 , G06F5/015
摘要： A three input arithmetic logic unit (230) generates a combination of the three inputs that is selected by a function signal. The second input signal comes from a controllable shifter (235). The shift amount is a default shift amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the shifter (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the shift amount. The output of the shift (235) may be stored independently of the arithmetic logic unit (230) result. The third input signal comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). One preferred form of the mask has a number of right justified 1's corresponding to a mask input signal. This mask input signal may be the default shift amount or a predetermined number of the least significant bits of the third input signal as selected by a multiplexer. A second preferred form of the mask is selected one of the left most 1, the right most 1, the left most bit change or the right most bit change of a predetermined set of the least significant bits of data recalled from a data register.
摘要翻译：三输入算术逻辑单元（230）产生由功能信号选择的三个输入的组合。第二输入信号来自可控移位器（235）。移位量是存储在特殊数据寄存器中的默认偏移量，是从数据寄存器或零调用的预定数据位组。一个恒定源（236）连接到移位器（235）以提供“1”的多位数字信号。这允许产生形式2N的第二输入信号，其中N是移位量。移位（235）的输出可以独立于算术逻辑单元（230）结果存储。第三输入信号来自多路复用器（233），其在指定的指令字段，从数据寄存器调用的数据或从掩码生成器输入的掩码（239）之间进行选择。掩模的一个优选形式具有对应于掩模输入信号的许多右对齐1。该掩模输入信号可以是由多路复用器选择的第三输入信号的默认偏移量或预定数量的最低有效位。选择掩模的第二优选形式是从数据寄存器回调的数据的最低有效位的预定集合的最左1，最右1，最左位变化或最右位变化中的一个。

3. 发明授权

US5640578A Arithmetic logic unit having plural independent sections and register storing resultant indicator bit from every section 失效
标题翻译：具有多个独立部分的算术逻辑单元和从每个部分存储结果指示符位的寄存器
公开(公告)号：US5640578A
公开(公告)日：1997-06-17
申请号：US158742
申请日：1993-11-30
申请人： Keith Balmer , Nicholas Ing-Simmons , Karl M. Guttag , Robert J. Gove , Jeremiah E. Golston , Christopher J. Read , Sydney W. Poland
发明人： Keith Balmer , Nicholas Ing-Simmons , Karl M. Guttag , Robert J. Gove , Jeremiah E. Golston , Christopher J. Read , Sydney W. Poland
IPC分类号： G06F3/153 , G06F7/575 , G06F9/302 , G06F9/318 , G06F9/32 , G06F12/08 , G06T1/00 , G06T1/20 , G06T11/00 , G09G5/39 , H04N1/387 , G06F7/38 , G06F7/50
CPC分类号： G06F7/575 , G06F9/30014 , G06F9/30036 , G06F9/30094 , G06F9/30189 , G06F9/30192 , G06F2207/382 , G06F2207/3828 , G06F7/49905
摘要： An arithmetic logic unit (230) may be divided into a plurality of independent sections (301, 302, 303, 340). A bit zero of carry status signal corresponding to each section that is stored in a flags register (211), which preferably includes more bits than the maximum number of sections of the arithmetic logic unit (230). New status signals may overwrite the previous status signals or rotate the stored bits and store the new status signals. A status register (210) stores a size indicator that determines the a number of sections of the arithmetic logic unit (230). A status detector has a zero detector (321, 322, 323, 324) for each elementary section (301, 302, 303, 304) of the arithmetic logic unit (230). When there are fewer than the maximum number of sections, these zero signals are ANDed (331, 332, 341). A multiplexer couples the carry-out of an elementary (311, 312, 313, 314) to the carry-in of an adjacent elementary section (301, 302, 303, 304) or not depending on the selected number of sections. The status detector supplies carry outs from each elementary section (301, 302, 303, 304) not coupled to an adjacent elementary section (301, 302, 303, 304) to the flags register (211). Status signals stored in the flags register (211) influence the combination of inputs formed by the arithmetic logic unit (230) within corresponding sections. An expand circuit (238) expands selected bits of flags register (211) to form a third input to a three input arithmetic logic unit (230).
摘要翻译：算术逻辑单元（230）可以被划分为多个独立部分（301,302,303,340）。对应于存储在标志寄存器（211）中的每个部分的进位状态信号的位零，其优选地包括比算术逻辑单元（230）的最大部分数量多的位。新的状态信号可以覆盖先前的状态信号或旋转存储的比特并存储新的状态信号。状态寄存器（210）存储确定算术逻辑单元（230）的段数的大小指示符。状态检测器对于算术逻辑单元（230）的每个基本部分（301,302,303,304）具有零检测器（321,322,323,324）。当小于最大数量的部分时，这些零信号为“与”（331,332,341）。多路复用器将基本（311,312,313,314）的进位输出耦合到相邻基本部分（301,302,303,304）的进位，或者不依赖于所选择的部分数量。状态检测器从没有耦合到相邻基本部分（301,302,303,304）的每个基本部分（301,302,303,304）提供进位到标志寄存器（211）。存储在标志寄存器（211）中的状态信号影响由相应部分内的算术逻辑单元（230）形成的输入的组合。扩展电路（238）扩展标志寄存器（211）的所选位以形成三输入算术逻辑单元（230）的第三输入。

4. 发明授权

US6098163A Three input arithmetic logic unit with shifter 失效
标题翻译：三输入算术逻辑单元带移位器
公开(公告)号：US6098163A
公开(公告)日：2000-08-01
申请号：US160573
申请日：1993-11-30
申请人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Phillip Moyse
发明人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Phillip Moyse
IPC分类号： G06F5/01 , G06F15/00
CPC分类号： G06F9/30167 , G06F5/015
摘要： A data processing apparatus includes a three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal comes from a controllable shifter (235). The shift amount is a default shift amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the shifter (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the shift amount. The output of the shifter (235) may be stored independently of the arithmetic logic unit (230) result. The third input signal comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). One preferred form of the mask has a number of right justified 1's corresponding to a mask input signal. This mask input signal may be the default shift amount or a predetermined number of the least significant bits of a third input signal as selected by a multiplexer. A second preferred form of the mask is selected one of the left most 1, the right most 1, the left most bit change or the right most bit change of a predetermined set of the least significant bits of data recalled from a data register. In the preferred embodiment of this invention, the three input arithmetic logic unit (230) is embodied in a data processor circuits as a part of a multiprocessor integrated circuit (100) used in image processing.
摘要翻译：数据处理装置包括产生由功能信号选择的三个输入的组合的三输入算术逻辑单元（230）。数据寄存器（200）存储三个数据输入和算术逻辑单元输出。第二输入信号来自可控移位器（235）。移位量是存储在特殊数据寄存器中的默认偏移量，是从数据寄存器或零调用的预定数据位组。一个恒定源（236）连接到移位器（235）以提供“1”的多位数字信号。这允许产生形式2N的第二输入信号，其中N是移位量。移位器（235）的输出可以独立于算术逻辑单元（230）的结果存储。第三输入信号来自多路复用器（233），其在指定的指令字段，从数据寄存器调用的数据或从掩码生成器输入的掩码（239）之间进行选择。掩模的一个优选形式具有对应于掩模输入信号的许多右对齐1。该掩模输入信号可以是由多路复用器选择的第三输入信号的默认偏移量或预定数量的最低有效位。选择掩模的第二优选形式是从数据寄存器回调的数据的最低有效位的预定集合的最左1，最右1，最左位变化或最右位变化中的一个。在本发明的优选实施例中，三输入算术逻辑单元（230）被实现为作为在图像处理中使用的多处理器集成电路（100）的一部分的数据处理器电路。

5. 发明授权

US5995748A Three input arithmetic logic unit with shifter and/or mask generator 失效
标题翻译：具有移位器和/或掩码发生器的三输入算术逻辑单元
公开(公告)号：US5995748A
公开(公告)日：1999-11-30
申请号：US99727
申请日：1998-06-19
申请人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Philip Moyse
发明人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Philip Moyse
IPC分类号： G06F5/01 , G06F9/302 , G06F9/305 , G06F9/308 , G06F9/315 , G06F9/32 , G06F12/02
CPC分类号： G06F9/30014 , G06F12/0284 , G06F5/015 , G06F9/30018 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30094 , G06F9/30167 , G06F9/325
摘要： A data processing apparatus includes a three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal optionally comes from a controllable shifter (235). The shift amount is a default shift amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the shifter (235) to supply an N bit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the shift amount. The output of the shifter (235) may be stored independently of the arithmetic logic unit (230) result. The third input signal optionally comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). This mask input signal may be the default shift amount or a predetermined number of the least significant bits of a third input signal as selected by a multiplexer. In the preferred embodiment of this invention, the three input arithmetic logic unit (230) is embodied in a data processor circuits as a part of a multiprocessor integrated circuit (100) used in image processing.
摘要翻译：数据处理装置包括产生由功能信号选择的三个输入的组合的三输入算术逻辑单元（230）。数据寄存器（200）存储三个数据输入和算术逻辑单元输出。第二输入信号可选地来自可控移位器（235）。移位量是存储在特殊数据寄存器中的默认偏移量，是从数据寄存器或零调用的预定数据位组。一个恒定源（236）连接到移位器（235）以提供“1”的N位数字信号。这允许产生形式2N的第二输入信号，其中N是移位量。移位器（235）的输出可以独立于算术逻辑单元（230）的结果存储。第三输入信号可选地来自多路复用器（233），其在指令指定的立即字段，从数据寄存器调用的数据或从掩码生成器输入的掩码（239）之间进行选择。该掩模输入信号可以是由多路复用器选择的第三输入信号的默认偏移量或预定数量的最低有效位。在本发明的优选实施例中，三输入算术逻辑单元（230）被实现为作为在图像处理中使用的多处理器集成电路（100）的一部分的数据处理器电路。

6. 发明授权

US5995747A Three input arithmetic logic unit capable of performing all possible three operand boolean operations with shifter and/or mask generator 失效
标题翻译：三输入算术逻辑单元能够用移位器和/或掩码发生器执行所有可能的三个操作数布尔运算
公开(公告)号：US5995747A
公开(公告)日：1999-11-30
申请号：US794962
申请日：1997-02-04
申请人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Philip Moyse
发明人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Philip Moyse
IPC分类号： G06F5/01 , G06F9/302 , G06F9/305 , G06F9/308 , G06F9/315 , G06F9/32 , G06F12/02 , G06F7/52
CPC分类号： G06F9/30014 , G06F12/0284 , G06F5/015 , G06F9/30018 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30094 , G06F9/30167 , G06F9/325
摘要： A data processing apparatus includes a three input arithmetic logic unit (230) that generates a Boolean combination of the three inputs that is selected by a function signal. The arithmetic logic unit is capable of forming all possible Boolean combinations of the three inputs. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal comes from a controllable shifter (235). The shift amount is a default shift amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the shifter (235) to supply an N bit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the shift amount. The output of the shifter (235) may be stored independently of the arithmetic logic unit (230) result. The third input signal comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). This mask input signal may be the default shift amount or a predetermined number of the least significant bits of a third input signal as selected by a multiplexer. In the preferred embodiment of this invention, the three input arithmetic logic unit (230) is embodied in a data processor circuits as a part of a multiprocessor integrated circuit (100) used in image processing.
摘要翻译：数据处理装置包括三输入算术逻辑单元（230），其生成由功能信号选择的三个输入的布尔组合。算术逻辑单元能够形成三个输入的所有可能的布尔组合。数据寄存器（200）存储三个数据输入和算术逻辑单元输出。第二输入信号来自可控移位器（235）。移位量是存储在特殊数据寄存器中的默认偏移量，是从数据寄存器或零调用的预定数据位组。一个恒定源（236）连接到移位器（235）以提供“1”的N位数字信号。这允许产生形式2N的第二输入信号，其中N是移位量。移位器（235）的输出可以独立于算术逻辑单元（230）的结果存储。第三输入信号来自多路复用器（233），其在指定的指令字段，从数据寄存器调用的数据或从掩码生成器输入的掩码（239）之间进行选择。该掩模输入信号可以是由多路复用器选择的第三输入信号的默认偏移量或预定数量的最低有效位。在本发明的优选实施例中，三输入算术逻辑单元（230）被实现为作为在图像处理中使用的多处理器集成电路（100）的一部分的数据处理器电路。

7. 发明授权

US5696954A Three input arithmetic logic unit with shifting means at one input forming a sum/difference of two inputs logically anded with a third input logically ored with the sum/difference logically anded with an inverse of the third input 失效
标题翻译：三输入算术逻辑单元，其中一个输入处的移位装置形成两个输入的和/差逻辑地与第三输入进行逻辑运算，第三输入与和/差逻辑地与第三输入
公开(公告)号：US5696954A
公开(公告)日：1997-12-09
申请号：US486562
申请日：1995-06-07
申请人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Philip Moyse
发明人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Philip Moyse
IPC分类号： G06F5/01 , G06F9/302 , G06F9/305 , G06F9/308 , G06F9/315 , G06F9/32 , G06F12/02 , G06F17/00
CPC分类号： G06F9/30014 , G06F12/0284 , G06F5/015 , G06F9/30018 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30094 , G06F9/30167 , G06F9/325
摘要： A data processing apparatus includes a three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal comes from a controllable shifter (235). The shifter could be a left barrel rotator with wrap around or a controllable left/right shifter. The shift amount is a default shift amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the shifter (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being a left shift amount. The output of the shifter (235) may be stored independently of the arithmetic logic unit (230) result. In the preferred embodiment of this invention, the three input arithmetic logic unit (230) is embodied in a data processor circuits as a part of a multiprocessor integrated circuit (100) used in image processing.
摘要翻译：数据处理装置包括产生由功能信号选择的三个输入的组合的三输入算术逻辑单元（230）。数据寄存器（200）存储三个数据输入和算术逻辑单元输出。第二输入信号来自可控移位器（235）。换档器可以是带有环绕的左滚筒旋转器或可控制的左/右移位器。移位量是存储在特殊数据寄存器中的默认偏移量，是从数据寄存器或零调用的预定数据位组。一个恒定源（236）连接到移位器（235）以提供“1”的多位数字信号。这允许产生形式为2N的第二输入信号，其中N是左移位量。移位器（235）的输出可以独立于算术逻辑单元（230）的结果存储。在本发明的优选实施例中，三输入算术逻辑单元（230）被实现为作为在图像处理中使用的多处理器集成电路（100）的一部分的数据处理器电路。

8. 发明授权

US6116768A Three input arithmetic logic unit with barrel rotator 失效
标题翻译：三输入算术逻辑单元，带桶旋转器
公开(公告)号：US6116768A
公开(公告)日：2000-09-12
申请号：US160299
申请日：1993-11-30
申请人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Phillip Moyse
发明人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Phillip Moyse
IPC分类号： G06F5/01 , G06F9/302 , G06F9/305 , G06F9/308 , G06F9/315 , G06F9/32 , G06F12/02 , G06F7/36
CPC分类号： G06F9/30014 , G06F12/0284 , G06F5/015 , G06F9/30018 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30094 , G06F9/30167 , G06F9/325
摘要： A data processing apparatus includes a three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal comes from a controllable barrel rotator (235). The rotate amount is a default rotate amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the barrel rotator (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the rotate amount. The output of the barrel rotator (235) may be stored independently of the arithmetic logic unit (230) result. In the preferred embodiment of this invention, the three input arithmetic logic unit (230) is embodied in a data processor circuits as a part of a multiprocessor integrated circuit (100) used in image processing.
摘要翻译：数据处理装置包括产生由功能信号选择的三个输入的组合的三输入算术逻辑单元（230）。数据寄存器（200）存储三个数据输入和算术逻辑单元输出。第二输入信号来自可控筒旋转器（235）。旋转量是存储在特殊数据寄存器中的默认旋转量，从数据寄存器或零调用的预定数据位组。恒定源（236）连接到筒旋转器（235）以提供“1”的多位数字信号。这允许产生形式2N的第二输入信号，其中N是旋转量。桶旋转器（235）的输出可以独立于算术逻辑单元（230）的结果存储。在本发明的优选实施例中，三输入算术逻辑单元（230）被实现为作为在图像处理中使用的多处理器集成电路（100）的一部分的数据处理器电路。

9. 发明授权

US5961635A Three input arithmetic logic unit with barrel rotator and mask generator 失效
标题翻译：三输入算术逻辑单元，带筒式旋转器和面罩发生器
公开(公告)号：US5961635A
公开(公告)日：1999-10-05
申请号：US160111
申请日：1993-11-30
申请人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Phillip Moyse
发明人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Phillip Moyse
IPC分类号： G06F5/01 , G06F7/575 , G06F7/76 , G06F9/30
CPC分类号： G06F7/764 , G06F5/01 , G06F7/575
摘要： A three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. The second input signal comes from a controllable barrel rotator (235). The rotate amount is a default rotate amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the barrel rotator (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2.sup.N, with N being the rotate amount. The output of the barrel rotator (235) may be stored independently of the arithmetic logic unit (230) result. The third input signal comes from a multiplexer (233) that selects between an instruction specified immediate field, data recalled from a data register or a mask input from a mask generator (239). One preferred form of the mask has a number of right justified 1's corresponding to a mask input signal. This mask input signal may be the default barrel rotate amount or a predetermined number of the least significant bits of a third input signal as selected by a multiplexer. A second preferred form of the mask is selected one of the left most 1, the right most 1, the left most bit change or the right most bit change of a predetermined set of the least significant bits of data recalled from a data register.
摘要翻译：三输入算术逻辑单元（230），其生成由功能信号选择的三个输入的组合。第二输入信号来自可控筒旋转器（235）。旋转量是存储在特殊数据寄存器中的默认旋转量，从数据寄存器或零调用的预定数据位组。恒定源（236）连接到筒旋转器（235）以提供“1”的多位数字信号。这允许产生形式2N的第二输入信号，其中N是旋转量。桶旋转器（235）的输出可以独立于算术逻辑单元（230）的结果存储。第三输入信号来自多路复用器（233），其在指定的指令字段，从数据寄存器调用的数据或从掩码生成器输入的掩码（239）之间进行选择。掩模的一个优选形式具有对应于掩模输入信号的许多右对齐1。该掩模输入信号可以是由多路复用器选择的默认桶旋转量或第三输入信号的预定数量的最低有效位。选择掩模的第二优选形式是从数据寄存器回调的数据的最低有效位的预定集合的最左1，最右1，最左位变化或最右位变化中的一个。

10. 发明授权

US5761726A Base address generation in a multi-processing system having plural memories with a unified address space corresponding to each processor 失效
标题翻译：在具有与每个处理器对应的统一地址空间的多个存储器的多处理系统中产生基地址
公开(公告)号：US5761726A
公开(公告)日：1998-06-02
申请号：US479981
申请日：1995-06-07
申请人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Philip Moyse
发明人： Karl M. Guttag , Keith Balmer , Robert J. Gove , Christopher J. Read , Jeremiah E. Golston , Sydney W. Poland , Nicholas Ing-Simmons , Philip Moyse
IPC分类号： G06F5/01 , G06F9/302 , G06F9/305 , G06F9/308 , G06F9/315 , G06F9/32 , G06F12/02 , G06F12/00
CPC分类号： G06F9/30014 , G06F12/0284 , G06F5/015 , G06F9/30018 , G06F9/30029 , G06F9/30032 , G06F9/30036 , G06F9/30094 , G06F9/30167 , G06F9/325
摘要： A multi-processing system includes a plurality of memories and a plurality of processors. Each of the memories has a unique addressable memory portion of a single memory address space. Each processors has a predetermined plurality of corresponding memories. These corresponding memories have a corresponding base address within said single memory address space The processors generate addresses for read/write access to data stored within said plurality of memories in accordance with received instructions. A switch matrix connected to the memories and the processors responds to an address generated by a processor to selectively route data between that processor and a memories whose unique addressable memory portion encompasses that address. A base address instruction executing on any one of the processors generates the base address corresponding to that processor. The base address preferably is substituted for the contents of a base address register in an address unit including a set of base address registers, a set of index address registers and a full adder.
摘要翻译：多处理系统包括多个存储器和多个处理器。每个存储器具有单个存储器地址空间的唯一可寻址存储器部分。每个处理器具有预定的多个对应的存储器。这些相应的存储器在所述单个存储器地址空间内具有对应的基址。根据接收到的指令，处理器产生用于对存储在所述多个存储器中的数据进行读/写访问的地址。连接到存储器和处理器的开关矩阵响应由处理器产生的地址，以选择性地在该处理器与其唯一可寻址存储器部分包含该地址的存储器之间路由数据。在任一个处理器上执行的基地址指令产生与该处理器对应的基地址。基址优选地代替包括一组基地址寄存器，一组索引地址寄存器和全加器的地址单元中的基地址寄存器的内容。

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