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1. 发明申请

US20120087184A1 Magnetic Random Access Memory (MRAM) Layout with Uniform Pattern 有权
标题翻译：具有统一图案的磁性随机存取存储器（MRAM）布局
公开(公告)号：US20120087184A1
公开(公告)日：2012-04-12
申请号：US12901074
申请日：2010-10-08
申请人： Kangho Lee , Tae Hyun Kim , Xia Li , Jung Pill Kim , Seung H. Kang
发明人： Kangho Lee , Tae Hyun Kim , Xia Li , Jung Pill Kim , Seung H. Kang
IPC分类号： G11C11/14 , H01R43/00
CPC分类号： G11C5/025 , G11C5/08 , G11C11/165 , H01L27/0207 , Y10T29/49117
摘要： A large scale memory array includes a uniform pattern of uniformly sized dummy bit cells and active bit cells. Sub-arrays within the large scale memory array are separated by the dummy bit cells. Signal distribution circuitry is formed with a width or height corresponding to the width or height of the dummy bit cells so that the signal distribution circuitry occupies the same footprint as the dummy bit cells without disrupting the uniform pattern across the large scale array. Edge dummy cells of a similar size or larger than the standard size bit cells may be placed around the edge of the large scale array to further reduce pattern loading affects.
摘要翻译：大规模存储器阵列包括统一大小的虚拟位单元和有源位单元的均匀图案。大规模存储器阵列中的子阵列由虚拟位单元分隔开。信号分配电路形成为具有对应于虚拟位单元的宽度或高度的宽度或高度，使得信号分配电路占据与虚拟位单元相同的覆盖区，而不会破坏整个大规模阵列上的均匀图案。类似大小或大于标准尺寸位单元的边缘虚拟单元可以放置在大规模阵列的边缘周围，以进一步减少图案负载影响。

2. 发明申请

US20120033490A1 Generating a Non-Reversible State at a Bitcell Having a First Magnetic Tunnel Junction and a Second Magnetic Tunnel Junction 有权
标题翻译：在具有第一磁隧道结和第二磁隧道结的位单元处产生不可逆状态
公开(公告)号：US20120033490A1
公开(公告)日：2012-02-09
申请号：US12849043
申请日：2010-08-03
申请人： Hari M. Rao , Jung Pill Kim , Seung H. Kang , Xiaochun Zhu , Tae Hyun Kim , Kangho Lee , Xia Li , Wah Nam Hsu , Wuyang Hao , Jungwon Suh , Nicholas K. Yu , Matthew Michael Nowak , Steven M. Millendorf , Asaf Ashkenazi
发明人： Hari M. Rao , Jung Pill Kim , Seung H. Kang , Xiaochun Zhu , Tae Hyun Kim , Kangho Lee , Xia Li , Wah Nam Hsu , Wuyang Hao , Jungwon Suh , Nicholas K. Yu , Matthew Michael Nowak , Steven M. Millendorf , Asaf Ashkenazi
IPC分类号： G11C11/14 , G06F17/50 , G11C29/00
CPC分类号： G11C11/16 , G11C11/14 , G11C11/1655 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C17/02 , G11C17/16 , G11C29/027
摘要： A method of generating a non-reversible state at a bitcell having a first magnetic tunnel junction (MTJ) and a second MTJ includes applying a program voltage to the first MTJ of the bitcell without applying the program voltage to the second MTJ of the bitcell. A memory device includes a bitcell having a first MTJ and a second MTJ and programming circuitry configured to generate a non-reversible state at the bitcell by applying a program signal to a selected one of the first MTJ and the second MTJ of the bitcell.
摘要翻译：在具有第一磁性隧道结（MTJ）和第二MTJ的位单元处产生不可逆状态的方法包括将编程电压施加到位单元的第一MTJ，而不将编程电压施加到位单元的第二MTJ。存储器件包括具有第一MTJ和第二MTJ的位单元以及被配置为通过将程序信号施加到位单元的第一MTJ和第二MTJ中的所选择的一个而在位单元处产生不可逆状态的编程电路。

3. 发明授权

US08547736B2 Generating a non-reversible state at a bitcell having a first magnetic tunnel junction and a second magnetic tunnel junction 有权
标题翻译：在具有第一磁性隧道结和第二磁性隧道结的位单元处产生不可逆状态
公开(公告)号：US08547736B2
公开(公告)日：2013-10-01
申请号：US12849043
申请日：2010-08-03
申请人： Hari M. Rao , Jung Pill Kim , Seung H. Kang , Xiaochun Zhu , Tae Hyun Kim , Kangho Lee , Xia Li , Wah Nam Hsu , Wuyang Hao , Jungwon Suh , Nicholas K. Yu , Matthew Michael Nowak , Steven M. Millendorf , Asaf Ashkenazi
发明人： Hari M. Rao , Jung Pill Kim , Seung H. Kang , Xiaochun Zhu , Tae Hyun Kim , Kangho Lee , Xia Li , Wah Nam Hsu , Wuyang Hao , Jungwon Suh , Nicholas K. Yu , Matthew Michael Nowak , Steven M. Millendorf , Asaf Ashkenazi
IPC分类号： G11C11/14
CPC分类号： G11C11/16 , G11C11/14 , G11C11/1655 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C17/02 , G11C17/16 , G11C29/027
摘要： A method of generating a non-reversible state at a bitcell having a first magnetic tunnel junction (MTJ) and a second MTJ includes applying a program voltage to the first MTJ of the bitcell without applying the program voltage to the second MTJ of the bitcell. A memory device includes a bitcell having a first MTJ and a second MTJ and programming circuitry configured to generate a non-reversible state at the bitcell by applying a program signal to a selected one of the first MTJ and the second MTJ of the bitcell.
摘要翻译：在具有第一磁性隧道结（MTJ）和第二MTJ的位单元处产生不可逆状态的方法包括将编程电压施加到位单元的第一MTJ，而不将编程电压施加到位单元的第二MTJ。存储器件包括具有第一MTJ和第二MTJ的位单元以及被配置为通过将程序信号施加到位单元的第一MTJ和第二MTJ中的所选择的一个而在位单元处产生不可逆状态的编程电路。

4. 发明授权

US08441850B2 Magnetic random access memory (MRAM) layout with uniform pattern 有权
标题翻译：具有均匀图案的磁性随机存取存储器（MRAM）布局
公开(公告)号：US08441850B2
公开(公告)日：2013-05-14
申请号：US12901074
申请日：2010-10-08
申请人： Kangho Lee , Tae Hyun Kim , Xia Li , Jung Pill Kim , Seung H. Kang
发明人： Kangho Lee , Tae Hyun Kim , Xia Li , Jung Pill Kim , Seung H. Kang
IPC分类号： G11C11/14
CPC分类号： G11C5/025 , G11C5/08 , G11C11/165 , H01L27/0207 , Y10T29/49117
摘要： A large scale memory array includes a uniform pattern of uniformly sized dummy bit cells and active bit cells. Sub-arrays within the large scale memory array are separated by the dummy bit cells. Signal distribution circuitry is formed with a width or height corresponding to the width or height of the dummy bit cells so that the signal distribution circuitry occupies the same footprint as the dummy bit cells without disrupting the uniform pattern across the large scale array. Edge dummy cells of a similar size or larger than the standard size bit cells may be placed around the edge of the large scale array to further reduce pattern loading affects.
摘要翻译：大规模存储器阵列包括统一大小的虚拟位单元和有源位单元的均匀图案。大规模存储器阵列中的子阵列由虚拟位单元分隔开。信号分配电路形成为具有对应于虚拟位单元的宽度或高度的宽度或高度，使得信号分配电路占据与虚拟位单元相同的覆盖区，而不会破坏整个大规模阵列上的均匀图案。类似大小或大于标准尺寸位单元的边缘虚拟单元可以放置在大规模阵列的边缘周围，以进一步减少图案负载影响。

5. 发明授权

US08638590B2 Resistance based memory having two-diode access device 有权
标题翻译：具有二极管接入装置的基于电阻的存储器
公开(公告)号：US08638590B2
公开(公告)日：2014-01-28
申请号：US12892237
申请日：2010-09-28
申请人： Wuyang Hao , Jungwon Suh , Kangho Lee , Tae Hyun Kim , Jung Pill Kim , Seung H. Kang
发明人： Wuyang Hao , Jungwon Suh , Kangho Lee , Tae Hyun Kim , Jung Pill Kim , Seung H. Kang
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C11/16 , G11C11/1653 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C13/0002 , G11C13/003 , G11C2213/72 , G11C2213/74
摘要： A resistance-based memory has a two-diode access device. In a particular embodiment, a method includes biasing a bit line and a sense line to generate a current through a resistance-based memory element via a first diode or a second diode. A cathode of the first diode is coupled to the bit line and an anode of the second diode is coupled to the sense line.
摘要翻译：基于电阻的存储器具有二极管存取装置。在特定实施例中，一种方法包括偏置位线和感测线以经由第一二极管或第二二极管通过基于电阻的存储器元件产生电流。第一二极管的阴极耦合到位线，并且第二二极管的阳极耦合到感测线。

6. 发明申请

US20120075906A1 Resistance Based Memory Having Two-Diode Access Device 有权
标题翻译：具有二极管接入设备的电阻式存储器
公开(公告)号：US20120075906A1
公开(公告)日：2012-03-29
申请号：US12892237
申请日：2010-09-28
申请人： Wuyang Ho , Jungwon Suh , Kangho Lee , Tae Hyun Kim , Jung Pill Kim , Seung H. Kang
发明人： Wuyang Ho , Jungwon Suh , Kangho Lee , Tae Hyun Kim , Jung Pill Kim , Seung H. Kang
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/0069 , G11C11/16 , G11C11/1653 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C13/0002 , G11C13/003 , G11C2213/72 , G11C2213/74
摘要： A resistance-based memory has a two-diode access device. In a particular embodiment, a method includes biasing a bit line and a sense line to generate a current through a resistance-based memory element via a first diode or a second diode. A cathode of the first diode is coupled to the bit line and an anode of the second diode is coupled to the sense line.
摘要翻译：基于电阻的存储器具有二极管存取装置。在特定实施例中，一种方法包括偏置位线和感测线以经由第一二极管或第二二极管通过基于电阻的存储器元件产生电流。第一二极管的阴极耦合到位线，并且第二二极管的阳极耦合到感测线。

7. 发明授权

US08526266B2 Row-decoder circuit and method with dual power systems 有权
标题翻译：具有双电源系统的行解码器电路和方法
公开(公告)号：US08526266B2
公开(公告)日：2013-09-03
申请号：US13032979
申请日：2011-02-23
申请人： Jung Pill Kim , Tae Hyun Kim , Seung H. Kang
发明人： Jung Pill Kim , Tae Hyun Kim , Seung H. Kang
IPC分类号： G11C8/00
CPC分类号： G11C11/1653 , G11C8/08 , G11C8/10 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1693
摘要： A Spin-Transfer-Torque Magnetic Random Access Memory includes a dual-voltage row decoder with charge sharing for read operations. The dual-voltage row decoder with charge sharing for read operations reduces read-disturbance failure rates and provides a robust macro design with improved yields. Voltage from one of the power supplies can be applied during a write operation.
摘要翻译：旋转转矩磁性随机存取存储器包括具有用于读取操作的电荷共享的双电压行解码器。具有用于读取操作的电荷共享的双电压行解码器可降低读取干扰故障率，并提供强大的宏设计，提高产量。在写入操作期间可以应用来自其中一个电源的电压。

8. 发明申请

US20120188816A1 Row-Decoder Circuit and Method with Dual Power Systems 有权
标题翻译：双电源系统的行解码电路和方法
公开(公告)号：US20120188816A1
公开(公告)日：2012-07-26
申请号：US13032979
申请日：2011-02-23
申请人： Jung Pill Kim , Tae Hyun Kim , Seung H. Kang
发明人： Jung Pill Kim , Tae Hyun Kim , Seung H. Kang
IPC分类号： G11C11/14 , G11C8/08 , G11C7/00
CPC分类号： G11C11/1653 , G11C8/08 , G11C8/10 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1693
摘要： A Spin-Transfer-Torque Magnetic Random Access Memory includes a dual-voltage row decoder with charge sharing for read operations. The dual-voltage row decoder with charge sharing for read operations reduces read-disturbance failure rates and provides a robust macro design with improved yields. Voltage from one of the power supplies can be applied during a write operation.
摘要翻译：旋转转矩磁性随机存取存储器包括具有用于读取操作的电荷共享的双电压行解码器。具有用于读取操作的电荷共享的双电压行解码器可降低读取干扰故障率，并提供强大的宏设计，提高产量。在写入操作期间可以应用来自其中一个电源的电压。

9. 发明授权

US08570797B2 Magnetic random access memory (MRAM) read with reduced disturb failure 有权
标题翻译：磁性随机存取存储器（MRAM）以减少的干扰故障读取
公开(公告)号：US08570797B2
公开(公告)日：2013-10-29
申请号：US13035006
申请日：2011-02-25
申请人： Jung Pill Kim , Tae Hyun Kim , Kangho Lee
发明人： Jung Pill Kim , Tae Hyun Kim , Kangho Lee
IPC分类号： G11C11/14
CPC分类号： G11C11/1673 , G11C11/1693
摘要： Magnetic tunnel junctions (MTJs) in magnetic random access memory (MRAM) are subject to read disturb events when the current passing through the MTJ causes a spontaneous switching of the MTJ due to spin transfer torque (STT) from a parallel state to an anti-parallel state or from an anti-parallel state to a parallel state. Because the state of the MTJ corresponds to stored data, a read disturb event may cause data loss in MRAM devices. Read disturb events may be reduced by controlling the direction of current flow through the MTJ. For example, the current direction through a reference MTJ may be selected based on the state of the reference MTJ. In another example, the current direction through a data or reference MTJ may be alternated such that the MTJ is only subject to read disturb events during approximately half the read operations on the MTJ.
摘要翻译：磁流体随机存取存储器（MRAM）中的磁隧道结（MTJ）在经过MTJ的电流导致由于自旋转移转矩（STT）从平行状态到抗反射的MTJ自发切换时，受到读取干扰事件，平行状态或从反平行状态到并行状态。因为MTJ的状态对应于存储的数据，读取干扰事件可能导致MRAM设备中的数据丢失。通过控制通过MTJ的电流的方向可以减少读取干扰事件。例如，可以基于参考MTJ的状态来选择通过参考MTJ的当前方向。在另一示例中，可以交替通过数据或参考MTJ的当前方向，使得MTJ仅在MTJ上的大约一半的读取操作期间经受读取干扰事件。

10. 发明授权

US08593173B2 Programmable logic sensing in magnetic random access memory 有权
标题翻译：磁性随机存取存储器中的可编程逻辑检测
公开(公告)号：US08593173B2
公开(公告)日：2013-11-26
申请号：US13244962
申请日：2011-09-26
申请人： Jung Pill Kim , Tae Hyun Kim , Wenqing Wu , Xiaochun Zhu , Seung H. Kang
发明人： Jung Pill Kim , Tae Hyun Kim , Wenqing Wu , Xiaochun Zhu , Seung H. Kang
IPC分类号： H03K19/177
CPC分类号： G11C11/16 , G11C13/0069 , H03K19/02 , H03K19/20
摘要： A Magnetic Random Access Memory (MRAM) logic circuit includes read sensing circuitry having a first level corresponding to a first category of logic circuitry and a second logic level corresponding to a second category of logic circuitry. The logic circuitry may be switchable between circuitry having the first logic level and circuitry having the second logic level according to the category of the logic circuit being implemented.
摘要翻译：磁性随机存取存储器（MRAM）逻辑电路包括具有对应于第一类逻辑电路的第一电平的读取感测电路和对应于第二类逻辑电路的第二逻辑电平。逻辑电路可以在具有第一逻辑电平的电路和具有第二逻辑电平的电路之间根据所实现的逻辑电路的类别来切换。

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