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1. 发明授权

US08593173B2 Programmable logic sensing in magnetic random access memory 有权
标题翻译：磁性随机存取存储器中的可编程逻辑检测
公开(公告)号：US08593173B2
公开(公告)日：2013-11-26
申请号：US13244962
申请日：2011-09-26
申请人： Jung Pill Kim , Tae Hyun Kim , Wenqing Wu , Xiaochun Zhu , Seung H. Kang
发明人： Jung Pill Kim , Tae Hyun Kim , Wenqing Wu , Xiaochun Zhu , Seung H. Kang
IPC分类号： H03K19/177
CPC分类号： G11C11/16 , G11C13/0069 , H03K19/02 , H03K19/20
摘要： A Magnetic Random Access Memory (MRAM) logic circuit includes read sensing circuitry having a first level corresponding to a first category of logic circuitry and a second logic level corresponding to a second category of logic circuitry. The logic circuitry may be switchable between circuitry having the first logic level and circuitry having the second logic level according to the category of the logic circuit being implemented.
摘要翻译：磁性随机存取存储器（MRAM）逻辑电路包括具有对应于第一类逻辑电路的第一电平的读取感测电路和对应于第二类逻辑电路的第二逻辑电平。逻辑电路可以在具有第一逻辑电平的电路和具有第二逻辑电平的电路之间根据所实现的逻辑电路的类别来切换。

2. 发明申请

US20130076390A1 Programmable Logic Sensing in Magnetic Random Access Memory 有权
标题翻译：磁性随机存取存储器中的可编程逻辑检测
公开(公告)号：US20130076390A1
公开(公告)日：2013-03-28
申请号：US13244962
申请日：2011-09-26
申请人： Jung Pill Kim , Tae Hyun Kim , Wenqing Wu , Xiaochun Zhu , Seung H. Kang
发明人： Jung Pill Kim , Tae Hyun Kim , Wenqing Wu , Xiaochun Zhu , Seung H. Kang
IPC分类号： H03K19/177 , G11C11/00
CPC分类号： G11C11/16 , G11C13/0069 , H03K19/02 , H03K19/20
摘要： A Magnetic Random Access Memory (MRAM) logic circuit includes read sensing circuitry having a first level corresponding to a first category of logic circuitry and a second logic level corresponding to a second category of logic circuitry. The logic circuitry may be switchable between circuitry having the first logic level and circuitry having the second logic level according to the category of the logic circuit being implemented.
摘要翻译：磁性随机存取存储器（MRAM）逻辑电路包括具有对应于第一类逻辑电路的第一电平的读取感测电路和对应于第二类逻辑电路的第二逻辑电平。逻辑电路可以在具有第一逻辑电平的电路和具有第二逻辑电平的电路之间根据所实现的逻辑电路的类别来切换。

3. 发明申请

US20120033490A1 Generating a Non-Reversible State at a Bitcell Having a First Magnetic Tunnel Junction and a Second Magnetic Tunnel Junction 有权
标题翻译：在具有第一磁隧道结和第二磁隧道结的位单元处产生不可逆状态
公开(公告)号：US20120033490A1
公开(公告)日：2012-02-09
申请号：US12849043
申请日：2010-08-03
申请人： Hari M. Rao , Jung Pill Kim , Seung H. Kang , Xiaochun Zhu , Tae Hyun Kim , Kangho Lee , Xia Li , Wah Nam Hsu , Wuyang Hao , Jungwon Suh , Nicholas K. Yu , Matthew Michael Nowak , Steven M. Millendorf , Asaf Ashkenazi
发明人： Hari M. Rao , Jung Pill Kim , Seung H. Kang , Xiaochun Zhu , Tae Hyun Kim , Kangho Lee , Xia Li , Wah Nam Hsu , Wuyang Hao , Jungwon Suh , Nicholas K. Yu , Matthew Michael Nowak , Steven M. Millendorf , Asaf Ashkenazi
IPC分类号： G11C11/14 , G06F17/50 , G11C29/00
CPC分类号： G11C11/16 , G11C11/14 , G11C11/1655 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C17/02 , G11C17/16 , G11C29/027
摘要： A method of generating a non-reversible state at a bitcell having a first magnetic tunnel junction (MTJ) and a second MTJ includes applying a program voltage to the first MTJ of the bitcell without applying the program voltage to the second MTJ of the bitcell. A memory device includes a bitcell having a first MTJ and a second MTJ and programming circuitry configured to generate a non-reversible state at the bitcell by applying a program signal to a selected one of the first MTJ and the second MTJ of the bitcell.
摘要翻译：在具有第一磁性隧道结（MTJ）和第二MTJ的位单元处产生不可逆状态的方法包括将编程电压施加到位单元的第一MTJ，而不将编程电压施加到位单元的第二MTJ。存储器件包括具有第一MTJ和第二MTJ的位单元以及被配置为通过将程序信号施加到位单元的第一MTJ和第二MTJ中的所选择的一个而在位单元处产生不可逆状态的编程电路。

4. 发明授权

US08547736B2 Generating a non-reversible state at a bitcell having a first magnetic tunnel junction and a second magnetic tunnel junction 有权
标题翻译：在具有第一磁性隧道结和第二磁性隧道结的位单元处产生不可逆状态
公开(公告)号：US08547736B2
公开(公告)日：2013-10-01
申请号：US12849043
申请日：2010-08-03
申请人： Hari M. Rao , Jung Pill Kim , Seung H. Kang , Xiaochun Zhu , Tae Hyun Kim , Kangho Lee , Xia Li , Wah Nam Hsu , Wuyang Hao , Jungwon Suh , Nicholas K. Yu , Matthew Michael Nowak , Steven M. Millendorf , Asaf Ashkenazi
发明人： Hari M. Rao , Jung Pill Kim , Seung H. Kang , Xiaochun Zhu , Tae Hyun Kim , Kangho Lee , Xia Li , Wah Nam Hsu , Wuyang Hao , Jungwon Suh , Nicholas K. Yu , Matthew Michael Nowak , Steven M. Millendorf , Asaf Ashkenazi
IPC分类号： G11C11/14
CPC分类号： G11C11/16 , G11C11/14 , G11C11/1655 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C17/02 , G11C17/16 , G11C29/027
摘要： A method of generating a non-reversible state at a bitcell having a first magnetic tunnel junction (MTJ) and a second MTJ includes applying a program voltage to the first MTJ of the bitcell without applying the program voltage to the second MTJ of the bitcell. A memory device includes a bitcell having a first MTJ and a second MTJ and programming circuitry configured to generate a non-reversible state at the bitcell by applying a program signal to a selected one of the first MTJ and the second MTJ of the bitcell.
摘要翻译：在具有第一磁性隧道结（MTJ）和第二MTJ的位单元处产生不可逆状态的方法包括将编程电压施加到位单元的第一MTJ，而不将编程电压施加到位单元的第二MTJ。存储器件包括具有第一MTJ和第二MTJ的位单元以及被配置为通过将程序信号施加到位单元的第一MTJ和第二MTJ中的所选择的一个而在位单元处产生不可逆状态的编程电路。

5. 发明申请

US20130121066A1 CIRCUIT AND METHOD FOR GENERATING A REFERENCE LEVEL FOR A MAGNETIC RANDOM ACCESS MEMORY ELEMENT 有权
标题翻译：用于产生磁性随机存取元件的参考电平的电路和方法
公开(公告)号：US20130121066A1
公开(公告)日：2013-05-16
申请号：US13293565
申请日：2011-11-10
申请人： Xiaochun Zhu , Xia Li , Wenqing Wu , Jung Pill Kim , Seung H. Kang
发明人： Xiaochun Zhu , Xia Li , Wenqing Wu , Jung Pill Kim , Seung H. Kang
IPC分类号： G11C11/16
CPC分类号： G11C11/16 , G11C5/147 , G11C11/1673
摘要： A method of establishing a reference level includes providing first and second non-overlapping paths from a first node to a second node, providing first and second reference magnetic random access memory (MRAM) elements in the first path, providing third and fourth reference MRAM elements in the second path, measuring a first value indicative of a resistance between the first node and the second node, and setting the reference level based at least in part on the measured value. Also an associated reference circuit.
摘要翻译：建立参考水平的方法包括提供从第一节点到第二节点的第一和第二非重叠路径，在第一路径中提供第一和第二参考磁随机存取存储器（MRAM）元件，提供第三和第四参考MRAM元件在所述第二路径中，测量表示所述第一节点和所述第二节点之间的电阻的第一值，并且至少部分地基于所述测量值来设置所述参考电平。还有一个相关的参考电路。

6. 发明授权

US08804413B2 Multi-free layer MTJ and multi-terminal read circuit with concurrent and differential sensing 有权
标题翻译：多自由层MTJ和具有并发和差分感测的多端读取电路
公开(公告)号：US08804413B2
公开(公告)日：2014-08-12
申请号：US13586934
申请日：2012-08-16
申请人： Xia Li , Wenqing Wu , Jung Pill Kim , Xiaochun Zhu , Seung H. Kang , Raghu Sagar Madala , Kendrick H. Yuen
发明人： Xia Li , Wenqing Wu , Jung Pill Kim , Xiaochun Zhu , Seung H. Kang , Raghu Sagar Madala , Kendrick H. Yuen
IPC分类号： G11C11/14 , G11C11/16 , G11C11/15
CPC分类号： G11C11/16 , G11C11/15 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/5607 , G11C2211/5615 , G11C2211/562 , G11C2211/5633 , H01L27/222 , H01L27/228 , H01L43/08
摘要： A multi-free layer magnetic tunnel junction (MTJ) cell includes a bottom electrode layer, an anti-ferromagnetic layer on the bottom electrode layer, a fixed magnetization layer on the anti-ferromagnetic layer and a barrier layer on the fixed magnetization layer. A first free magnetization layer is on a first area of the barrier layer, and a capping layer is on the first free magnetization layer. A free magnetization layer is on a second area of the barrier layer, laterally displaced from the first area, and a capping layer is on the second free magnetization layer. Optionally current switches establish a read current path including the first free magnetization layer concurrent with not establishing a read current path including the second free magnetization layer. Optionally current switches establishing a read current path including the first and second free magnetization layer.
摘要翻译：多自由层磁隧道结（MTJ）单元包括底电极层，底电极层上的反铁磁层，反铁磁层上的固定磁化层和固定磁化层上的阻挡层。第一自由磁化层位于阻挡层的第一区域上，并且覆盖层位于第一自由磁化层上。自由磁化层在阻挡层的第二区域上，从第一区域横向移位，并且覆盖层位于第二自由磁化层上。可选地，电流开关建立包括第一自由磁化层的读取电流路径，同时不建立包括第二自由磁化层的读取电流路径。可选地，电流开关建立包括第一和第二自由磁化层的读取电流路径。

7. 发明授权

US08576617B2 Circuit and method for generating a reference level for a magnetic random access memory element 有权
标题翻译：用于产生用于磁随机存取存储器元件的参考电平的电路和方法
公开(公告)号：US08576617B2
公开(公告)日：2013-11-05
申请号：US13293565
申请日：2011-11-10
申请人： Xiaochun Zhu , Xia Li , Wenqing Wu , Jung Pill Kim , Seung H. Kang
发明人： Xiaochun Zhu , Xia Li , Wenqing Wu , Jung Pill Kim , Seung H. Kang
IPC分类号： G11C11/00 , G11C11/14
CPC分类号： G11C11/16 , G11C5/147 , G11C11/1673
摘要： A method of establishing a reference level includes providing first and second non-overlapping paths from a first node to a second node, providing first and second reference magnetic random access memory (MRAM) elements in the first path, providing third and fourth reference MRAM elements in the second path, measuring a first value indicative of a resistance between the first node and the second node, and setting the reference level based at least in part on the measured value. Also an associated reference circuit.
摘要翻译：建立参考水平的方法包括提供从第一节点到第二节点的第一和第二非重叠路径，在第一路径中提供第一和第二参考磁随机存取存储器（MRAM）元件，提供第三和第四参考MRAM元件在所述第二路径中，测量表示所述第一节点和所述第二节点之间的电阻的第一值，并且至少部分地基于所述测量值来设置所述参考电平。还有一个相关的参考电路。

8. 发明申请

US20130201757A1 MULTI-FREE LAYER MTJ AND MULTI-TERMINAL READ CIRCUIT WITH CONCURRENT AND DIFFERENTIAL SENSING 有权
标题翻译：多层MTJ和多终端读取电路，具有同步和差分感测
公开(公告)号：US20130201757A1
公开(公告)日：2013-08-08
申请号：US13586934
申请日：2012-08-16
申请人： Xia Li , Wenqing Wu , Jung Pill Kim , Xiaochun Zhu , Seung H. Kang , Raghu Sagar Madala , Kendrick H. Yuen
发明人： Xia Li , Wenqing Wu , Jung Pill Kim , Xiaochun Zhu , Seung H. Kang , Raghu Sagar Madala , Kendrick H. Yuen
IPC分类号： G11C11/14 , H01L29/82
CPC分类号： G11C11/16 , G11C11/15 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/5607 , G11C2211/5615 , G11C2211/562 , G11C2211/5633 , H01L27/222 , H01L27/228 , H01L43/08
摘要： A multi-free layer magnetic tunnel junction (MTJ) cell includes a bottom electrode layer, an anti-ferromagnetic layer on the bottom electrode layer, a fixed magnetization layer on the anti-ferromagnetic layer and a barrier layer on the fixed magnetization layer. A first free magnetization layer is on a first area of the barrier layer, and a capping layer is on the first free magnetization layer. A free magnetization layer is on a second area of the barrier layer, laterally displaced from the first area, and a capping layer is on the second free magnetization layer. Optionally current switches establish a read current path including the first free magnetization layer concurrent with not establishing a read current path including the second free magnetization layer. Optionally current switches establishing a read current path including the first and second free magnetization layer.
摘要翻译：多自由层磁隧道结（MTJ）单元包括底电极层，底电极层上的反铁磁层，反铁磁层上的固定磁化层和固定磁化层上的阻挡层。第一自由磁化层位于阻挡层的第一区域上，并且覆盖层位于第一自由磁化层上。自由磁化层在阻挡层的第二区域上，从第一区域横向移位，并且覆盖层位于第二自由磁化层上。可选地，电流开关建立包括第一自由磁化层的读取电流路径，同时不建立包括第二自由磁化层的读取电流路径。可选地，电流开关建立包括第一和第二自由磁化层的读取电流路径。

9. 发明授权

US08625338B2 Asymmetric write scheme for magnetic bit cell elements 有权
标题翻译：磁位元件的非对称写入方案
公开(公告)号：US08625338B2
公开(公告)日：2014-01-07
申请号：US12755978
申请日：2010-04-07
申请人： Xiaochun Zhu , Hari M. Rao , Jung Pill Kim , Seung H. Kang
发明人： Xiaochun Zhu , Hari M. Rao , Jung Pill Kim , Seung H. Kang
IPC分类号： G11C11/14
CPC分类号： G11C11/1675 , G11C11/16 , G11C11/1659 , G11C11/1693
摘要： Asymmetric switching is defined for magnetic bit cell elements. A magnetic bit cell for memory and other devices includes a transistor coupled to an MTJ structure. A bit line is coupled at one terminal of the bit cell to the MTJ structure. At another terminal of the bit cell, a source line is coupled to the source/drain terminal of the transistor. The bit line is driven by a bit line driver that provides a first voltage. The source line is driven by a source line driver that provides a second voltage. The second voltage is larger than the first voltage. The switching characteristics of the bit cell and MTJ structure are improved and made more reliable by one or a combination of applying the higher second voltage to the source line and/or reducing the overall parasitic resistance in the magnetic bit cell element.
摘要翻译：磁比特元件定义了非对称开关。用于存储器和其它器件的磁位单元包括耦合到MTJ结构的晶体管。位线在位单元的一个端子耦合到MTJ结构。在位单元的另一个端子处，源极线耦合到晶体管的源极/漏极端子。位线由提供第一电压的位线驱动器驱动。源极线由提供第二电压的源极线驱动器驱动。第二电压大于第一电压。通过将较高的第二电压施加到源极线和/或降低磁头单元元件中的整体寄生电阻的一个或组合来提高位单元和MTJ结构的开关特性并使其变得更可靠。

10. 发明申请

US20120218805A1 Configurable Memory Array 有权
标题翻译：可配置内存阵列
公开(公告)号：US20120218805A1
公开(公告)日：2012-08-30
申请号：US13034763
申请日：2011-02-25
申请人： Jung Pill Kim , Hari M. Rao , Xiaochun Zhu , Xia Li , Seung H. Kang
发明人： Jung Pill Kim , Hari M. Rao , Xiaochun Zhu , Xia Li , Seung H. Kang
IPC分类号： G11C5/06 , H05K13/00 , G11C29/08 , G11C11/00 , G11C7/00
CPC分类号： G11C11/1677 , G11C8/08 , G11C8/14 , G11C11/16 , G11C11/161 , G11C29/18 , G11C29/30 , G11C2029/1202 , G11C2029/2602 , H01L43/12
摘要： Embodiments disclosed include a memory array having a plurality of bit lines and a plurality of source lines disposed in columns. A plurality of word lines is disposed in rows. A plurality of storage elements have a first subset of storage elements electrically decoupled from the memory array and a second subset of storage elements coupled to the memory array. The memory array further includes a plurality of bit cells, each including one storage element from the second subset of storage elements coupled to at least two transistors. The bit cells are coupled to the plurality of bit lines and the plurality source lines. Each transistor is coupled to one word line. The memory array can further include logic to select a high performance mode and a high density mode.
摘要翻译：所公开的实施例包括具有多个位线和多个排列成列的源极线的存储器阵列。多行字线被排列成行。多个存储元件具有与存储器阵列电分离的存储元件的第一子集和耦合到存储器阵列的存储元件的第二子集。存储器阵列还包括多个位单元，每个位单元包括来自耦合到至少两个晶体管的存储元件的第二子集的一个存储元件。位单元耦合到多个位线和多个源极线。每个晶体管耦合到一个字线。存储器阵列还可以包括选择高性能模式和高密度模式的逻辑。

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