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1. 发明申请

US20140024215A1 DOUBLE PATTERNING METHOD 有权
标题翻译：双重图案方法
公开(公告)号：US20140024215A1
公开(公告)日：2014-01-23
申请号：US13555306
申请日：2012-07-23
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ying Zhang
IPC分类号： B44C1/22 , H01B13/00 , H01L21/308
CPC分类号： H01L21/3086 , H01B13/00 , H01B19/04 , H01L21/0337 , H01L21/3081 , H01L21/32134 , H01L21/32137
摘要： Disclosed is an improved double patterning method for forming openings (e.g., vias or trenches) or mesas on a substrate. This method avoids the wafer topography effects seen in prior art double patterning techniques by ensuring that the substrate itself is only subjected to a single etch process. Specifically, in the method, a first mask layer is formed on the substrate and processed such that it has a doped region and multiple undoped regions within the doped region. Then, either the undoped regions or the doped region can be selectively removed in order to form a mask pattern above the substrate. Once the mask pattern is formed, an etch process can be performed to transfer the mask pattern into the substrate. Depending upon whether the undoped regions are removed or the doped region is removed, the mask pattern will form openings (e.g., vias or trenches) or mesas, respectively, on the substrate.
摘要翻译：公开了一种用于在基板上形成开口（例如，通孔或沟槽）或台面的改进的双重图案化方法。该方法通过确保衬底本身仅经历单次蚀刻工艺来避免现有技术的双重图案化技术中所见到的晶片形貌效应。具体地说，在该方法中，在衬底上形成第一掩模层并进行处理，使得其在掺杂区域内具有掺杂区域和多个未掺杂区域。然后，可以选择性地去除未掺杂区域或掺杂区域，以在衬底上方形成掩模图案。一旦形成掩模图案，就可以执行蚀刻工艺以将掩模图案转印到基板中。取决于未掺杂的区域是去除还是去除掺杂区域，掩模图案将分别在衬底上形成开口（例如，通孔或沟槽）或台面。

2. 发明授权

US08889562B2 Double patterning method 有权
标题翻译：双重图案化方法
公开(公告)号：US08889562B2
公开(公告)日：2014-11-18
申请号：US13555306
申请日：2012-07-23
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ying Zhang
IPC分类号： H01L21/302
CPC分类号： H01L21/3086 , H01B13/00 , H01B19/04 , H01L21/0337 , H01L21/3081 , H01L21/32134 , H01L21/32137
摘要： Disclosed is an improved double patterning method for forming openings (e.g., vias or trenches) or mesas on a substrate. This method avoids the wafer topography effects seen in prior art double patterning techniques by ensuring that the substrate itself is only subjected to a single etch process. Specifically, in the method, a first mask layer is formed on the substrate and processed such that it has a doped region and multiple undoped regions within the doped region. Then, either the undoped regions or the doped region can be selectively removed in order to form a mask pattern above the substrate. Once the mask pattern is formed, an etch process can be performed to transfer the mask pattern into the substrate. Depending upon whether the undoped regions are removed or the doped region is removed, the mask pattern will form openings (e.g., vias or trenches) or mesas, respectively, on the substrate.
摘要翻译：公开了一种用于在基板上形成开口（例如，通孔或沟槽）或台面的改进的双重图案化方法。该方法通过确保衬底本身仅经历单次蚀刻工艺来避免现有技术的双重图案化技术中所见到的晶片形貌效应。具体地说，在该方法中，在衬底上形成第一掩模层并进行处理，使得其在掺杂区域内具有掺杂区域和多个未掺杂区域。然后，可以选择性地去除未掺杂区域或掺杂区域，以在衬底上方形成掩模图案。一旦形成掩模图案，就可以执行蚀刻工艺以将掩模图案转印到基板中。取决于未掺杂的区域是去除还是去除掺杂区域，掩模图案将分别在衬底上形成开口（例如，通孔或沟槽）或台面。

3. 发明授权

US09054211B2 Compressively stressed FET device structures 有权
标题翻译：压应力FET器件结构
公开(公告)号：US09054211B2
公开(公告)日：2015-06-09
申请号：US13540801
申请日：2012-07-03
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L27/088 , H01L21/8234 , H01L21/8238 , H01L29/66 , H01L29/78
CPC分类号： H01L21/823431 , H01L21/823412 , H01L21/823807 , H01L21/823821 , H01L29/66795 , H01L29/7843 , H01L29/7846 , H01L29/785
摘要： An FET device structure has a Fin-FET device with a fin of a Si based material. An oxide element is abutting the fin and exerts pressure onto the fin. The Fin-FET device channel is compressively stressed due to the pressure on the fin. A further FET device structure has Fin-FET devices in a row. An oxide element extending perpendicularly to the row of fins is abutting the fins and exerts pressure onto the fins. Device channels of the Fin-FET devices are compressively stressed due to the pressure on the fins.
摘要翻译： FET器件结构具有具有Si基材料的翅片的Fin-FET器件。氧化物元件邻接翅片并对翅片施加压力。 Fin-FET器件通道由于鳍上的压力而受到压缩应力。另外的FET器件结构具有Fin-FET器件。垂直于翅片排延伸的氧化物元件邻接散热片并对翅片施加压力。 Fin-FET器件的器件通道由于鳍片上的压力而受到压缩应力。

4. 发明授权

US08994085B2 Integrated circuit including DRAM and SRAM/logic 有权
标题翻译：集成电路包括DRAM和SRAM /逻辑
公开(公告)号：US08994085B2
公开(公告)日：2015-03-31
申请号：US13551714
申请日：2012-07-18
申请人： Veeraraghavan S. Basker , Kangguo Cheng , Bruce B. Doris , Terence B. Hook , Ali Khakifirooz , Pranita Kulkarni , Tenko Yamashita , Chun-Chen Yeh
发明人： Veeraraghavan S. Basker , Kangguo Cheng , Bruce B. Doris , Terence B. Hook , Ali Khakifirooz , Pranita Kulkarni , Tenko Yamashita , Chun-Chen Yeh
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119 , H01L21/84 , H01L27/11 , H01L27/12
CPC分类号： H01L21/84 , H01L27/10861 , H01L27/1087 , H01L27/10873 , H01L27/10894 , H01L27/10897 , H01L27/1108 , H01L27/1116 , H01L27/1203 , H01L29/945
摘要： An integrated circuit comprising an N+ type layer, a buffer layer arranged on the N+ type layer; a P type region formed on with the buffer layer; an insulator layer overlying the N+ type layer, a silicon layer overlying the insulator layer, an embedded RAM FET formed in the silicon layer and connected with a conductive node of a trench capacitor that extends into the N+ type layer, the N+ type layer forming a plate electrode of the trench capacitor, a first contact through the silicon layer and the insulating layer and electrically connecting to the N+ type layer, a first logic RAM FET formed in the silicon layer above the P type region, the P type region functional as a P-type back gate of the first logic RAM FET, and a second contact through the silicon layer and the insulating layer and electrically connecting to the P type region.
摘要翻译：一种集成电路，包括N +型层，设置在N +型层上的缓冲层; 形成在缓冲层上的P型区域; 覆盖N +型层的绝缘体层，覆盖绝缘体层的硅层，形成在硅层中并与延伸到N +型层的沟槽电容器的导电节点连接的嵌入式RAM FET，N +型层形成沟槽电容器的平板电极，通过硅层和绝缘层的第一接触并且电连接到N +型层，形成在P型区域上方的硅层中的第一逻辑RAM FET，P型区域用作第一逻辑RAM FET的P型背栅，以及通过硅层和绝缘层的第二接触，并且电连接到P型区域。

5. 发明授权

US08653596B2 Integrated circuit including DRAM and SRAM/logic 有权
标题翻译：集成电路包括DRAM和SRAM /逻辑
公开(公告)号：US08653596B2
公开(公告)日：2014-02-18
申请号：US13344885
申请日：2012-01-06
申请人： Kangguo Cheng , Bruce B. Doris , Terence B. Hook , Ali Khakifirooz , Pranita Kulkarni
发明人： Kangguo Cheng , Bruce B. Doris , Terence B. Hook , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L21/70 , H01L27/12 , H01L21/762 , H01L21/84
CPC分类号： H01L29/945 , H01L21/84 , H01L27/1052 , H01L27/1087 , H01L27/10873 , H01L27/10894 , H01L27/1116 , H01L27/1203 , H01L27/1207
摘要： An integrated circuit includes an SOI substrate with a unitary N+ layer below the BOX, a P region in the N+ layer, an eDRAM with an N+ plate, and logic/SRAM devices above the P region. The P region functions as a back gate of the logic/SRAM devices. An optional intrinsic (undoped) layer can be formed between the P back gate layer and the N+ layer to reduce the junction field and lower the junction leakage between the P back gate and the N+ layer. In another embodiment an N or N+ back gate can be formed in the P region. The N+ back gate functions as a second back gate of the logic/SRAM devices. The N+ plate of the SOI eDRAM, the P back gate, and the N+ back gate can be electrically biased at the same or different voltage potentials. Methods to fabricate the integrated circuits are also disclosed.
摘要翻译：集成电路包括在BOX下方具有单一N +层的SOI衬底，N +层中的P区，N +板的eDRAM和P区上方的逻辑/ SRAM器件。 P区域用作逻辑/ SRAM器件的后门。可以在P背栅层和N +层之间形成可选的本征（未掺杂）层，以减少结场并降低P背栅与N +层之间的结泄漏。在另一个实施例中，可以在P区中形成N或N +背栅。 N +后门作为逻辑/ SRAM器件的第二个后门。 SOI eDRAM的N +板，P背栅极和N +背栅极可以在相同或不同的电压电位下被电偏置。还公开了制造集成电路的方法。

6. 发明授权

US08629504B2 Extremely thin semiconductor-on-insulator (ETSOI) integrated circuit with on-chip resistors and method of forming the same 有权
标题翻译：具有片上电阻的非常薄的绝缘体上半导体（ETSOI）集成电路及其形成方法
公开(公告)号：US08629504B2
公开(公告)日：2014-01-14
申请号：US13433401
申请日：2012-03-29
申请人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Ghavam G. Shahidi
发明人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Ghavam G. Shahidi
IPC分类号： H01L21/00
CPC分类号： H01L27/1214 , H01L21/84 , H01L27/1203 , H01L27/13
摘要： An electrical device is provided that in one embodiment includes a semiconductor-on-insulator (SOI) substrate having a semiconductor layer with a thickness of less than 10 nm. A semiconductor device having a raised source region and a raised drain region of a single crystal semiconductor material of a first conductivity is present on a first surface of the semiconductor layer. A resistor composed of the single crystal semiconductor material of the first conductivity is present on a second surface of the semiconductor layer. A method of forming the aforementioned electrical device is also provided.
摘要翻译：提供了一种电气装置，其在一个实施例中包括具有厚度小于10nm的半导体层的绝缘体上半导体（SOI）基板。在半导体层的第一表面上存在具有第一导电性的单晶半导体材料的升高的源极区域和升高的漏极区域的半导体器件。由第一导电性的单晶半导体材料构成的电阻器存在于半导体层的第二表面上。还提供了形成上述电气装置的方法。

7. 发明申请

US20130344677A1 SHALLOW TRENCH ISOLATION STRUCTURES 有权
公开(公告)号：US20130344677A1
公开(公告)日：2013-12-26
申请号：US13531780
申请日：2012-06-25
申请人： Bruce B. Doris , Kangguo Cheng , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni , Arvind Kumar , Shom Ponoth
发明人： Bruce B. Doris , Kangguo Cheng , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni , Arvind Kumar , Shom Ponoth
IPC分类号： H01L21/762
CPC分类号： H01L29/0649 , H01L21/76224 , H01L21/76283
摘要： Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate.

8. 发明申请

US20130341754A1 SHALLOW TRENCH ISOLATION STRUCTURES 有权
公开(公告)号：US20130341754A1
公开(公告)日：2013-12-26
申请号：US13531654
申请日：2012-06-25
申请人： Bruce B. Doris , Kangguo Cheng , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni , Arvind Kumar , Shom Ponoth
发明人： Bruce B. Doris , Kangguo Cheng , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni , Arvind Kumar , Shom Ponoth
IPC分类号： H01L29/06
CPC分类号： H01L29/0649 , H01L21/76224 , H01L21/76283
摘要： Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate.

9. 发明授权

US08587086B2 Self-aligned dual depth isolation and method of fabrication 失效
标题翻译：自对准双深度隔离和制造方法
公开(公告)号：US08587086B2
公开(公告)日：2013-11-19
申请号：US13598992
申请日：2012-08-30
申请人： Kangguo Cheng , Robert Heath Dennard , Bruce B. Doris , Ali Khakifirooz , Ghavam G. Shahidi
发明人： Kangguo Cheng , Robert Heath Dennard , Bruce B. Doris , Ali Khakifirooz , Ghavam G. Shahidi
IPC分类号： H01L21/70
CPC分类号： H01L21/84 , H01L21/3086 , H01L21/76283 , H01L27/1104
摘要： FDSOI devices and methods for the fabrication thereof are provided. In one aspect, a method for fabricating a device includes the following steps. A wafer is provided having a substrate, a BOX and a SOI layer. A hardmask layer is deposited over the SOI layer. A photoresist layer is deposited over the hardmask layer and patterned into groups of segments. A tilted implant is performed to damage all but those portions of the hardmask layer covered or shadowed by the segments. Portions of the hardmask layer damaged by the implant are removed. A first etch is performed through the hardmask layer to form a deep trench in the SOI layer, the BOX and at least a portion of the substrate. The hardmask layer is patterned using the patterned photoresist layer. A second etch is performed through the hardmask layer to form shallow trenches in the SOI layer.
摘要翻译：提供了FDSOI器件及其制造方法。一方面，一种制造装置的方法包括以下步骤。提供具有基板，BOX和SOI层的晶片。硬掩模层沉积在SOI层上。光致抗蚀剂层沉积在硬掩模层上并且被图案化成一组片段。执行倾斜的植入物以损坏被片段覆盖或遮蔽的硬掩模层的所有部分。移除由植入物损坏的硬掩模层的部分。通过硬掩模层执行第一蚀刻，以在SOI层，BOX和衬底的至少一部分中形成深沟槽。使用图案化的光致抗蚀剂层对硬掩模层进行图案化。通过硬掩模层进行第二蚀刻，以在SOI层中形成浅沟槽。

10. 发明申请

US20130270627A1 FinFET NON-VOLATILE MEMORY AND METHOD OF FABRICATION 失效
标题翻译： FinFET非易失性存储器和制造方法
公开(公告)号：US20130270627A1
公开(公告)日：2013-10-17
申请号：US13444219
申请日：2012-04-11
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L27/12 , H01L21/336
CPC分类号： H01L21/823431 , H01L21/28273 , H01L21/28282 , H01L21/845 , H01L27/11521 , H01L27/11524 , H01L27/11568 , H01L27/1157 , H01L29/42328 , H01L29/42332 , H01L29/42344 , H01L29/66795 , H01L29/66825 , H01L29/66833 , H01L29/785 , H01L29/7881 , H01L29/792
摘要： A method of manufacturing a FinFET non-volatile memory device and a FinFET non-volatile memory device structure. A substrate is provided and a layer of semiconductor material is deposited over the substrate. A hard mask is deposited over the semiconductor material and the structure is patterned to form fins. A charge storage layer is deposited over the structure, including the fins and the portions of it are damaged using an angled ion implantation process. The damaged portions are removed and gate structures are formed on either side of the fin, with only one side having a charge storage layer.
摘要翻译：一种制造FinFET非易失性存储器件和FinFET非易失性存储器件结构的方法。提供衬底并且在衬底上沉积半导体材料层。在半导体材料上沉积硬掩模，并且将该结构图案化以形成翅片。电荷存储层沉积在结构上，包括鳍片，并且其部分使用成角度的离子注入工艺被损坏。损坏的部分被去除并且栅极结构形成在翅片的任一侧，只有一侧具有电荷存储层。

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